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📄 rxpll.asm

📁 MIMO 2x2接收端选择全系统仿真代码
💻 ASM
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           LDW     .D1T1   *+A13(4),A0
||         SUB     .S1     A1,A0,A3

           STW     .D2T1   A3,*+SP(152)
           NOP             3
           STW     .D2T1   A0,*+SP(156)
           LDW     .D2T2   *+SP(136),B3
	.line	26

           MVKL    .S2     0x3f278d37,B4
||         MVKL    .S1     _cos_table,A0

           MVKH    .S2     0x3f278d37,B4
||         MVKH    .S1     _cos_table,A0

           MV      .D1     A1,A0
||         STW     .D2T2   B4,*+SP(160)
||         MV      .S2X    A0,B11

           ZERO    .D1     A12
||         STW     .D2T1   A0,*+SP(164)      ; |115| 

	.line	6
           ZERO    .D1     A14               ; |95| 
	.line	24
           ZERO    .D1     A0                ; |113| 
           STW     .D2T1   A0,*+SP(168)      ; |113| 
	.line	18
;** --------------------------------------------------------------------------*
;**   BEGIN LOOP L1
;** --------------------------------------------------------------------------*
L1:    
;**	-----------------------g3:
;** 129	-----------------------    C$11 = (short)(V$1*factor_1);
;** 129	-----------------------    Ileft[pos] = K$27[C$11]**(++U$31);
;** 130	-----------------------    Qleft[pos] = K$27[_extu((unsigned)C$11+K$40, 21u, 21u)]**U$31;
;** 136	-----------------------    // LOOP BELOW UNROLLED BY FACTOR(2)
;** 136	-----------------------    I$4 = K$50;
;** 136	-----------------------    I$3 = I$4;
;** 136	-----------------------    I$2 = I$3;
;** 136	-----------------------    I$1 = I$2;
;**  	-----------------------    U$61 = (unsigned)pos;
;** 136	-----------------------    L$2 = 8;
;**  	-----------------------    U$59 = &lpf_coeff[-2];
;** 136	-----------------------    k = 0u;
;**  	-----------------------    #pragma MUST_ITERATE(8, 8, 8)
;**  	-----------------------    #pragma LOOP_FLAGS(4098u)
;**	-----------------------g5:
;** 141	-----------------------    C$8 = U$61-k;
;** 141	-----------------------    C$10 = C$8&0xfu;
;** 141	-----------------------    C$9 = *(U$59 += 2);
;** 141	-----------------------    I$1 += Ileft[C$10]*C$9;
;** 142	-----------------------    I$3 += Qleft[C$10]*C$9;
;** 141	-----------------------    C$7 = C$8+K$79&0xfu;
;** 141	-----------------------    C$6 = U$59[1];
;** 141	-----------------------    I$2 += Ileft[C$7]*C$6;
;** 142	-----------------------    I$4 += Qleft[C$7]*C$6;
;** 143	-----------------------    k += 2u;
;** 143	-----------------------    if ( --L$2 ) goto g5;
	.line	40
           MPYSP   .M2     B13,B3,B4         ; |129| 
           LDW     .D2T1   *+SP(148),A3      ; |129| 
           NOP             2
           SPTRUNC .L2     B4,B4             ; |129| 
           NOP             3
           EXT     .S2     B4,16,16,B4       ; |129| 

           LDW     .D1T1   *++A3,A0          ; |129| 
||         LDW     .D2T2   *+B11[B4],B5      ; |129| 

           STW     .D2T1   A3,*+SP(148)      ; |129| 
           ADD     .S1X    4,SP,A3           ; |129| 
           NOP             2
           MPYSP   .M1X    A0,B5,A0          ; |129| 
           NOP             3
           STW     .D1T1   A0,*+A3[A14]      ; |129| 
	.line	41
           LDW     .D2T1   *+SP(148),A0      ; |130| 
           MVK     .S2     0xfffffe00,B5
           ADD     .D2     B5,B4,B4          ; |130| 
           EXTU    .S2     B4,21,21,B4       ; |130| 
           LDW     .D2T2   *+B11[B4],B4      ; |130| 
           LDW     .D1T1   *A0,A0            ; |130| 
           NOP             4
           MPYSP   .M1X    A0,B4,A0          ; |130| 
           ADDAW   .D2     SP,17,B4          ; |130| 
           MV      .S1X    B4,A3             ; |130| Define a twin register
           NOP             1
           STW     .D1T1   A0,*+A3[A14]      ; |130| 
	.line	47
           MVK     .S2     0x2,B1            ; init prolog collapse predicate
           MVK     .S2     6,B0              ; |136| 
           MVKL    .S2     _lpf_coeff-8,B4
           MVC     .S2     CSR,B10

           ZERO    .D1     A6                ; |136| 
||         MV      .S1     A14,A11
||         AND     .L2     -2,B10,B5
||         MVKH    .S2     _lpf_coeff-8,B4

           MV      .D1     A12,A10           ; |136| 
||         ZERO    .D2     B2
||         SUB     .L1     A11,A6,A5         ; |141| (P) <0,0> 
||         MV      .S1X    B4,A0
||         MVC     .S2     B5,CSR            ; interrupts off

;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*
;*      Loop source line                 : 136
;*      Loop opening brace source line   : 137
;*      Loop closing brace source line   : 143
;*      Loop Unroll Multiple             : 2x
;*      Known Minimum Trip Count         : 8
;*      Known Maximum Trip Count         : 8
;*      Known Max Trip Count Factor      : 8
;*      Loop Carried Dependency Bound(^) : 4
;*      Unpartitioned Resource Bound     : 4
;*      Partitioned Resource Bound(*)    : 5
;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     3        1     
;*      .S units                     0        1     
;*      .D units                     4        4     
;*      .M units                     3        1     
;*      .X cross paths               4        3     
;*      .T address paths             4        2     
;*      Long read paths              0        0     
;*      Long write paths             0        0     
;*      Logical  ops (.LS)           3        2     (.L or .S unit)
;*      Addition ops (.LSD)          3        2     (.L or .S or .D unit)
;*      Bound(.L .S .LS)             3        2     
;*      Bound(.L .S .D .LS .LSD)     5*       4     
;*
;*      Searching for software pipeline schedule at ...
;*         ii = 5  Register is live too long
;*         ii = 5  Register is live too long
;*         ii = 5  Schedule found with 4 iterations in parallel
;*      Done
;*
;*      Epilog not removed
;*      Collapsed epilog stages     : 0
;*
;*      Prolog not entirely removed
;*      Collapsed prolog stages     : 2
;*
;*      Minimum required memory pad : 0 bytes
;*
;*      For further improvement on this loop, try option -mh16
;*
;*      Minimum safe trip count     : 3 (after unrolling)
;*----------------------------------------------------------------------------*
L2:    ; PIPED LOOP PROLOG

           MV      .L1     A12,A2            ; |136| 
||         MVKH    .S2     0x10000,B2        ; init prolog collapse predicate
||         ADD     .S1X    4,SP,A3           ; |141| (P) <0,1> 
||         AND     .L2X    15,A5,B4          ; |141| (P) <0,1> 
||         LDW     .D1T1   *++A0(8),A1       ; |141| (P) <0,1> 

           MV      .D1     A12,A7            ; |136| 
||         MV      .L2X    A12,B4            ; |136| 
||         ADDAW   .D2     SP,17,B5          ; |142| (P) <0,2> 
||         ADD     .L1     A8,A5,A9          ; |141| (P) <0,2> 
||         MV      .S1X    B4,A4             ; |141| (P) <0,2> Define a twin register
||         B       .S2     L3                ; |143| (P) <0,12> 

;** --------------------------------------------------------------------------*
L3:    ; PIPED LOOP KERNEL

   [!B1]   ADDSP   .L1     A7,A2,A2          ; |141| <0,13>  ^ 
||         MPYSP   .M1     A1,A5,A4          ; |141| <1,8> 
||         ADDAW   .D2     SP,17,B7          ; |142| <2,3> 
||         ADD     .L2     4,SP,B5           ; |141| <2,3> 
||         MV      .S1X    B5,A3             ; |142| <2,3> Define a twin register
||         AND     .S2X    15,A9,B9          ; |141| <2,3> 
||         LDW     .D1T1   *+A3[A4],A5       ; |141| <2,3> 

   [!B1]   ADDSP   .L2     B8,B4,B4          ; |142| <0,14>  ^ 
|| [!B1]   ADDSP   .L1     A5,A10,A10        ; |142| <0,14>  ^ 
|| [!B2]   MPYSP   .M1X    A9,B6,A7          ; |141| <1,9> 
||         ADD     .S1     2,A6,A6           ; |143| <2,4> 
||         LDW     .D1T1   *+A0(4),A9        ; |141| <2,4> 
||         LDW     .D2T2   *+B5[B9],B6       ; |141| <2,4> 

           MPYSP   .M1     A1,A5,A5          ; |142| <1,10> 
||         MPYSP   .M2X    A9,B5,B8          ; |142| <1,10> 
||         LDW     .D2T2   *+B7[B9],B5       ; |142| <2,5> 
||         LDW     .D1T1   *+A3[A4],A5       ; |142| <2,5> 
||         SUB     .S1     A11,A6,A5         ; |141| <3,0> 

   [ B2]   MPYSU   .M2     2,B2,B2           ; <0,16> 
|| [ B1]   SUB     .D2     B1,1,B1           ; <0,16> 
|| [ B0]   SUB     .L2     B0,1,B0           ; |143| <1,11> 
||         LDW     .D1T1   *++A0(8),A1       ; |141| <3,1> 
||         ADD     .S1X    4,SP,A3           ; |141| <3,1> 
||         AND     .S2X    15,A5,B5          ; |141| <3,1> 

   [ B0]   B       .S2     L3                ; |143| <1,12> 
|| [!B2]   ADDSP   .L1     A4,A7,A7          ; |141| <1,12>  ^ 
||         ADDAW   .D2     SP,17,B5          ; |142| <3,2> 
||         ADD     .D1     A8,A5,A9          ; |141| <3,2> 
||         MV      .S1X    B5,A4             ; |141| <3,2> Define a twin register

;** --------------------------------------------------------------------------*
L4:    ; PIPED LOOP EPILOG
;** 145	-----------------------    pos = pos+1&0xf;
;** 148	-----------------------    C$5 = I$1+I$2;
;** 148	-----------------------    if ( C$5 == K$50 ) goto g8;
;** 149	-----------------------    phase_diff = -(I$3+I$4)*_rcpsp(C$5);
;**	-----------------------g8:
;** 153	-----------------------    loop_filter_output = (U$107*loop_filter_output+U$109*phase_diff)*U$106;
;** 155	-----------------------    if ( !((i >= K$114)&(i < uiBuffLen)) ) goto g10;
;** 155	-----------------------    pPLLparam->delta_avg = V$0 += loop_filter_output;
;**	-----------------------g10:
;** 158	-----------------------    pPLLparam->theta = V$1 += loop_filter_output+K$121;
;** 160	-----------------------    if ( V$1 < K$7 ) goto g15;
;**  	-----------------------    #pragma LOOP_FLAGS(4096u)

           MPYSP   .M1     A1,A5,A0          ; |141| (E) <2,8> 
||         ADDAW   .D2     SP,17,B7          ; |142| (E) <3,3> 
||         ADD     .L2     4,SP,B5           ; |141| (E) <3,3> 
||         MV      .S1X    B5,A3             ; |142| (E) <3,3> Define a twin register
||         AND     .S2X    15,A9,B9          ; |141| (E) <3,3> 
||         LDW     .D1T1   *+A3[A4],A4       ; |141| (E) <3,3> 
||         ADDSP   .L1     A7,A2,A3          ; |141| (E) <1,13>  ^ 

           ADDSP   .L2     B8,B4,B4          ; |142| (E) <1,14>  ^ 
||         MPYSP   .M1X    A9,B6,A5          ; |141| (E) <2,9> 
||         ADD     .S1     2,A6,A6           ; |143| (E) <3,4> 
||         LDW     .D1T1   *+A0(4),A9        ; |141| (E) <3,4> 
||         LDW     .D2T2   *+B5[B9],B5       ; |141| (E) <3,4> 
||         ADDSP   .L1     A5,A10,A0         ; |142| (E) <1,14>  ^ 

           MPYSP   .M1     A1,A5,A3          ; |142| (E) <2,10> 
||         LDW     .D2T2   *+B7[B9],B4       ; |142| (E) <3,5> 
||         LDW     .D1T1   *+A3[A4],A0       ; |142| (E) <3,5> 
||         MPYSP   .M2X    A9,B5,B6          ; |142| (E) <2,10> 

           NOP             1
           ADDSP   .L1     A0,A7,A0          ; |141| (E) <2,12>  ^ 

           ADDSP   .L1     A5,A3,A4          ; |141| (E) <2,13>  ^ 
||         MPYSP   .M1     A1,A4,A3          ; |141| (E) <3,8> 

           ADDSP   .L2     B6,B4,B4          ; |142| (E) <2,14>  ^ 
||         MPYSP   .M1X    A9,B5,A0          ; |141| (E) <3,9> 
||         ADDSP   .L1     A3,A0,A3          ; |142| (E) <2,14>  ^ 

           MPYSP   .M2X    A9,B4,B5          ; |142| (E) <3,10> 
||         MPYSP   .M1     A1,A0,A0          ; |142| (E) <3,10> 

           NOP             1
           ADDSP   .L1     A3,A0,A0          ; |141| (E) <3,12>  ^ 
           ADDSP   .L1     A0,A4,A0          ; |141| (E) <3,13>  ^ 

           ADDSP   .L1     A0,A3,A10         ; |142| (E) <3,14>  ^ 
||         ADDSP   .L2     B5,B4,B4          ; |142| (E) <3,14>  ^ 

           NOP             1

           MV      .L2X    A0,B5
||         MVC     .S2     B10,CSR           ; interrupts on

;** --------------------------------------------------------------------------*
           MV      .S2X    A0,B6
           MV      .S1X    B4,A3
	.line	56
           ADD     .D1     1,A14,A0          ; |145| 
           AND     .S1     15,A0,A0          ; |145| 
           EXT     .S1     A0,16,16,A14      ; |145| 
	.line	59
           ADDSP   .L2     B6,B5,B5          ; |148| 
           NOP             3
           CMPEQSP .S2X    B5,A12,B0         ; |148| 
	.line	60

   [!B0]   ZERO    .D2     B4                ; |149| 
|| [!B0]   ADDSP   .L1     A3,A10,A0         ; |149| 

   [!B0]   SET     .S2     B4,31,31,B4       ; |149| 
           NOP             2

   [!B0]   RCPSP   .S2     B5,B4             ; |149| 
|| [!B0]   XOR     .S1X    A0,B4,A0          ; |149| 

   [!B0]   MPYSP   .M1X    B4,A0,A0          ; |149| 
           NOP             3
   [!B0]   STW     .D2T1   A0,*+SP(172)      ; |149| 
	.line	64
           LDW     .D2T1   *+SP(136),A0
           LDW     .D2T1   *+SP(172),A3      ; |153| 
           LDW     .D2T1   *+SP(156),A4      ; |153| 
           LDW     .D2T1   *+SP(140),A5
           LDW     .D2T1   *+SP(144),A6
           NOP             2
           MPYSP   .M1     A3,A4,A3          ; |153| 
           MPYSP   .M1     A0,A5,A0          ; |153| 

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