emhwlib_registers_tango15.h

1. 8623L平台

#define VO_component_out_conv2 0x1008 /* width RMuint32 */
#define VO_component_out_conv3 0x100c /* width RMuint32 */
#define VO_component_out_conv4 0x1010 /* width RMuint32 */
#define VO_component_out_conv5 0x1014 /* width RMuint32 */
#define VO_component_out_xoffset_field 0x1018 /* width RMuint32 */
#define VO_component_out_yoffset 0x101c /* width RMuint32 */
#define VO_component_out_TV_config 0x1040 /* width RMuint32 */
#define VO_component_out_TV_size 0x1044 /* width RMuint32 */
#define VO_component_out_TV_hsync 0x1048 /* width RMuint32 */
#define VO_component_out_TV_vsync_O_0 0x104c /* width RMuint32 */
#define VO_component_out_TV_vsync_O_1 0x1050 /* width RMuint32 */
#define VO_component_out_TV_vsync_E_0 0x1054 /* width RMuint32 */
#define VO_component_out_TV_vsync_E_1 0x1058 /* width RMuint32 */
#define VO_component_out_TV_HD_hsync_info 0x105c /* width RMuint32 */
#define VO_component_out_TV_HD_vsync 0x1060 /* width RMuint32 */
#define VO_component_out_TV_CGMS 0x1064 /* width RMuint32 */
#define VO_component_out_TV_CC_AGC 0x1068 /* width RMuint32 */
#define VO_component_out_TV_test_config 0x106c /* width RMuint32 */
#define VO_component_out_TV_config2 0x1070 /* width RMuint32 */
#define VO_component_out_TV_cav_minmax 0x1074 /* width RMuint32 */
#define VO_component_out_TV_timing_sync 0x1078 /* width RMuint32 */
#define VO_component_out_TV_MV_N_0_22 0x1080 /* width RMuint32 */
#define VO_component_out_TV_MV_N_1_2_3_4 0x1084 /* width RMuint32 */
#define VO_component_out_TV_MV_N_5_6_7_8 0x1088 /* width RMuint32 */
#define VO_component_out_TV_MV_N_9_10_11 0x108c /* width RMuint32 */
#define VO_component_out_TV_MV_N_12_13_14 0x1090 /* width RMuint32 */
#define VO_component_out_TV_MV_N_15_16_17_18 0x1094 /* width RMuint32 */
#define VO_component_out_TV_MV_N_19_20_21 0x1098 /* width RMuint32 */
/* DispComponentOut registers done */

/* DispCompositeOut registers */
#define VO_composite_out_reset_bit 0x15 /* width RMuint32 */
#define VO_composite_out_bcs 0x1100 /* width RMuint32 */
#define VO_composite_out_Xoffset 0x1104 /* width RMuint32 */
#define VO_composite_out_Yoffset 0x1108 /* width RMuint32 */
#define VO_composite_out_TV_config 0x1140 /* width RMuint32 */
#define VO_composite_out_TV_size 0x1144 /* width RMuint32 */
#define VO_composite_out_TV_hsync 0x1148 /* width RMuint32 */
#define VO_composite_out_TV_vsync_O_0 0x114c /* width RMuint32 */
#define VO_composite_out_TV_vsync_O_1 0x1150 /* width RMuint32 */
#define VO_composite_out_TV_vsync_E_0 0x1154 /* width RMuint32 */
#define VO_composite_out_TV_vsync_E_1 0x1158 /* width RMuint32 */
#define VO_composite_out_TV_CGMS 0x1164 /* width RMuint32 */
#define VO_composite_out_TV_CC_AGC 0x1168 /* width RMuint32 */
#define VO_composite_out_TV_test_config 0x116c /* width RMuint32 */
#define VO_composite_out_TV_MV_N_0_22 0x1180 /* width RMuint32 */
#define VO_composite_out_TV_MV_N_1_2_3_4 0x1184 /* width RMuint32 */
#define VO_composite_out_TV_MV_N_5_6_7_8 0x1188 /* width RMuint32 */
#define VO_composite_out_TV_MV_N_9_10_11 0x118c /* width RMuint32 */
#define VO_composite_out_TV_MV_N_12_13_14 0x1190 /* width RMuint32 */
#define VO_composite_out_TV_MV_N_15_16_17_18 0x1194 /* width RMuint32 */
#define VO_composite_out_TV_MV_N_19_20_21 0x1198 /* width RMuint32 */
/* DispCompositeOut registers done */

/* DemuxEngine registers */
#define REG_BASE_demux_engine 0x000A0000 /* width RMuint32 */
#define MEM_BASE_demux_engine 0x00140000 /* width RMuint32 */
#define PMEM_BASE_demux_engine 0x00140000 /* width RMuint32 */
#define DMEM_BASE_demux_engine 0x00150000 /* width RMuint32 */
#define demux_MISC_dr_mode 0x1e80 /* width RMuint32 */
#define demux_MISC_dr_length 0x1e81 /* width RMuint32 */
#define demux_MISC_dr_address 0x1e82 /* width RMuint32 */
#define demux_MISC_dw_mode 0x1e84 /* width RMuint32 */
#define demux_MISC_dw_length 0x1e85 /* width RMuint32 */
#define demux_MISC_dw_address 0x1e86 /* width RMuint32 */
#define demux_MISC_reset0 0x1e88 /* width RMuint32 */
#define demux_MISC_reset1 0x1e89 /* width RMuint32 */
#define demux_MISC_interrupt 0x1e8A /* width RMuint32 */
#define demux_MISC_timer_div 0x1e8b /* width RMuint32 */
#define demux_MISC_timer_count 0x1e8c /* width RMuint32 */
#define demux_mutex0 0x1e90 /* width RMuint32 */
#define demux_mutex1 0x1e91 /* width RMuint32 */
#define demux_mutex2 0x1e92 /* width RMuint32 */
#define demux_mutex3 0x1e93 /* width RMuint32 */
#define demux_mutex4 0x1e94 /* width RMuint32 */
#define demux_mutex5 0x1e95 /* width RMuint32 */
#define demux_mutex6 0x1e96 /* width RMuint32 */
#define demux_mutex7 0x1e97 /* width RMuint32 */
#define demux_GBUSIF_MAIN_WADD 0x1ea0 /* width RMuint32 */
#define demux_GBUSIF_MAIN_RADD 0x1ea1 /* width RMuint32 */
#define demux_GBUSIF_MAIN_BYTE 0x1ea2 /* width RMuint32 */
#define demux_GBUSIF_MAIN_WORD 0x1ea3 /* width RMuint32 */
#define demux_GBUSIF_MAIN_DWORD 0x1ea4 /* width RMuint32 */
#define demux_GBUSIF_MAIN_STATUS 0x1ea5 /* width RMuint32 */
#define demux_GBUSIF_ISR_WADD 0x1ea8 /* width RMuint32 */
#define demux_GBUSIF_ISR_RADD 0x1ea9 /* width RMuint32 */
#define demux_GBUSIF_ISR_BYTE 0x1eaa /* width RMuint32 */
#define demux_GBUSIF_ISR_WORD 0x1eab /* width RMuint32 */
#define demux_GBUSIF_ISR_DWORD 0x1eac /* width RMuint32 */
#define demux_GBUSIF_ISR_STATUS 0x1ead /* width RMuint32 */
#define demux_MBUSIF_w0_add 0x1ec0 /* width RMuint32 */
#define demux_MBUSIF_w0_cnt 0x1ec1 /* width RMuint32 */
#define demux_MBUSIF_w0_skip 0x1ec2 /* width RMuint32 */
#define demux_MBUSIF_w0_cmd 0x1ec3 /* width RMuint32 */
#define demux_MBUSIF_r0_add 0x1ed0 /* width RMuint32 */
#define demux_MBUSIF_r0_cnt 0x1ed1 /* width RMuint32 */
#define demux_MBUSIF_r0_skip 0x1ed2 /* width RMuint32 */
#define demux_MBUSIF_r0_cmd 0x1ed3 /* width RMuint32 */
#define demux_cipher_c2_secret_key 0x1c00 /* width RMuint32 */
#define demux_cipher_c2_key_lsb 0x1c70 /* width RMuint32 */
#define demux_cipher_c2_key_msb 0x1c71 /* width RMuint32 */
#define demux_cipher_c2g_ecb_data_lsb 0x1c72 /* width RMuint32 */
#define demux_cipher_c2g_ecb_data_msb 0x1c73 /* width RMuint32 */
#define demux_cipher_c2_flags 0x1c74 /* width RMuint32 */
#define demux_cipher_multi2_syst_key 0x1c80 /* width RMuint32 */
#define demux_cipher_multi2_data_key 0x1c88 /* width RMuint32 */
#define demux_cipher_multi2_iv       0x1c8a /* width RMuint32 */
#define demux_cipher_multi2_flags 0x1c8c /* width RMuint32 */
#define demux_cipher_config 0x1c8f /* width RMuint32 */
#define demux_cipher_rc4_key_0 0x1e40 /* width RMuint32 */
#define demux_cipher_rc4_key_1 0x1e41 /* width RMuint32 */
#define demux_cipher_rc4_key_2 0x1e42 /* width RMuint32 */
#define demux_cipher_rc4_key_3 0x1e43 /* width RMuint32 */
#define demux_cipher_rc4_key_4 0x1e44 /* width RMuint32 */
#define demux_cipher_rc4_key_5 0x1e45 /* width RMuint32 */
#define demux_cipher_rc4_key_6 0x1e46 /* width RMuint32 */
#define demux_cipher_rc4_key_7 0x1e47 /* width RMuint32 */
#define demux_cipher_rc4_flags 0x1e48 /* width RMuint32 */
#define demux_cipher_des_key1_1 0x1e50 /* width RMuint32 */
#define demux_cipher_des_key1_2 0x1e51 /* width RMuint32 */
#define demux_cipher_des_key2_1 0x1e52 /* width RMuint32 */
#define demux_cipher_des_key2_2 0x1e53 /* width RMuint32 */
#define demux_cipher_des_key3_1 0x1e54 /* width RMuint32 */
#define demux_cipher_des_key3_2 0x1e55 /* width RMuint32 */
#define demux_cipher_des_IV_1 0x1e56 /* width RMuint32 */
#define demux_cipher_des_IV_2 0x1e57 /* width RMuint32 */
#define demux_cipher_des_flags 0x1e58 /* width RMuint32 */
#define demux_cipher_dvbcsa_csr_ls 0x1e5c /* width RMuint32 */
#define demux_cipher_dvbcsa_csr_ms 0x1e5d /* width RMuint32 */
#define demux_cipher_dvbcsa_flags 0x1e5e /* width RMuint32 */
#define demux_cipher_aes_key_1 0x1e60 /* width RMuint32 */
#define demux_cipher_aes_key_2 0x1e61 /* width RMuint32 */
#define demux_cipher_aes_key_3 0x1e62 /* width RMuint32 */
#define demux_cipher_aes_key_4 0x1e63 /* width RMuint32 */
#define demux_cipher_aes_key_5 0x1e64 /* width RMuint32 */
#define demux_cipher_aes_key_6 0x1e65 /* width RMuint32 */
#define demux_cipher_aes_key_7 0x1e66 /* width RMuint32 */
#define demux_cipher_aes_key_8 0x1e67 /* width RMuint32 */
#define demux_cipher_aes_flags 0x1e68 /* width RMuint32 */
#define demux_cipher_aes_IV_1 0x1e69 /* width RMuint32 */
#define demux_cipher_aes_IV_2 0x1e6a /* width RMuint32 */
#define demux_cipher_aes_IV_3 0x1e6b /* width RMuint32 */
#define demux_cipher_aes_IV_4 0x1e6c /* width RMuint32 */
#define demux_cipher_aes_IV_5 0x1e6d /* width RMuint32 */
#define demux_cipher_aes_IV_6 0x1e6e /* width RMuint32 */
#define demux_cipher_aes_IV_7 0x1e6f /* width RMuint32 */
#define demux_cipher_aes_IV_8 0x1e70 /* width RMuint32 */
#define demux_cipher_dvd_cnt 0x1e78 /* width RMuint32 */
#define demux_cipher_dvd_tklo 0x1e7a /* width RMuint32 */
#define demux_cipher_dvd_tkhi 0x1e7b /* width RMuint32 */
#define demux_cipher_dvd_state0 0x1e7c /* width RMuint32 */
#define demux_cipher_dvd_state1 0x1e7d /* width RMuint32 */
#define demux_cw_ram_multi2_syst_key 0x1a00 /* width RMuint32 */
#define demux_cw_ram_multi2_data_key 0x1a80 /* width RMuint32 */
#define demux_cw_ram_multi2_iv 0x1aa0 /* width RMuint32 */
#define demux_cw_ram_rc4_key 0x1ac0 /* width RMuint32 */
#define demux_cw_ram_aes_key 0x1b00 /* width RMuint32 */
#define demux_cw_ram_aes_iv 0x1b08 /* width RMuint32 */
#define demux_cw_ram_dvbcsa_key 0x1b60 /* width RMuint32 */
#define demux_cw_ram_des_key1 0x1b80 /* width RMuint32 */
#define demux_cw_ram_des_key2 0x1ba0 /* width RMuint32 */
#define demux_cw_ram_des_key3 0x1bc0 /* width RMuint32 */
#define demux_cw_ram_des_iv 0x1be0 /* width RMuint32 */
#define demux_section_filter_start 0x1800 /* width RMuint32 */
#define TDMX_gpio_data 0x2e0c /* width RMuint32 */
#define TDMX_gpio_dir 0x2e0d /* width RMuint32 */
#define demux_spi_write_ptr0 0x1e08 /* width RMuint32 */
#define demux_spi_write_ptr1 0x1e09 /* width RMuint32 */
#define demux_spi_write_ptr2 0x1e0a /* width RMuint32 */
#define demux_spi_write_ptr3 0x1e0b /* width RMuint32 */
#define demux_spi_routing 0x1e0c /* width RMuint32 */
#define demux_spi_clk_phase 0x1e0d /* width RMuint32 */
#define demux_spi_sync_bytes 0x1e0e /* width RMuint32 */
#define demux_idma_write_ptr 0x1e18 /* width RMuint32 */
#define demux_idma_cnt 0x1e19 /* width RMuint32 */
#define demux_odma_read_ptr 0x1e20 /* width RMuint32 */
#define demux_odma_cnt 0x1e21 /* width RMuint32 */
#define demux_odma_sc_stat 0x1e22 /* width RMuint32 */
#define demux_odma_sc_match 0x1e23 /* width RMuint32 */
#define demux_sbox_mode 0x1e28 /* width RMuint32 */
#define demux_MISC_UNRESET_MASK 0xd800 /* width RMuint32 */
#define demux_MISC_RESET_MASK 0xd8d8 /* width RMuint32 */
#define demux_SP_init 0x7fe /* width RMuint32 */
/* DemuxEngine registers done */

/* Demux registers */
/* Demux registers done */

/* DemuxProgram registers */
/* DemuxProgram registers done */

/* MpegEngine registers */
#define REG_BASE_mpeg_engine_0 0x00080000 /* width RMuint32 */
#define MEM_BASE_mpeg_engine_0 0x00100000 /* width RMuint32 */
#define PMEM_BASE_mpeg_engine_0 0x00100000 /* width RMuint32 */
#define DMEM_BASE_mpeg_engine_0 0x00110000 /* width RMuint32 */
#define REG_BASE_mpeg_engine_1 0x00090000 /* width RMuint32 */
#define MEM_BASE_mpeg_engine_1 0x00120000 /* width RMuint32 */
#define PMEM_BASE_mpeg_engine_1 0x00120000 /* width RMuint32 */
#define DMEM_BASE_mpeg_engine_1 0x00130000 /* width RMuint32 */
#define mpeg_mutex0 0x0fe0 /* width RMuint32 */
#define mpeg_mutex1 0x0fe1 /* width RMuint32 */
#define mpeg_mutex2 0x0fe2 /* width RMuint32 */
#define mpeg_mutex3 0x0fe3 /* width RMuint32 */
#define mpeg_mutex4 0x0fe4 /* width RMuint32 */
#define mpeg_mutex5 0x0fe5 /* width RMuint32 */
#define mpeg_mutex6 0x0fe6 /* width RMuint32 */
#define mpeg_mutex7 0x0fe7 /* width RMuint32 */
#define RBUS_offset 0x4000 /* width RMuint32 */
#define mpeg_MBUSIF_w0_addlo 0xE80 /* width RMuint32 */
#define mpeg_MBUSIF_w0_addhi 0xE81 /* width RMuint32 */
#define mpeg_MBUSIF_w0_xcnt 0xE82 /* width RMuint32 */
#define mpeg_MBUSIF_w0_ycnt 0xE83 /* width RMuint32 */
#define mpeg_MBUSIF_w0_skiplo 0xE84 /* width RMuint32 */
#define mpeg_MBUSIF_w0_skiphi 0xE85 /* width RMuint32 */
#define mpeg_MBUSIF_w0_cmd 0xE86 /* width RMuint32 */
#define mpeg_MBUSIF_w0_vbuf_width 0xE87 /* width RMuint32 */
#define mpeg_MBUSIF_r0_addlo 0xE90 /* width RMuint32 */
#define mpeg_MBUSIF_r0_addhi 0xE91 /* width RMuint32 */
#define mpeg_MBUSIF_r0_xcnt 0xE92 /* width RMuint32 */
#define mpeg_MBUSIF_r0_ycnt 0xE93 /* width RMuint32 */
#define mpeg_MBUSIF_r0_skiplo 0xE94 /* width RMuint32 */
#define mpeg_MBUSIF_r0_skiphi 0xE95 /* width RMuint32 */
#define mpeg_MBUSIF_r0_cmd 0xE96 /* width RMuint32 */
#define mpeg_MBUSIF_r0_vbuf_width 0xE97 /* width RMuint32 */
#define mpeg_MBUSIF_r1_addlo 0xEA0 /* width RMuint32 */
#define mpeg_MBUSIF_r1_addhi 0xEA1 /* width RMuint32 */
#define mpeg_MBUSIF_r1_xcnt 0xEA2 /* width RMuint32 */
#define mpeg_MBUSIF_r1_ycnt 0xEA3 /* width RMuint32 */
#define mpeg_MBUSIF_r1_skiplo 0xEA4 /* width RMuint32 */
#define mpeg_MBUSIF_r1_skiphi 0xEA5 /* width RMuint32 */
#define mpeg_MBUSIF_r1_cmd 0xEA6 /* width RMuint32 */
#define mpeg_MBUSIF_r1_vbuf_width 0xEA7 /* width RMuint32 */
#define mpeg_MBUSIF_w1_addlo 0xEB0 /* width RMuint32 */
#define mpeg_MBUSIF_w1_addhi 0xEB1 /* width RMuint32 */
#define mpeg_MBUSIF_w1_xcnt 0xEB2 /* width RMuint32 */
#define mpeg_MBUSIF_w1_ycnt 0xEB3 /* width RMuint32 */
#define mpeg_MBUSIF_w1_skiplo 0xEB4 /* width RMuint32 */
#define mpeg_MBUSIF_w1_skiphi 0xEB5 /* width RMuint32 */
#define mpeg_MBUSIF_w1_cmd 0xEB6 /* width RMuint32 */
#define mpeg_MBUSIF_w1_vbuf_width 0xEB7 /* width RMuint32 */
#define mpeg_MBUSIF_r2_addlo 0xEC0 /* width RMuint32 */
#define mpeg_MBUSIF_r2_addhi 0xEC1 /* width RMuint32 */
#define mpeg_MBUSIF_r2_xcnt 0xEC2 /* width RMuint32 */
#define mpeg_MBUSIF_r2_ycnt 0xEC3 /* width RMuint32 */
#define mpeg_MBUSIF_r2_skiplo 0xEC4 /* width RMuint32 */
#define mpeg_MBUSIF_r2_skiphi 0xEC5 /* width RMuint32 */
#define mpeg_MBUSIF_r2_cmd 0xEC6 /* width RMuint32 */
#define mpeg_MBUSIF_r2_vbuf_width 0xEC7 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_WADD_LOW 0xFA0 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_WADD_HIGH 0xFA1 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_RADD_LOW 0xFA2 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_RADD_HIGH 0xFA3 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_BYTE 0xFA4 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_WORD 0xFA5 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_DWORD_LOW 0xFA6 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_DWORD_HIGH 0xFA7 /* width RMuint32 */