emhwlib_registers_tango15.h

1. 8623L平台

#define VO_osd_format_hds 0x0300 /* width RMuint32 */
#define VO_osd_output_size 0x0304 /* width RMuint32 */
#define VO_osd_scale_factor 0x0308 /* width RMuint32 */
#define VO_osd_scale_phase_flicker 0x030c /* width RMuint32 */
#define VO_osd_alpha_routing 0x0310 /* width RMuint32 */
#define VO_osd_key_color 0x0314 /* width RMuint32 */
#define VO_osd_lut 0x9000 /* width RMuint32 */
#define VO_osd_lut0 0x9000 /* width RMuint32 */
/* DispOSDScaler registers done */

/* DispHardwareCursor registers */
#define VO_cursor_reset_bit 0x01 /* width RMuint32 */
#define VO_cursor_size_ctrl 0x0100 /* width RMuint32 */
#define VO_cursor_lut 0x0140 /* width RMuint32 */
#define VO_cursor_lut0 0x0140 /* width RMuint32 */
#define VO_cursor_lut1 0x0144 /* width RMuint32 */
#define VO_cursor_lut2 0x0148 /* width RMuint32 */
#define VO_cursor_lut3 0x014c /* width RMuint32 */
#define VO_cursor_lut4 0x0150 /* width RMuint32 */
#define VO_cursor_lut5 0x0154 /* width RMuint32 */
#define VO_cursor_lut6 0x0158 /* width RMuint32 */
#define VO_cursor_lut7 0x015c /* width RMuint32 */
#define VO_cursor_lut8 0x0160 /* width RMuint32 */
#define VO_cursor_lut9 0x0164 /* width RMuint32 */
#define VO_cursor_lut10 0x0168 /* width RMuint32 */
#define VO_cursor_lut11 0x016c /* width RMuint32 */
#define VO_cursor_lut12 0x0170 /* width RMuint32 */
#define VO_cursor_lut13 0x0174 /* width RMuint32 */
#define VO_cursor_lut14 0x0178 /* width RMuint32 */
#define VO_cursor_lut15 0x017c /* width RMuint32 */
#define VO_cursor_pix 0x8000 /* width RMuint32 */
#define VO_cursor_pix0 0x8000 /* width RMuint32 */
/* DispHardwareCursor registers done */

/* DispMainVideoScaler registers */
#define VO_main_reset_bit 0x04 /* width RMuint32 */
#define VO_main_format_hds 0x0400 /* width RMuint32 */
#define VO_main_output_size 0x0404 /* width RMuint32 */
#define VO_main_scale_factor 0x0408 /* width RMuint32 */
#define VO_main_scale_phase 0x040c /* width RMuint32 */
#define VO_main_phase 0x040c /* width RMuint32 */
#define VO_main_alpha_deint_routing 0x0410 /* width RMuint32 */
#define VO_main_deint2 0x0414 /* width RMuint32 */
#define VO_main_bcs 0x0418 /* width RMuint32 */
#define VO_main_pulldown 0x041c /* width RMuint32 */
#define VO_main_strip_filter 0x0420 /* width RMuint32 */
#define VO_main_nonlinear_0 0x0424 /* width RMuint32 */
#define VO_main_nonlinear_1 0x0428 /* width RMuint32 */
/* DispMainVideoScaler registers done */

/* DispSubPictureScaler registers */
#define VO_subp_reset_bit 0x02 /* width RMuint32 */
#define VO_subp_format_hds 0x0200 /* width RMuint32 */
#define VO_subp_output_size 0x0204 /* width RMuint32 */
#define VO_subp_scale_factor 0x0208 /* width RMuint32 */
#define VO_subp_scale_phase_routing 0x020c /* width RMuint32 */
#define VO_sp_lut 0x0240 /* width RMuint32 */
#define VO_sp_lut0 0x0240 /* width RMuint32 */
/* DispSubPictureScaler registers done */

/* DispVCRMultiScaler registers */
#define VO_VCR_reset_bit 0x05 /* width RMuint32 */
#define VO_VCR_format_hds 0x0500 /* width RMuint32 */
#define VO_VCR_output_size 0x0504 /* width RMuint32 */
#define VO_VCR_scale_factor 0x0508 /* width RMuint32 */
#define VO_VCR_scale_phase 0x050c /* width RMuint32 */
#define VO_VCR_phase 0x050c /* width RMuint32 */
#define VO_VCR_alpha_routing 0x0510 /* width RMuint32 */
#define VO_VCR_key_color 0x0514 /* width RMuint32 */
#define VO_VCR_bcs 0x0518 /* width RMuint32 */
#define VO_VCR_strip_edge 0x051C /* width RMuint32 */
#define VO_VCR_nonlinear_0 0x0520 /* width RMuint32 */
#define VO_VCR_nonlinear_1 0x0524 /* width RMuint32 */
#define VO_VCR_tiling 0x0528 /* width RMuint32 */
#define VO_VCR_lut 0xa000 /* width RMuint32 */
#define VO_VCR_lut0 0xa000 /* width RMuint32 */
/* DispVCRMultiScaler registers done */

/* DispCRTMultiScaler registers */
#define VO_CRT_reset_bit 0x06 /* width RMuint32 */
#define VO_CRT_format_hds 0x0600 /* width RMuint32 */
#define VO_CRT_output_size 0x0604 /* width RMuint32 */
#define VO_CRT_scale_factor 0x0608 /* width RMuint32 */
#define VO_CRT_scale_phase 0x060c /* width RMuint32 */
#define VO_CRT_phase 0x060c /* width RMuint32 */
#define VO_CRT_alpha_routing 0x0610 /* width RMuint32 */
#define VO_CRT_key_color 0x0614 /* width RMuint32 */
#define VO_CRT_bcs 0x0618 /* width RMuint32 */
#define VO_CRT_strip_edge 0x061C /* width RMuint32 */
#define VO_CRT_nonlinear_0 0x0620 /* width RMuint32 */
#define VO_CRT_nonlinear_1 0x0624 /* width RMuint32 */
#define VO_CRT_tiling 0x0628 /* width RMuint32 */
#define VO_CRT_lut 0xb000 /* width RMuint32 */
#define VO_CRT_lut0 0xb000 /* width RMuint32 */
/* DispCRTMultiScaler registers done */

/* DispGFXMultiScaler registers */
#define VO_GFX_reset_bit 0x07 /* width RMuint32 */
#define VO_GFX_format_hds 0x0700 /* width RMuint32 */
#define VO_GFX_output_size 0x0704 /* width RMuint32 */
#define VO_GFX_scale_factor 0x0708 /* width RMuint32 */
#define VO_GFX_scale_phase 0x070c /* width RMuint32 */
#define VO_GFX_phase 0x070c /* width RMuint32 */
#define VO_GFX_alpha_routing 0x0710 /* width RMuint32 */
#define VO_GFX_key_color 0x0714 /* width RMuint32 */
#define VO_GFX_bcs 0x0718 /* width RMuint32 */
#define VO_GFX_strip_edge 0x071C /* width RMuint32 */
#define VO_GFX_nonlinear_0 0x0720 /* width RMuint32 */
#define VO_GFX_nonlinear_1 0x0724 /* width RMuint32 */
#define VO_GFX_tiling 0x0728 /* width RMuint32 */
#define VO_GFX_lut 0xc000 /* width RMuint32 */
#define VO_GFX_lut0 0xc000 /* width RMuint32 */
/* DispGFXMultiScaler registers done */

/* DispMainMixer registers */
#define VO_mix_reset_bit 0x08 /* width RMuint32 */
#define VO_mix_gfx_pos 0x0800 /* width RMuint32 */
#define VO_mix_crt_pos 0x0804 /* width RMuint32 */
#define VO_mix_vcr_pos 0x0808 /* width RMuint32 */
#define VO_mix_sp_pos 0x080C /* width RMuint32 */
#define VO_mix_mv_pos 0x0810 /* width RMuint32 */
#define VO_mix_osd_pos 0x0814 /* width RMuint32 */
#define VO_mix_gin_pos 0x0818 /* width RMuint32 */
#define VO_mix_cur_pos 0x081C /* width RMuint32 */
#define VO_mix_index 0x0820 /* width RMuint32 */
#define VO_mix_frame_size 0x0824 /* width RMuint32 */
#define VO_mix_background 0x0828 /* width RMuint32 */
/* DispMainMixer registers done */

/* DispVCRMixer registers */
#define VO_vcrmix_reset_bit 0x09 /* width RMuint32 */
#define VO_vcrmix_gfx_pos 0x0900 /* width RMuint32 */
#define VO_vcrmix_crt_pos 0x0904 /* width RMuint32 */
#define VO_vcrmix_sp_pos 0x0908 /* width RMuint32 */
#define VO_vcrmix_vcr_pos 0x090C /* width RMuint32 */
#define VO_vcrmix_index 0x0910 /* width RMuint32 */
#define VO_vcrmix_frame_size 0x0914 /* width RMuint32 */
#define VO_vcrmix_background 0x0918 /* width RMuint32 */
/* DispVCRMixer registers done */

/* DispColorBars registers */
#define VO_color_bars_reset_bit 0x0b /* width RMuint32 */
#define VO_color_bars_ctrl 0x0d00 /* width RMuint32 */
#define VO_color_bars_size 0x0d04 /* width RMuint32 */
/* DispColorBars registers done */

/* DispRouting registers */
#define VO_routing_reset_bit 0x16 /* width RMuint32 */
#define VO_routing_ctrl 0x1208 /* width RMuint32 */
/* DispRouting registers done */

/* DispVideoInput registers */
#define VO_vid_in_reset_bit 0x10 /* width RMuint32 */
#define VO_vid_in_format 0x0b00 /* width RMuint32 */
#define VO_vid_in_data_size 0x0b04 /* width RMuint32 */
#define VO_vid_in_data_Xoffset 0x0b08 /* width RMuint32 */
#define VO_vid_in_data_Yoffset 0x0b0c /* width RMuint32 */
#define VO_vid_in_hz_sync 0x0b10 /* width RMuint32 */
#define VO_vid_in_vt_sync 0x0b14 /* width RMuint32 */
#define VO_vid_in_sync_coord 0x0b18 /* width RMuint32 */
#define VO_vid_in_top_vbi 0x0b1c /* width RMuint32 */
#define VO_vid_in_bot_vbi 0x0b20 /* width RMuint32 */
#define VO_vid_in_counters 0x0b24 /* width RMuint32 */
#define VO_vid_in_vbi_size 0x0b28 /* width RMuint32 */
#define VO_vid_in_vbi_vsm 0x0b2c /* width RMuint32 */
#define VO_vid_in_vbi_Voffset 0x0b30 /* width RMuint32 */
#define VO_vid_in_format2 0x0b34 /* width RMuint32 */
#define VO_vid_in_counters2 0x0b38 /* width RMuint32 */
/* DispVideoInput registers done */

/* DispGraphicInput registers */
#define VO_graph_in_reset_bit 0x11 /* width RMuint32 */
#define VO_graph_in_format 0x0c00 /* width RMuint32 */
#define VO_graph_in_alpha_routing 0x0c04 /* width RMuint32 */
#define VO_graph_in_key_color 0x0c08 /* width RMuint32 */
#define VO_graph_in_data_size 0x0c0c /* width RMuint32 */
#define VO_graph_in_data_Xoffset 0x0c10 /* width RMuint32 */
#define VO_graph_in_data_Yoffset 0x0c14 /* width RMuint32 */
#define VO_graph_in_hz_sync 0x0c18 /* width RMuint32 */
#define VO_graph_in_vt_sync 0x0c1c /* width RMuint32 */
#define VO_graph_in_sync_coord 0x0c20 /* width RMuint32 */
#define VO_graph_in_sync_offset 0x0c24 /* width RMuint32 */
#define VO_graph_in_top_vbi 0x0c28 /* width RMuint32 */
#define VO_graph_in_bot_vbi 0x0c2c /* width RMuint32 */
#define VO_graph_in_counters 0x0c30 /* width RMuint32 */
#define VO_graph_in_format2 0x0c34 /* width RMuint32 */
#define VO_graph_in_counters2 0x0c38 /* width RMuint32 */
#define VO_graph_in_vbi_size 0x0c3c /* width RMuint32 */
#define VO_graph_in_vbi_vsm 0x0c40 /* width RMuint32 */
#define VO_graph_in_vbi_Voffset 0x0c44 /* width RMuint32 */
/* DispGraphicInput registers done */

/* DispDigitalOut registers */
#define VO_digit_out_reset_bit 0x12 /* width RMuint32 */
#define VO_digit_out_conv0 0x0e00 /* width RMuint32 */
#define VO_digit_out_conv1 0x0e04 /* width RMuint32 */
#define VO_digit_out_conv2 0x0e08 /* width RMuint32 */
#define VO_digit_out_conv3 0x0e0c /* width RMuint32 */
#define VO_digit_out_conv4 0x0e10 /* width RMuint32 */
#define VO_digit_out_conv5 0x0e14 /* width RMuint32 */
#define VO_digit_out_format 0x0e20 /* width RMuint32 */
#define VO_digit_out_Xoffset 0x0e24 /* width RMuint32 */
#define VO_digit_out_Yoffset 0x0e28 /* width RMuint32 */
#define VO_digit_out_hz_sync 0x0e2c /* width RMuint32 */
#define VO_digit_out_vt_sync 0x0e30 /* width RMuint32 */
#define VO_digit_out_vsync_coord 0x0e34 /* width RMuint32 */
#define VO_digit_out_pads_config 0x0020 /* width RMuint32 */
#define VO_digit_out_gamma_lut0 0xf000 /* width RMuint32 */
#define VO_digit_out_temp_lut0 0xf400 /* width RMuint32 */
/* DispDigitalOut registers done */

/* DispMainAnalogOut registers */
#define VO_main_analog_reset_bit 0x13 /* width RMuint32 */
#define VO_main_analog_conv0 0x0f00 /* width RMuint32 */
#define VO_main_analog_conv1 0x0f04 /* width RMuint32 */
#define VO_main_analog_conv2 0x0f08 /* width RMuint32 */
#define VO_main_analog_conv3 0x0f0c /* width RMuint32 */
#define VO_main_analog_conv4 0x0f10 /* width RMuint32 */
#define VO_main_analog_conv5 0x0f14 /* width RMuint32 */
#define VO_main_analog_xoffset_field 0x0f18 /* width RMuint32 */
#define VO_main_analog_yoffset 0x0f1c /* width RMuint32 */
#define VO_main_analog_cvbs_conv0 0x0f20 /* width RMuint32 */
#define VO_main_analog_cvbs_conv1 0x0f24 /* width RMuint32 */
#define VO_main_analog_cvbs_conv2 0x0f28 /* width RMuint32 */
#define VO_main_analog_cvbs_conv3 0x0f2c /* width RMuint32 */
#define VO_main_analog_cvbs_conv4 0x0f30 /* width RMuint32 */
#define VO_main_analog_cvbs_conv5 0x0f34 /* width RMuint32 */
#define VO_main_analog_TV_config 0x0f40 /* width RMuint32 */
#define VO_main_analog_TV_size 0x0f44 /* width RMuint32 */
#define VO_main_analog_TV_hsync 0x0f48 /* width RMuint32 */
#define VO_main_analog_TV_vsync_O_0 0x0f4c /* width RMuint32 */
#define VO_main_analog_TV_vsync_O_1 0x0f50 /* width RMuint32 */
#define VO_main_analog_TV_vsync_E_0 0x0f54 /* width RMuint32 */
#define VO_main_analog_TV_vsync_E_1 0x0f58 /* width RMuint32 */
#define VO_main_analog_TV_HD_hsync_info 0x0f5c /* width RMuint32 */
#define VO_main_analog_TV_HD_vsync 0x0f60 /* width RMuint32 */
#define VO_main_analog_TV_CGMS 0x0f64 /* width RMuint32 */
#define VO_main_analog_TV_CC_AGC 0x0f68 /* width RMuint32 */
#define VO_main_analog_TV_test_config 0x0f6c /* width RMuint32 */
#define VO_main_analog_TV_teletext_config 0x0f70 /* width RMuint32 */
#define VO_main_analog_TV_config2 0x0f74 /* width RMuint32 */
#define VO_main_analog_TV_cav_minmax 0x0f78 /* width RMuint32 */
#define VO_main_analog_TV_timing_sync 0x0f7c /* width RMuint32 */
#define VO_main_analog_TV_MV_N_0_22 0x0f80 /* width RMuint32 */
#define VO_main_analog_TV_MV_N_1_2_3_4 0x0f84 /* width RMuint32 */
#define VO_main_analog_TV_MV_N_5_6_7_8 0x0f88 /* width RMuint32 */
#define VO_main_analog_TV_MV_N_9_10_11 0x0f8c /* width RMuint32 */
#define VO_main_analog_TV_MV_N_12_13_14 0x0f90 /* width RMuint32 */
#define VO_main_analog_TV_MV_N_15_16_17_18 0x0f94 /* width RMuint32 */
#define VO_main_analog_TV_MV_N_19_20_21 0x0f98 /* width RMuint32 */
#define VO_main_analog_tlxt0 0xe000 /* width RMuint32 */
/* DispMainAnalogOut registers done */

/* DispComponentOut registers */
#define VO_component_out_reset_bit 0x14 /* width RMuint32 */
#define VO_component_out_conv0 0x1000 /* width RMuint32 */
#define VO_component_out_conv1 0x1004 /* width RMuint32 */