test-stage0.c

1. 8623L平台

	uart_printf("\t[F] Set System frequency (SYS: %dMHz)\n", idivide(tango_get_sysclock(), 1000000));
	uart_puts("\t[X] Exit special mode\n");
	uart_puts("\tChoice: ");

	c = uart_getc();
	uart_putc('\n');
	switch(c) {
	    case '0': {
			 unsigned long dram_reg_base = REG_BASE_dram_controller_0;
			 unsigned long old_dunit_cfg = gbus_read_uint32(0, dram_reg_base + DRAM_dunit_cfg);
			 unsigned long old_delay = gbus_read_uint32(0, dram_reg_base + DRAM_dunit_delay0_ctrl);
			 unsigned long dunit_cfg, delay;

			 dunit_cfg = uart_getULong("  DRAM dunit_cfg (0=unchanged): ");
			 delay = uart_getULong("  DRAM delay_ctrl (0=unchanged): ");
			 if (dunit_cfg == 0)
				 dunit_cfg = old_dunit_cfg;
			 if (delay == 0)
				 delay = old_delay;
				 
			 if ((delay != old_delay) || (dunit_cfg != old_dunit_cfg)) {
				 gbus_write_uint32(0, dram_reg_base + G2L_RESET_CONTROL, 3);
				 gbus_write_uint32(0, dram_reg_base + G2L_RESET_CONTROL, 2);
				 gbus_write_uint32(0, dram_reg_base + DRAM_dunit_cfg, dunit_cfg);
				 gbus_write_uint32(0, dram_reg_base + DRAM_dunit_delay0_ctrl, delay);
				 gbus_write_uint32(0, dram_reg_base + G2L_RESET_CONTROL, 0);
				 dunit_changed = 1;
			 } 
	            }
		    break;
#if (DEFAULT_DRAM1_SIZE != 0)
	    case '1': {
			 unsigned long dram_reg_base = REG_BASE_dram_controller_1;
			 unsigned long old_dunit_cfg = gbus_read_uint32(0, dram_reg_base + DRAM_dunit_cfg);
			 unsigned long old_delay = gbus_read_uint32(0, dram_reg_base + DRAM_dunit_delay0_ctrl);
			 unsigned long dunit_cfg, delay;

			 dunit_cfg = uart_getULong("  DRAM dunit_cfg (0=unchanged): ");
			 delay = uart_getULong("  DRAM delay_ctrl (0=unchanged): ");
			 if (dunit_cfg == 0)
				 dunit_cfg = old_dunit_cfg;
			 if (delay == 0)
				 delay = old_delay;
				 
			 if ((delay != old_delay) || (dunit_cfg != old_dunit_cfg)) {
				 gbus_write_uint32(0, dram_reg_base + G2L_RESET_CONTROL, 3);
				 gbus_write_uint32(0, dram_reg_base + G2L_RESET_CONTROL, 2);
				 gbus_write_uint32(0, dram_reg_base + DRAM_dunit_cfg, dunit_cfg);
				 gbus_write_uint32(0, dram_reg_base + DRAM_dunit_delay0_ctrl, delay);
				 gbus_write_uint32(0, dram_reg_base + G2L_RESET_CONTROL, 0);
				 dunit_changed = 1;
			 } 
	            }
		    break;
#endif
	    case 'K':
	    case 'k': {
			 unsigned long tmp = uart_getULong("  #Block: ");
			 if ((tmp <= 0) || (tmp >= 8192)) {
				 uart_puts("  Invalid input value [1-8191].\n");
		         } else
				 nblocks = tmp;
	            }
		    break;
	    case 'Z':
	    case 'z': {
			 unsigned long tmp = uart_getULong("  Block size: ");
			 if ((tmp <= 0) || (tmp >= 8192) || ((tmp & 0x3) != 0)) {
				 uart_puts("  Invalid input value [4-8188], multiple of 4.\n");
		         } else
				 blk_size = tmp;
	            }
		    break;
	    case 'S':
	    case 's': {
			 unsigned long val = uart_getULong("  DRAM Test Start freq.: ");
			 if (val == 0) 
				 uart_puts("  Invalid input value.\n");
			 else if (val > end)
				 uart_printf("  Invalid value %ld (start > end)\n", val);
			 else 
				 start = val;
	            }
		    break;
	    case 'E':
	    case 'e': {
			 unsigned long val = uart_getULong("  DRAM Test End freq.: ");
			 if (val == 0) 
				 uart_puts("  Invalid input value.\n");
			 else if (val < start)
				 uart_printf("  Invalid value %ld (end < start)\n", val);
			 else 
				 end = val;
	            }
		    break;
	    case 'L':
	    case 'l': { 
			 unsigned long val = uart_getULong("  DRAM Test Write delay: ");
			 if (val >= 0x10)
				 uart_printf("  Invalid input value %ld (0x%lx).\n", val, val);
			 else 
				 w_delay = val;
	            }
		    break;
	    case 'G':
	    case 'g': { 
			 unsigned long val = uart_getULong("  Min. good size: ");
			 if ((val < 1) || (val >= 0x10))
				 uart_printf("  Invalid input value %ld (1-15).\n", val);
			 else 
				 gsize = val;
	            }
		    break;
	    case 'M':
	    case 'm': { 
			 unsigned long val = uart_getULong("  Test Pattern mask: ");
			 tmask = val;
	            }
		    break;
	    case 'D':
            case 'd':
		    uart_puts("\n\n");
		    em8600_mem_test_all_freqs(start, end, w_delay, nblocks, blk_size, tmask);
		    uart_puts("\n\n");
		    break;
	    case 'B':
            case 'b': {
			 int i;
		         uart_puts("\n\n");
		         for (i = 0; bist_table[i].addr != 0; i++) 
			    do_bist(&bist_table[i]);
		         uart_puts("\n\n");
		    }
		    break;
	    case 'C':
            case 'c': {
			 unsigned int res = 0;
		         uart_puts("\n\n");
			 if ((res = em86xx_cache_bist()) == 0)
				 uart_puts("I/D-CACHE BIST OK\n");
			 else {
				 if (res & 1)
					 uart_puts("\07I-CACHE BIST failed\n");
				 if (res & 2)
					 uart_puts("\07D-CACHE BIST failed\n");
			 }
			 if (dcache_test())
				 uart_puts("\07D-CACHE test failed\n");
			 else
				 uart_puts("D-CACHE test OK\n");
			 uart_puts("\n\n");
		    }
		    break;
	    case 'P':
            case 'p':
		    uart_puts("\n\n");
		    em8600_mem_test_find_params(dunit_changed, nblocks, blk_size, gsize, tmask);
		    dunit_changed = mem_test_needed = 0;
		    uart_puts("\n\n");
		    break;
	    case 'A':
            case 'a':
		    uart_puts("\n\n");
		    em8600_mem_test_all_bits(w_delay, def_freq, nblocks, blk_size, tmask);
		    uart_puts("\n\n");
		    break;
	    case 'T':
            case 't':
		    uart_puts("\n\n");
		    em8600_special_mem_test(nblocks, blk_size, tmask);
		    uart_puts("\n\n");
		    break;
            case '3': {
			  unsigned long gbus_addr;
			  gbus_addr = uart_getULong("  GBUS address (aligned by 4): ");
			  if (gbus_addr != 0) 
				  uart_printf("  *(0x%08lx) => 0x%08lx\n", gbus_addr, gbus_read_uint32(0, gbus_addr));
			  else 
				  uart_printf("  Invalid gbus address.\n");
	            }
		    break;
            case '4': {
			  unsigned long gbus_addr, val;
			  gbus_addr = uart_getULong("  GBUS address (aligned by 4): ");
			  if (gbus_addr != 0) {
				  val = uart_getULong("  Data: ");
				  gbus_write_uint32(0, gbus_addr, val);
				  uart_printf("  *(0x%08lx) <= 0x%08lx\n", gbus_addr, val);
			  } else 
				  uart_printf("  Invalid gbus address.\n");
	            }
		    break;
            case '6': {
			  unsigned long gbus_addr;
			  gbus_addr = uart_getULong("  GBUS address (aligned by 2): ");
			  if (gbus_addr != 0) 
				  uart_printf("  *(0x%08lx) => 0x%04lx\n", gbus_addr, gbus_read_uint16(0, gbus_addr));
			  else 
				  uart_printf("  Invalid gbus address.\n");
	            }
		    break;
            case '7': {
			  unsigned long gbus_addr, val;
			  gbus_addr = uart_getULong("  GBUS address (aligned by 2): ");
			  if (gbus_addr != 0) {
				  val = uart_getULong("  Data: ") & 0xffff;
				  gbus_write_uint16(0, gbus_addr, val);
				  uart_printf("  *(0x%08lx) <= 0x%04lx\n", gbus_addr, val);
			  } else 
				  uart_printf("  Invalid gbus address.\n");
	            }
		    break;
            case '8': {
			  unsigned long gbus_addr;
			  gbus_addr = uart_getULong("  GBUS address: ");
			  if (gbus_addr != 0) 
				  uart_printf("  *(0x%08lx) => 0x%02lx\n", gbus_addr, gbus_read_uint8(0, gbus_addr));
			  else 
				  uart_printf("  Invalid gbus address.\n");
	            }
		    break;
            case '9': {
			  unsigned long gbus_addr, val;
			  gbus_addr = uart_getULong("  GBUS address: ");
			  if (gbus_addr != 0) {
				  val = uart_getULong("  Data: ") & 0xff;
				  gbus_write_uint8(0, gbus_addr, val);
				  uart_printf("  *(0x%08lx) <= 0x%02lx\n", gbus_addr, val);
			  } else 
				  uart_printf("  Invalid gbus address.\n");
	            }
		    break;
	    case 'F':
            case 'f': {
			  unsigned long freq, mux, fp_divider = 0;

			  freq = uart_getULong("  System freq.: ");

			  if (freq == 0) {
				 uart_puts("  Invalid input value.\n");
				 break;
			  }

			  mux = gbus_read_uint32(0, REG_BASE_system_block + SYS_sysclk_mux);
			  switch((mux >> 8) & 0xf) {
				  case 0: fp_divider = 0x1190000;
					  break;
				  case 2:
				  case 3:
				  case 4:
				  case 5:
				  case 6:
				  case 7: fp_divider = 0x1100000;
					  break;
				  default: uart_puts("No supported divider value.\n");
					   done = 1;
					   break;
			  }

			  gbus_write_uint32(0, REG_BASE_system_block + SYS_sysclk_mux, 
					  gbus_read_uint32(0, REG_BASE_system_block + SYS_sysclk_mux) & 0xfffffffe);
			  gbus_write_uint32(0, REG_BASE_system_block + SYS_clkgen0_pll, fp_divider + ((freq << 1) - 2));
			  gbus_write_uint32(0, REG_BASE_system_block + SYS_sysclk_mux, mux);
			  em86xx_msleep(100);
			  freq = idivide(tango_get_sysclock(), 1000000);
			  uart_printf("\nSystem frequency is now %dMHz.\n", freq);
			  def_freq = freq;
			  mem_test_needed = 1;
			  if (freq < start) {
				  start = freq - 12;
				  end = freq + 28;
			  }
			  if (freq > end) {
				  end = freq + 12;
				  start = freq - 28;
			  }
	            }
		    break;
	    case 'X':
            case 'x':
		    uart_puts("Exiting special mode.\n");
		    done = 1;
		    break;
        }
    }

    if ((mem_test_needed != 0) || (dunit_changed != 0)) {
       uart_puts("\n\nRunning DRAM Adjustment due the system frequency changes .. ");
       em8600_mem_test_find_params(dunit_changed, nblocks, blk_size, gsize, tmask);
       uart_puts("\n\n");
    }
    return(0);
}

#endif /* !CONFIG_SPECIAL_MODE */