loader-stage0.s

1. 8623L平台

cache_init:

    uart_putc_io #'C', r10, r11

#if defined(CONFIG_ENABLE_CACHE) && !defined(CONFIG_BOOTINITONLY)
    mov r0, #0x1c                   @ 512 MB regions (0x10000000)
    orr r0, r0, r0, lsl #8          @ Instruction and Data region size
    mcr p15, 0x0, r0, c6, c0, 0     @ Region Size register (CP15-6)

    mov r0, #0xf000                 @ Enable Instruction Cache for regions over 2GB (4, 5, 6, 7)
    orr r0, r0, #0x00f0             @ Enable Data Cache for regions over 2GB (4, 5, 6, 7)
    mcr p15, 0x0, r0, c2, c0, 0     @ Cacheability Control register (CP15-2)

    mov r0, #0xf0                   @ Enable Writeback for regions over 2GB (4, 5, 6, 7)
    mcr p15, 0x0, r0, c3, c0, 0     @ Writeback Control register (CP15-3)

    ldr r0, =0xffff                 @ Read/write access in any mode
    mcr p15, 0x0, r0, c4, c0, 0     @ Instruction Space Protection register (CP15-4)

    ldr r0, =0xffff                 @ Read/write access in any mode
    mcr p15, 0x0, r0, c5, c0, 0     @ Data Space Protection register (CP15-5)

    mov r0, #0x00                   @ (little-endian)
    orr r0, r0, #0x1000             @ Instruction Cache Enable
    orr r0, r0, #0x0004             @ Data Cache Enable
    orr r0, r0, #0x0002             @ Write Buffering
    orr r0, r0, #0x0001             @ Protection Enable
                                    @ When set, this bit enables caches, protection,
                                    @ and write buffering. When cleared, all are disabled
                                    @ regardless of other bits.
    mcr p15, 0x0, r0, c1, c0, 0     @ Configuration register (CP15-1)

    @ nop cycles for stability (not necessary)
    mov r0, r0
    mov r0, r0
    mov r0, r0
    mov r0, r0
#endif

@
@ do other initialization
@

misc_init:

#ifdef CONFIG_BOOTINITONLY
    @
    @ this procedure is done by em86xx_bootconfig()
    @

    @ load configvalid
    ldr r3, data_configvalid

    @ setup PCI subsystem ID
    ldr r0, =(REG_BASE_HOST + PCI_devcfg_base)
    ldr r1, data_pci_subsystem_id
    tst r3, #CONFIGVALID_PCISUBID
    strne r1, [r0, #(PCI_devcfg_reg2 - PCI_devcfg_base)]

    @ setup PCI revision
    ldr r1, [r0, #(PCI_devcfg_reg1 - PCI_devcfg_base)]
    ldr r2, data_pci_revision_id
    bic r1, r1, #0xff
    orr r1, r1, r2
    tst r3, #CONFIGVALID_PCIREVID
    strne r1, [r0, #(PCI_devcfg_reg1 - PCI_devcfg_base)]

    @ setup PCI memory size
    ldr r1, [r0, #(PCI_devcfg_reg3 - PCI_devcfg_base)]
    ldr r2, data_pci_memory_size
    bic r1, r1, #0x07
    orr r1, r1, r2
    tst r3, #CONFIGVALID_PCIMEMSIZE
    strne r1, [r0, #(PCI_devcfg_reg3 - PCI_devcfg_base)]

    @ set PCI configuration valid bit
    mov r1, #0x00010000
    str r1, [r0, #(PCI_host_host_reg2 - PCI_devcfg_base)]

    @
    @ this procedure is done by em86xx_init()
    @

    @ setup remap register
    ldr r0, =(REG_BASE_CPU + CPU_remap)
    ldr r1, =(DRAMBASE)
    str r1, [r0]

    @ setup GPIO and IRQ mapping
    ldr r0, =(REG_BASE_SYSTEM + SYS_gpio_int)
    ldr r1, =(DEFAULT_IRQ_GPIOMAP)
    str r1, [r0]

    @ setup peripheral bus interface
    ldr r0, =(REG_BASE_HOST + PB_cfg_base)
    ldr r1, =(DEFAULT_PB_DEFAULT_TIMING)
    str r1, [r0, #(PB_default_timing - PB_cfg_base)]

    ldr r1, =(DEFAULT_PB_CS_CONFIG)
    str r1, [r0, #(PB_cs_config - PB_cfg_base)]

    @ setup timing 0 
    @ r0 is already set before
    ldr r1, =(DEFAULT_PB_TIMING0)
    str r1, [r0, #(PB_timing0 - PB_cfg_base)]
    ldr r1, =(DEFAULT_PB_USE_TIMING0)
    str r1, [r0, #(PB_use_timing0 - PB_cfg_base)]

    @ setup timing 1
    ldr r1, =(DEFAULT_PB_TIMING1)
    str r1, [r0, #(PB_timing1 - PB_cfg_base)]
    ldr r1, =(DEFAULT_PB_USE_TIMING1)
    str r1, [r0, #(PB_use_timing1 - PB_cfg_base)]

    @ setup timing 2
    ldr r1, =(DEFAULT_PB_TIMING2)
    str r1, [r0, #(PB_timing2 - PB_cfg_base)]
    ldr r1, =(DEFAULT_PB_USE_TIMING2)
    str r1, [r0, #(PB_use_timing2 - PB_cfg_base)]

    @ setup timing 3
    ldr r1, =(DEFAULT_PB_TIMING3)
    str r1, [r0, #(PB_timing3 - PB_cfg_base)]
    ldr r1, =(DEFAULT_PB_USE_TIMING3)
    str r1, [r0, #(PB_use_timing3 - PB_cfg_base)]

    @ setup timing 4
    ldr r1, =(DEFAULT_PB_TIMING4)
    str r1, [r0, #(PB_timing4 - PB_cfg_base)]
    ldr r1, =(DEFAULT_PB_USE_TIMING4)
    str r1, [r0, #(PB_use_timing4 - PB_cfg_base)]

    @ setup timing 5
    ldr r1, =(DEFAULT_PB_TIMING5)
    str r1, [r0, #(PB_timing5 - PB_cfg_base)]
    ldr r1, =(DEFAULT_PB_USE_TIMING5)
    str r1, [r0, #(PB_use_timing5 - PB_cfg_base)]
#endif

@
@ DRAM adjustment
@

#ifdef CONFIG_DRAMADJUSTMENT
    uart_putc_io #'M', r10, r11

    @ setup stack for C codes
    @ EM86XX has internal memory at REG_BASE_CPU
    @ use internal memory for stack of C functions
    ldr r1, =(REG_BASE_CPU + STAGE0_XTRA_STACK_SIZE)
    mov sp, r1

    @ call xtra_stage0() function
    ldr r0, =(STAGE0_CONFIG_ADDR)       @ first parameter
    ldr r1, =(STAGE0_XTRA_IMAGE_START)  @ new PC
    orr r1, r1, #0x80000000		@ jump to cache-on area
    mov lr, pc
    mov pc, r1                          @ emulate 'bl' instruction

    uart_putc #'m', r10, r11
#endif

@
@ Crypto stage 0
@

#ifdef CONFIG_ENABLE_CRYPTO_FULL
    uart_putc_io #'X', r10, r11
 
#if defined(CONFIG_BOOTFROM_SFLASH)
    @ set periphal bus default timing compatible with high CPU clock
    ldr r0, =(REG_BASE_HOST + PB_default_timing)
    ldr r2, data_pb_default_timing
    str r2, [r0]
    mov r0, r0
    mov r0, r0
    mov r0, r0
    b   2f
data_pb_default_timing:         
    .long DEFAULT_PB_DEFAULT_TIMING
2:
#endif
   
    @ setup stack for C codes
    @ EM86XX has internal memory at REG_BASE_CPU
    @ use internal memory for stack of C functions
    ldr r1, =(REG_BASE_CPU + STAGE0_CRYPTO_STACK_SIZE)
    mov sp, r1

    @ call crypto stage 0 entry function
    ldr r1, =(STAGE0_CRYPTO_IMAGE_START)  @ new PC
    mov lr, pc
    mov pc, r1                          @ emulate 'bl' instruction
    
    uart_putc #'x', r10, r11
#endif

@
@ production test
@

#ifdef CONFIG_PRODUCTIONTEST
    uart_putc_io #'T', r10, r11

    @ setup stack for C codes
    @ EM86XX has internal memory at REG_BASE_CPU
    @ use internal memory for stack of C functions
    ldr r1, =(REG_BASE_CPU + STAGE0_TEST_STACK_SIZE)
    mov sp, r1

    @ call test_stage0() function
    ldr r0, =(STAGE0_CONFIG_ADDR)       @ first parameter
    ldr r1, =(STAGE0_TEST_IMAGE_START)  @ new PC
    orr r1, r1, #0x80000000		@ jump to cache-on area
    mov lr, pc
    mov pc, r1                          @ emulate 'bl' instruction

    uart_putc #'t', r10, r11
#endif

@
@ load main boot loader to DRAM
@

#if defined(CONFIG_BOOTINITONLY) || defined(CONFIG_ENABLE_CRYPTO_FULL)

loop:
    b loop

#else
#if defined(CONFIG_ENABLE_CRYPTO)
    @ Done by the ucode if crypto fully enabled
    @ copy key zone to DRAM
    ldr r1, =BASE_KEY_ZONE
    ldr r2, =END_KEY_ZONE
    ldr r3, =MEM_BASE_KEY_ZONE
    bl copy_func
#endif

    @ copy boot loader
load_to_dram:

#ifdef CONFIG_ENABLE_COPYONRAM
    adr r1, copy_func
    adr r2, copy_func_end
    ldr r3, =CONFIG_COPYONRAM_ADDR
    mov r9, r3
    bl copy_func
#endif

#if defined(CONFIG_ENABLE_2NDBOOT) && defined(BOOT_2NDBOOT)
    @ First check the secondary boot loader is OK
    @   1. signature in offset CFG_2NDBOOT matches
    @   2. verify the checksum
    @ If OK, copy this one instead

stage2_check:
    uart_putc_debug_io #'K', r10, r11

#if defined(CONFIG_BOOTFROM_SFLASH)
    @ set periphal bus default timing compatible with high CPU clock
    ldr r0, =(REG_BASE_HOST + PB_default_timing)
    ldr r2, data_pb_default_timing
    str r2, [r0]
    mov r0, r0
    mov r0, r0
    mov r0, r0
    b   2f
data_pb_default_timing:         
    .long DEFAULT_PB_DEFAULT_TIMING
2:
#endif

    ldr r1, data_stage2_image_start
    add r3, r1, #CFG_2NDBOOT
    ldr r3, [r3]
    ldr r0, data_signature

    cmp r3, r0		
    bne stage1_load	@ the signature must matched

    mov r0, #0
    ldr r3, data_stage2_size	@ get the address which contains the size
    ldr r3, [r3]		@ get the size
    add r2, r1, r3

cksum_loop:
    ldr r3, [r1], #4
    add r0, r0, r3
    cmp r1, r2
    blt cksum_loop

    cmp r0, #0		@ check if checksum is 0
    bne stage1_load	@ check not matched, go for the original route

stage2_copy:
    uart_putc_debug_io #'S', r10, r11

    @ load addresses
    ldr r1, data_stage2_image_start
    ldr r3, data_stage2_load_start
    ldr r3, [r3]
    ldr r4, data_stage2_size	@ get the address which contains the size
    ldr r4, [r4]		@ get ths size
    add r2, r1, r4
    bl copy_func

    mov r9, #1
    b load_config_to_dram

data_stage2_image_start:
    .long (MEMORY_BASE_HOST_PFLASH+STAGE1_IMAGE_SIZE)
data_stage2_size:
    @ The size of 2nd image is offset of (CFG_2NDBOOT + 8)
    .long (MEMORY_BASE_HOST_PFLASH+STAGE1_IMAGE_SIZE + CFG_2NDBOOT + 8)
data_stage2_load_start:
    @ The load address of 2nd image is offset of (CFG_2NDBOOT + 4)
    .long (MEMORY_BASE_HOST_PFLASH+STAGE1_IMAGE_SIZE + CFG_2NDBOOT + 4)
data_stage2_entry:
    @ The entry point of 2nd image is offset of (CFG_2NDBOOT + 12)
    .long (MEMORY_BASE_HOST_PFLASH+STAGE1_IMAGE_SIZE + CFG_2NDBOOT + 12)
#endif /* CONFIG_ENABLE_2NDBOOT && BOOT_2NDBOOT */

stage1_load:
    uart_putc_debug_io #'L', r10, r11

    @ load addresses
    adr r0, load_addr
    @ldmia r0, { r1 - r3 }
    ldr r1, [r0, #0x00]     @ STAGE1 image start address
    ldr r2, [r0, #0x04]     @ STAGE1 image end address
    ldr r3, [r0, #0x08]     @ address where loader copys STAGE1 image to

    ldr r4, data_filesize
    cmp r4, #0x00
    addne r2, r1, r4

#ifdef CONFIG_ENABLE_COPYONRAM
    mov lr, pc
    mov pc, r9
#else
    bl copy_func
#endif

    mov r9, #0

    @ copy configuration
load_config_to_dram:

    uart_putc_debug_io #'F', r10, r11

    adr r1, config_start
    adr r2, config_end

#if defined(CONFIG_ENABLE_2NDBOOT) && defined(BOOT_2NDBOOT)
    cmp r9, #0
    beq 1f
    ldr r3, data_stage2_load_start
    ldr r3, [r3]
    add r3, r3, #0x40
    b 2f
#endif /* CONFIG_ENABLE_2NDBOOT && BOOT_2NDBOOT */

1:
    ldr r3, =STAGE1_CONFIG_ADDR

2:
#if defined(CONFIG_BOOTFROM_SFLASH)
    ldr r4, =LOADER_CONFIGBOOTSFLASH
#elif defined(CONFIG_BOOTFROM_FLASH)
    ldr r4, =LOADER_CONFIGBOOTFLASH
#else
    mov r4, #0
#endif
    str r4, [r3], #4

#ifdef CONFIG_ENABLE_COPYONRAM
    mov lr, pc
    mov pc, r9
#else
    bl copy_func
#endif

@
@ jump to boot loader in the RAM
@

boot_main:

    uart_putc_debug_io #'J', r10, r11
    uart_putc_debug_io #'\r', r10, r11
    uart_putc_debug_io #'\n', r10, r11

#if defined(CONFIG_ENABLE_2NDBOOT) && defined(BOOT_2NDBOOT)
    cmp r9, #0
    beq 3f
    ldr r9, data_stage2_entry	@ get stage2 entry point
    ldr r9, [r9]
    b 4f
#endif

3:
    adr r0, load_addr		@ get stage1 entry point
    ldr r9, [r0, #0x0c]

4:
    mov pc, r9

load_addr:
    .long STAGE1_IMAGE_START
    .long STAGE1_IMAGE_END
    .long STAGE1_LOAD_ADDR
    .long STAGE1_START_ADDR

copy_func:
    @ r1 = src, r2 = end of source, r3 = des
    @ destroy r4
    uart_putc_debug_io #'c', r10, r11
copy_func_loop:
    @ldmia r1!, { r4 - r7 }
    @stmia r3!, { r4 - r7 }
    ldr r4, [r1], #4
    str r4, [r3], #4
    cmp r1, r2
    blt copy_func_loop

    mov pc, lr
copy_func_end:

#endif /* CONFIG_BOOTINITONLY || CONFIG_ENABLE_CRYPTO_FULL */
#endif