loader-stage0.s

1. 8623L平台

/*****************************************
 Copyright (c) 2002-2003
 Sigma Designs, Inc. All Rights Reserved
 Proprietary and Confidential
 *****************************************/

/* This file is part of the EM86XX boot loader */

/*
    Stage 0 boot loader
    Boot loader directly executed from Serial Flash or Flash
    by Ho Lee 02/04/2002

    CONFIG_BOOTFROM_SFLASH :
        initializes serial flash and loads image from serial flash
    CONFIG_BOOTFROM_FLASH :
        initializes parallel flash and loads image from parallel flash

    CONFIG_BOOTINITONLY :
        minimizes the boot loader size. it doesn't load stage 1 boot loader.
        just initializes system parameters and sleeps forever.
*/

#define __ASSEMBLY__

#include "config.h"
#include "hardware.h"
#include "irqs.h"
#include "memcfg.h"
#if defined(CONFIG_ENABLE_CRYPTO)
#include <crypto_config.h>
#endif

// #define MINIMUM_SFLASH_BOOTLOADER

#ifdef MINIMUM_SFLASH_BOOTLOADER
#define DEBUG
#else
// #define DEBUG
#endif

#ifdef CONFIG_USE_SYSCLK
#define UART_FREQ ((EM86XX_EXT_CLOCK/((((DEFAULT_CLKGEN_PLL&0x3f0000)>>16)+2)*2))*((DEFAULT_CLKGEN_PLL&0x3ff)+2))
#else
#define UART_FREQ (EM86XX_EXT_CLOCK)
#endif

    .text
    .code 32
    .align 0

    .global stage0_start

#ifdef CONFIG_BOOTFROM_SFLASH
@
@ Serial Flash signature 4 bytes
@

    .long 0x7f02ed7e            @ BYTE 0 : signature = 0x7e (or 0x9e)
                                @ BYTE 1 : signature = 0xed
                                @ BYTE 2 : [6..7] signature = 0
                                @          [5] chip desect clocked = 0
                                @          [0..1] address bits = 2 (24 bits : 3 bytes_in_address - 1)
                                @ BYTE 3 : [7] A8 sent in read command = 0
                                @          [0..6] stuff bits = 0x7f
#endif

    b   stage0_start            @ offset 0x00

@
@ user configurable settings : 0x60 - 4
@

config_start:

data_filesize:                  @ offset 0x04 : stage 1 boot loader size
    .long 0x00000000
data_version:                   @ offset 0x08
//    .long 0x00010000
    .long BOOTLOADER_VERSION
data_signature:                 @ offset 0x0c
    .long LOADER_CONFIGSIGN

data_SYS_clkgen0_pll:           @ offset 0x10
                                @ FIN = EM86XX_EXT_CLOCK (e.g. 27000000)
                                @ clock = (FIN * (N + 2) / (M + 2)) / 2
    @ .long 0x0101002e          @ (46 + 2) / (1 + 2) = 16 : FIN * 16 / 2 = 216.0 MHz
    @ .long 0x0101002b          @ (43 + 2) / (1 + 2) = 15 : FIN * 15 / 2 = 202.5 MHz
    @ .long 0x01010028          @ (40 + 2) / (1 + 2) = 14 : FIN * 14 / 2 = 189.0 MHz
    @ .long 0x01010025          @ (37 + 2) / (1 + 2) = 13 : FIN * 13 / 2 = 175.5 MHz
    @ .long 0x01010022          @ (34 + 2) / (1 + 2) = 12 : FIN * 12 / 2 = 162.0 MHz
    @ .long 0x0101001f          @ (31 + 2) / (1 + 2) = 11 : FIN * 11 / 2 = 148.5 MHz
    @ .long 0x0101001c          @ (28 + 2) / (1 + 2) = 10 : FIN * 10 / 2 = 135.0 MHz
    @ .long 0x01010019          @ (25 + 2) / (1 + 2) = 9 : FIN * 9 / 2 = 121.5 MHz
    @ .long 0x01010016          @ (22 + 2) / (1 + 2) = 8 : FIN * 8 / 2 = 108.0 MHz
    .long DEFAULT_CLKGEN_PLL
data_DRAM0_dunit_cfg:           @ offset 0x14
    @ .long 0xe34000b8
    .long DEFAULT_DRAM0_DUNIT_CFG
data_DRAM1_dunit_cfg:           @ offset 0x18
    @ .long 0xe34000b8
    @ .long 0x133000bc
    @ .long 0x0
    .long DEFAULT_DRAM1_DUNIT_CFG
data_DRAM_dunit_delay0_ctrl:    @ offset 0x1c
    .long DEFAULT_DRAM_DUNIT_DELAY0_CTRL

#if defined(CONFIG_BOOTFROM_SFLASH)
data_SFLA_driver_speed:         @ offset 0x20
    .long DEFAULT_SFLA_DRIVER_SPEED
#elif defined(CONFIG_BOOTFROM_FLASH)
data_pb_default_timing:         @ offset 0x20
    .long DEFAULT_PB_DEFAULT_TIMING
#else
data_specific:                  @ offset 0x20
    .long 0x00000000
#endif
data_pci_subsystem_id:          @ offset 0x24
    .long DEFAULT_PCI_SUBSYSTEM_ID
data_pci_revision_id:           @ offset 0x28
    .long DEFAULT_PCI_REVISION_ID   @ Rev. A = 1, Rev. B = 2
data_pci_memory_size:           @ offset 0x2c
    .long DEFAULT_PCI_MEMORY_SIZE

data_bootflag:                  @ offset 0x30
    @.long BOOTFLAG_NONE
    @.long (BOOTFLAG_BOOT | BOOTFLAG_BOOT_FIRST(BOOTFLAG_MEDIA_HDD))
    @.long (BOOTFLAG_BOOT | BOOTFLAG_BOOT_FIRST(BOOTFLAG_MEDIA_FLASH) | BOOTFLAG_BOOT_SECOND(BOOTFLAG_MEDIA_HDD))
    @.long (BOOTFLAG_BOOT | BOOTFLAG_BOOT_FIRST(BOOTFLAG_MEDIA_CD))
    .long DEFAULT_BOOTFLAG

data_configvalid:               @ offset 0x34
    .long DEFAULT_CONFIGVALID

data_dramsize:                  @ offset 0x38
    .long CONFIG_DRAMSIZE(DEFAULT_DRAM0_SIZE, DEFAULT_DRAM1_SIZE)

data_imagesize:                 @ offset 0x3c : entire image size except serial flash signature
    .long 0x00000000
data_checksum:                  @ offset 0x40 : checksum 
    .long 0x00000000

#ifndef CONFIG_BOOTINITONLY

data_other_config:              @ offset 0x44 - 0x4f
    .long 0x00000000
    .long 0x00000000
    .long 0x00000000

data_boardname:                 @ offset 0x50 - 0x5f
#ifdef CONFIG_SUBBOARD
    .ascii CONFIG_SUBBOARD
    .space 0x10 - CONFIG_SUBBOARD_LEN, 0x00
#else
    .space 0x10, 0x00
#endif
#endif

config_end:

@
@ debugging
@
@ uart_init : initialize UART 0
@ uart_putc : print out one character (debug, production test)
@ uart_putc_debug : print out one character (debug only)
@

#if defined(DEBUG) || defined(CONFIG_PRODUCTIONTEST) || defined(DEBUG_DRAMADJUSTMENT)
    .equ    UART_INTEN, 0x08
    .equ    UART_FIFOCTL, 0x10
    .equ    UART_LINECTL, 0x14
    .equ    UART_CLKDIV, 0x28
    .equ    UART_CLKSEL, 0x2c

    .macro uart_init, reg1, reg2
    ldr \reg1, =(REG_BASE_CPU + CPU_uart0_base)
    mov \reg2, #0x00            @ disable interrupt
    str \reg2, [\reg1, #UART_INTEN]
    mov \reg2, #0x1f
    str \reg2, [\reg1, #UART_FIFOCTL]
    mov \reg2, #0x03            @ N-8-1
    str \reg2, [\reg1, #UART_LINECTL]
#ifdef CONFIG_USE_SYSCLK
    mov \reg2, #0x00            @ internal clock
#else
    mov \reg2, #0x01            @ external clock
#endif
    str \reg2, [\reg1, #UART_CLKSEL]
#if 0
#if DEFAULT_UART_BAUDRATE == 115200
    @mov \reg2, #81              @ 148.5MHz, 115200bps
    mov \reg2, #91             @ 166MHz, 115200bps
#else
    @mov \reg2, #242             @ 148.5MHz, 38400bps
    @mov \reg2, #206             @ 126MHz, 38400bps
    mov \reg2, #0x100          @ 166MHz, 38400bps
    orr \reg2, \reg2, #0x0f        @ 166MHz, 38400bps
#endif
#else
#if (UART_FREQ/(16*DEFAULT_UART_BAUDRATE)) < 0x100
    mov \reg2, #(UART_FREQ/(16*DEFAULT_UART_BAUDRATE))
#else
    mov \reg2, #0x100
    orr \reg2, \reg2, #((UART_FREQ/(16*DEFAULT_UART_BAUDRATE))-0x100)
#endif
#endif
    str \reg2, [\reg1, #UART_CLKDIV]
    .endm

    .macro uart_putc, ch, reg1, reg2
#if 0
1:
    ldr \reg1, =(REG_BASE_CPU + CPU_uart0_linestat)
    ldr \reg1, [\reg1]
    and \reg1, \reg1, #0x20
    beq 1b
#endif
    ldr \reg1, =(REG_BASE_CPU + CPU_uart0_txd)
    mov \reg2, \ch
    str \reg2, [\reg1]
    .endm

    .macro uart_putc_io, ch, regio, reg2
    mov \reg2, \ch
    str \reg2, [\regio]
    .endm
#else
    .macro uart_init, reg1, reg2
    .endm

    .macro uart_putc, ch, reg1, reg2
    .endm

    .macro uart_putc_io, ch, regio, reg2
    .endm
#endif

#ifdef DEBUG
    .macro uart_putc_debug_io, ch, regio, reg2
    mov \reg2, \ch
    str \reg2, [\regio]
    .endm
#else
    .macro uart_putc_debug_io, ch, regio, reg2
    .endm
#endif

@
@ initialize Serial Flash & PLL
@ After hard reset, CPU operates at 13.5MHz
@

stage0_start:
    @ internally use :
    @  r0, r1 : register
    @  r2 : data

#if defined(CONFIG_BOOTFROM_SFLASH)
    @ set serial flash speed compatible with high CPU clock
    ldr r0, =(REG_BASE_HOST + SFLA_driver_speed)
    ldr r2, data_SFLA_driver_speed
    str r2, [r0]
#elif defined(CONFIG_BOOTFROM_FLASH)
    @ set periphal bus default timing compatible with high CPU clock
    ldr r0, =(REG_BASE_HOST + PB_default_timing)
    ldr r2, data_pb_default_timing
    str r2, [r0]
#endif

    @ set PLL
    ldr r1, =(REG_BASE_SYSTEM + SYS_clkgen0_pll)
    ldr r2, data_SYS_clkgen0_pll
    str r2, [r1]

    mov r0, #0
    mov r1, #4096
1:
    cmp r0, r1
    beq 2f
    add r0, r0, #1
    b 1b

2:
    @ set clock MUX
    ldr r1, =(REG_BASE_SYSTEM + SYS_sysclk_mux)
    mov r2, #1
    str r2, [r1]

    @ invalidate and disable caches
    mov r0, #0x00
    mcr p15, 0x0, r0, c7, c5, 0     @ Invalidate Instruction Cache (all)
    mcr p15, 0x0, r0, c7, c6, 0     @ Invalidate Data Cache (all)
    mcr p15, 0x0, r0, c1, c0, 0     @ disable all cache

    @ setup initial fiq stack top
setup_fiq_stack:
    mrs r1, cpsr		    @ save old cpsr
    msr cpsr_c, #0xd1		    @ FIQ mode, disable IRQ/FIQ
    ldr r0, =(DRAM0_BASE + FM_IRQHANDLER_STACKTOP_FIQ) @ growing downward
    mov sp, r0			    @ set stack
    msr cpsr_c, r1		    @ restore old cpsr

#ifdef MINIMUM_SFLASH_BOOTLOADER
    /* This portion of codes is for chips like 8622/8625 where the
       serial flash is embedded. What it'll do is to probe the
       parallel flash with the bootloader's signature. Map the found
       parallel flash to 0 with CPU_remap, and jump to it. */
#if defined(CONFIG_BOOTFROM_SFLASH)
    uart_init r10, r11
    uart_putc #'P', r10, r11
setup_pflash_timing:
    @ set periphal bus default timing compatible with high CPU clock
    ldr r0, =(REG_BASE_HOST + PB_default_timing)
    ldr r2, data_pb_default_timing
    str r2, [r0]
    ldr r0, =(REG_BASE_HOST + PB_cs_config)
    ldr r2, data_pb_cs_config
    str r2, [r0]
    mov r0, r0
    mov r0, r0
    mov r0, r0
    ldr r0, data_probe_pflash	/* Make absolute jump to sflash address so
				   we're not depend on CPU_remap anymore */
    mov pc, r0

data_pb_default_timing:         
    .long DEFAULT_PB_DEFAULT_TIMING

data_pb_cs_config:
    .long 0x000000ff	/* We need to assume CS0-3 are all pflash
			   (packed mode, 8 bit access) */

data_probe_pflash:
    .long probe_pflash

probe_pflash:	/* Start looking for parallel flash one by one*/
    uart_putc #'1', r10, r11
    ldr r2, data_signature
    ldr r0, =(MEMORY_BASE_HOST_PB_CS(0))
    add r0, r0, #12	/* The offset to signature */

probe_next:
    uart_putc #'2', r10, r11
    ldr r1, [r0]
    cmp r1, r2		/* Try to find the signature within pflash */
    beq found_pflash_image
    add r0, r0, #0x01000000	/* 16MB apart */
    b probe_next
    
found_pflash_image:	/* Found the right parallel flash (r0) */
    uart_putc #'T', r10, r11
    ldr r1, =(REG_BASE_CPU + CPU_remap)
    str r0, [r1]
    mov lr, #0
    mov pc, lr		/* Jump to address 0 */
    nop
#endif
#else /* !MINIMUM_SFLASH_BOOTLOADER */

#ifndef CONFIG_BOOTINITONLY
    @ nop cycles for stability (not necessary)
    mov r0, r0
    mov r0, r0
    mov r0, r0
    mov r0, r0
#endif

@
@ initialize DRAM
@

dram_init:

    uart_init r10, r11
    uart_putc #'D', r10, r11

    @ initialize DRAM controller 0
    uart_putc_io #'1', r10, r11
    mov r0, #REG_BASE_DRAMCTRL0
    ldr r1, data_DRAM0_dunit_cfg
    ldr r2, data_DRAM_dunit_delay0_ctrl
    bl dram_init_ctrl

    @ initialize DRAM controller 1
    uart_putc_io #'2', r10, r11
    mov r0, #REG_BASE_DRAMCTRL1
    ldr r1, data_DRAM1_dunit_cfg
    bl dram_init_ctrl

    b cache_init

dram_init_ctrl:
    @ initialize each DRAM controller
    @ call with :
    @  r0 = base address of DRAM controller register
    @  r1 = setting for DRAM_dunit_cfg
    @    if this setting is 0, just disable the DRAM controller
    @  r2 = setting for DRAM_dunit_delay0_ctrl
    @ internally use :
    @  r3, r4 : register
    @  r5 : data

    @ reset
    add r3, r0, #DRAM_g2l_base
    add r3, r3, #(DRAM_g2l_reset_control - DRAM_g2l_base)
    mov r5, #0x03
    strb r5, [r3]
    cmp r1, #0x00       @ if the DRAM should be disabled
    moveq pc, lr        @ just return here
    mov r5, #0x02
    strb r5, [r3]

    @ DRAM configuration
    add r4, r0, #DRAM_dunit_cfg
    str r1, [r4]

    @ DRAM delay control
    add r4, r0, #DRAM_dunit_delay0_ctrl
    str r2, [r4]

    @ full operation
    mov r5, #0x00
    strb r5, [r3]

    @ return to caller
    mov pc, lr

@
@ cache control
@