📄 mambo.h
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// PCI Timeout (slave)#define PCI_timeout_base 0x8000#define PCI_timeout_value (PCI_timeout_base + 0x00)#define PCI_timeout_status (PCI_timeout_base + 0x04)#define PCI_timer_counter (PCI_timeout_base + 0x08)#define PCI_timer_test_register (PCI_timeout_base + 0x0c)#define PCI_wakeup_register (PCI_timeout_base + 0x10)// PCI SLAVE (directly accessed, slave)#define PCI_slavecfg_base 0x9000#define PCI_slavecfg_region_0_base (PCI_slavecfg_base + 0x00)#define PCI_slavecfg_region_1_base (PCI_slavecfg_base + 0x04)#define PCI_slavecfg_region_2_base (PCI_slavecfg_base + 0x08)#define PCI_slavecfg_region_3_base (PCI_slavecfg_base + 0x0c)#define PCI_slavecfg_region_4_base (PCI_slavecfg_base + 0x10)#define PCI_slavecfg_region_5_base (PCI_slavecfg_base + 0x14)#define PCI_slavecfg_region_6_base (PCI_slavecfg_base + 0x18)#define PCI_slavecfg_region_7_base (PCI_slavecfg_base + 0x1c)#define PCI_slavecfg_irq (PCI_slavecfg_base + 0x20)// PCI host#define PCI_mambo_is_host 0xe000// PCI device configuration#define PCI_devcfg_base 0xfe00#define PCI_devcfg_host_reg2 (PCI_devcfg_base + 0xd6)#define PCI_devcfg_reg0 (PCI_devcfg_base + 0xe8)#define PCI_devcfg_reg1 (PCI_devcfg_base + 0xec)#define PCI_devcfg_reg2 (PCI_devcfg_base + 0xf0)#define PCI_devcfg_reg3 (PCI_devcfg_base + 0xf4)#define PCI_devcfg_config (PCI_devcfg_base + 0xf8)// PCI master access#define PCI_master_base 0xfe00#define PCI_master_read_addr (PCI_master_base + 0xc0)#define PCI_master_read_counter (PCI_master_base + 0xc4)#define PCI_master_read_enable (PCI_master_base + 0xc8)#define PCI_master_read_reverse (PCI_master_base + 0xcc)#define PCI_master_write_addr (PCI_master_base + 0xd8)#define PCI_master_write_counter (PCI_master_base + 0xdc)#define PCI_master_write_enable (PCI_master_base + 0xe0)#define PCI_master_burst (PCI_master_base + 0xe4)// PCI host functionality#define PCI_host_base 0xfe00#define PCI_host_host_reg1 (PCI_host_base + 0xd0)#define PCI_host_host_reg2 (PCI_host_base + 0xd4)// PCI region base (relative to PCI base address 0)#define PCI_region_base 0x9000#define PCI_region_0_base (PCI_region_base + 0x00)#define PCI_region_1_base (PCI_region_base + 0x04)#define PCI_region_2_base (PCI_region_base + 0x08)#define PCI_region_3_base (PCI_region_base + 0x0c)#define PCI_region_4_base (PCI_region_base + 0x10)#define PCI_region_5_base (PCI_region_base + 0x14)#define PCI_region_6_base (PCI_region_base + 0x18)#define PCI_region_7_base (PCI_region_base + 0x1c)/* * DRAM Controllers * * Base Address : MAMBO_DRAMCTRLx_BASE */// DRAM unit configuration#define DRAM_dunit_base 0x0000#define DRAM_dunit_cfg (DRAM_dunit_base + 0x00)#define DRAM_dunit_delay0_ctrl (DRAM_dunit_base + 0x04)#define DRAM_dunit_delay1_ctrl (DRAM_dunit_base + 0x08)#define DRAM_dunit_auto_delay_ctrl (DRAM_dunit_base + 0x0c)#define DRAM_dunit_delay_probe (DRAM_dunit_base + 0x10)#define DRAM_dunit_effective_delay (DRAM_dunit_base + 0x14)#define DRAM_dunit_bw_probe_cfg (DRAM_dunit_base + 0x20)#define DRAM_dunit_bw_probe_cnt (DRAM_dunit_base + 0x24)// MBUS unit configuration#define DRAM_mbus_base 0x0200#define DRAM_mbus_w0_cfg (DRAM_mbus_base + 0x00)#define DRAM_mbus_w1_cfg (DRAM_mbus_base + 0x04)#define DRAM_mbus_w2_cfg (DRAM_mbus_base + 0x08)#define DRAM_mbus_w3_cfg (DRAM_mbus_base + 0x0c)#define DRAM_mbus_w4_cfg (DRAM_mbus_base + 0x10)#define DRAM_mbus_w5_cfg (DRAM_mbus_base + 0x14)#define DRAM_mbus_w6_cfg (DRAM_mbus_base + 0x18)#define DRAM_mbus_r0_cfg (DRAM_mbus_base + 0x40)#define DRAM_mbus_r1_cfg (DRAM_mbus_base + 0x44)#define DRAM_mbus_r2_cfg (DRAM_mbus_base + 0x48)#define DRAM_mbus_r3_cfg (DRAM_mbus_base + 0x4c)#define DRAM_mbus_r4_cfg (DRAM_mbus_base + 0x50)#define DRAM_mbus_r5_cfg (DRAM_mbus_base + 0x54)#define DRAM_mbus_r6_cfg (DRAM_mbus_base + 0x58)#define DRAM_mbus_r7_cfg (DRAM_mbus_base + 0x5c)#define DRAM_mbus_r8_cfg (DRAM_mbus_base + 0x60)#define DRAM_mbus_r9_cfg (DRAM_mbus_base + 0x64)// VBUS unit configuration#define DRAM_vbus_base 0x0300#define DRAM_vbus_r0_cfg (DRAM_vbus_base + 0x00)#define DRAM_vbus_r1_cfg (DRAM_vbus_base + 0x04)#define DRAM_vbus_r2_cfg (DRAM_vbus_base + 0x08)#define DRAM_vbus_r3_cfg (DRAM_vbus_base + 0x0c)#define DRAM_vbus_r4_cfg (DRAM_vbus_base + 0x10)#define DRAM_vbus_r5_cfg (DRAM_vbus_base + 0x14)#define DRAM_vbus_r6_cfg (DRAM_vbus_base + 0x18)#define DRAM_vbus_r7_cfg (DRAM_vbus_base + 0x1c)// GBUS to LBUS bridge#define DRAM_g2l_base 0xff00#define DRAM_g2l_bist_busy (DRAM_g2l_base + 0xe0)#define DRAM_g2l_bist_pass (DRAM_g2l_base + 0xe4)#define DRAM_g2l_bist_mask (DRAM_g2l_base + 0xe8)#define DRAM_g2l_reset_control (DRAM_g2l_base + 0xfc)/* * CPU Block * * Base Address : MAMBO_CPU_BASE */// CPU local ram#define CPU_localmem_base 0x0000 // UART - UART 0#define CPU_uart0_base 0xc100#define CPU_uart0_rxd (CPU_uart0_base + 0x00)#define CPU_uart0_txd (CPU_uart0_base + 0x04)#define CPU_uart0_inten (CPU_uart0_base + 0x08)#define CPU_uart0_intid (CPU_uart0_base + 0x0c)#define CPU_uart0_fifoctl (CPU_uart0_base + 0x10)#define CPU_uart0_linectl (CPU_uart0_base + 0x14)#define CPU_uart0_modemctl (CPU_uart0_base + 0x18)#define CPU_uart0_linestat (CPU_uart0_base + 0x1c)#define CPU_uart0_modemstat (CPU_uart0_base + 0x20)#define CPU_uart0_scratch (CPU_uart0_base + 0x24)#define CPU_uart0_clkdiv (CPU_uart0_base + 0x28)#define CPU_uart0_clkset (CPU_uart0_base + 0x2c)#define CPU_UART0_BASE (MAMBO_CPU_BASE + CPU_uart0_base) /* UART 0 */// UART - UART 1#define CPU_uart1_base 0xc200#define CPU_uart1_rxd (CPU_uart1_base + 0x00)#define CPU_uart1_txd (CPU_uart1_base + 0x04)#define CPU_uart1_inten (CPU_uart1_base + 0x08)#define CPU_uart1_intid (CPU_uart1_base + 0x0c)#define CPU_uart1_fifoctl (CPU_uart1_base + 0x10)#define CPU_uart1_linectl (CPU_uart1_base + 0x14)#define CPU_uart1_modemctl (CPU_uart1_base + 0x18)#define CPU_uart1_linestat (CPU_uart1_base + 0x1c)#define CPU_uart1_modemstat (CPU_uart1_base + 0x20)#define CPU_uart1_scratch (CPU_uart1_base + 0x24)#define CPU_uart1_clkdiv (CPU_uart1_base + 0x28)#define CPU_uart1_clkset (CPU_uart1_base + 0x2c)#define CPU_UART1_BASE (MAMBO_CPU_BASE + CPU_uart1_base) /* UART 0 */// Timer - Timer 0#define CPU_timer0_base 0xc500#define CPU_timer0_load (CPU_timer0_base + 0x00)#define CPU_timer0_value (CPU_timer0_base + 0x04)#define CPU_timer0_ctrl (CPU_timer0_base + 0x08)#define CPU_timer0_clr (CPU_timer0_base + 0x0c)#define CPU_TIMER0_BASE (MAMBO_CPU_BASE + CPU_timer0_base) /* TIMER 0 */// Timer - Timer 1#define CPU_timer1_base 0xc600#define CPU_timer1_load (CPU_timer1_base + 0x00)#define CPU_timer1_value (CPU_timer1_base + 0x04)#define CPU_timer1_ctrl (CPU_timer1_base + 0x08)#define CPU_timer1_clr (CPU_timer1_base + 0x0c)#define CPU_TIMER1_BASE (MAMBO_CPU_BASE + CPU_timer1_base) /* TIMER 1 */// Timer - RTC#define CPU_rtc_base 0xc800#define CPU_rtc_data (CPU_rtc_base + 0x00)#define CPU_rtc_match (CPU_rtc_base + 0x04)#define CPU_rtc_stat (CPU_rtc_base + 0x08)#define CPU_rtc_load (CPU_rtc_base + 0x0c)#define CPU_rtc_ctrl (CPU_rtc_base + 0x10)// Interupt controller - IRQ#define CPU_irq_base 0xe000#define CPU_irq_status (CPU_irq_base + 0x00)#define CPU_irq_rawstat (CPU_irq_base + 0x04)#define CPU_irq_enableset (CPU_irq_base + 0x08)#define CPU_irq_enableclr (CPU_irq_base + 0x0c)#define CPU_irq_softset (CPU_irq_base + 0x10)#define CPU_irq_softclr (CPU_irq_base + 0x14)// Interupt controller - FIQ#define CPU_fiq_base 0xe100#define CPU_fiq_status (CPU_fiq_base + 0x00)#define CPU_fiq_rawstat (CPU_fiq_base + 0x04)#define CPU_fiq_enableset (CPU_fiq_base + 0x08)#define CPU_fiq_enableclr (CPU_fiq_base + 0x0c)#define CPU_fiq_softset (CPU_fiq_base + 0x10)#define CPU_fiq_softclr (CPU_fiq_base + 0x14)// Interrupt controller - Edge detector#define CPU_edge_base 0xe200#define CPU_edge_status (CPU_edge_base + 0x00)#define CPU_edge_rawstat (CPU_edge_base + 0x04)#define CPU_edge_config_rise (CPU_edge_base + 0x08)#define CPU_edge_config_fall (CPU_edge_base + 0x0c)// PT110 to GBUS bridge#define CPU_remap 0xf000#define CPU_REMAP (MAMBO_CPU_BASE + CPU_remap)// RESET#define CPU_reset 0xfffc#define CPU_RESET (MAMBO_HOST_BASE + CPU_reset)/* * Video Output * * Base Address : MAMBO_VIDEOOUT_BASE *//* * MPEG Engine * * Base Address : MAMBO_MPEGx_BASE *//* * Transport Demux * * Base Address : MAMBO_TSDEMUX_BASE *//* * Audio Block * * Base Address : MAMBO_AUDIOx_BASE *//* * Others */#define UART_NR 2 // number of UART port. // needed by drivers/char/serial_mambo.c/* * Clock * * Only use timer 1 & 2 * (both run at 24MHz and will need the clock divider set to 16). * * Timer 0 runs at bus frequency and therefore could vary and currently * uHAL can't handle that. * */// PLL input clock, typically 27 Mhz#define MAMBO_EXT_CLOCK 27000000 #endif⌨️ 快捷键说明
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