📄 mambo.h
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/* * linux/include/asm-arm/arch-mambo/hardware.h * * Copyright 2002-2003, Sigma Designs, Inc * * This file contains the hardware definitions for Mambo. * * by Ho Lee 01/27/2003 */#ifndef __ASM_ARCH_HARDWARE_H#define __ASM_ARCH_HARDWARE_H/* macro to get at IO space when running virtually *//* but we are not here... */#define IO_ADDRESS(x) (x)/* ------------------------------------------------------------------------ * Mambo Registers * ------------------------------------------------------------------------ *//* * Mambo Register Base Addresses */// Configuration Memory#define MAMBO_CONFIG_BASE 0x00000000#define MAMBO_SYSTEM_BASE 0x00010000 /* System Block */#define MAMBO_HOST_BASE 0x00020000 /* Host Interface */ #define MAMBO_DRAMCTRL0_BASE 0x00030000 /* DRAM Controller 0 */#define MAMBO_DRAMCTRL1_BASE 0x00040000 /* DRAM Controller 1 */#define MAMBO_DRAMCTRL2_BASE 0x00050000 /* DRAM Controller 2 */#define MAMBO_CPU_BASE 0x00060000 /* CPU Block */#define MAMBO_VIDEOUT_BASE 0x00070000 /* Video Output */#define MAMBO_MPEG0_BASE 0x00080000 /* MPEG Engine 0 */#define MAMBO_MPEG1_BASE 0x00090000 /* MPEG Engine 1 */#define MAMBO_TSDEMUX_BASE 0x000a0000 /* Transport Demux */#define MAMBO_AUDIO0_BASE 0x000c0000 /* Audio Block 0 */#define MAMBO_AUDIO1_BASE 0x000d0000 /* Audio Block 1 */// RISC Memories#define MAMBO_RISC_BASE 0x00100000#define MAMBO_MPEG0_RISC_BASE 0x00100000 /* MPEG Engine 0 RISC */#define MAMBO_MPEG1_RISC_BASE 0x00120000 /* MPEG Engine 1 RISC */#define MAMBO_TSDEMUX_RISC_BASE 0x00140000 /* Transport Demux RISC */#define MAMBO_AUDIO0_DSP_BASE 0x00180000 /* Audio Block 0 DSP */#define MAMBO_AUDIO1_DSP_BASE 0x001a0000 /* Audio Block 1 DSP */// DRAM Memories#define MAMBO_DRAM0_MEMORY_BASE 0x10000000 /* Memory controlled by DRAM controller 0 */#define MAMBO_DRAM1_MEMORY_BASE 0x20000000 /* Memory controlled by DRAM controller 1 */#define MAMBO_DRAM2_MEMORY_BASE 0x30000000 /* Memory controlled by DRAM controller 2 */// Host Memories#define MAMBO_HOST_SFLASH_BASE 0x40000000 /* Serial Flash */#define MAMBO_HOST_PB0_BASE 0x44000000 /* Peripheral Bus CS #0 Memory */#define MAMBO_HOST_PB1_BASE 0x45000000 /* Peripheral Bus CS #1 Memory */#define MAMBO_HOST_PB2_BASE 0x46000000 /* Peripheral Bus CS #2 Memory */#define MAMBO_HOST_PB3_BASE 0x47000000 /* Peripheral Bus CS #3 Memory */// PCI Memories#define MAMBO_PCI_CONFIG_BASE 0x50000000 /* PCI configuration */#define MAMBO_PCI_IO_BASE 0x58000000 /* PCI I/O space */#define MAMBO_PCI_MEMORY_BASE 0x60000000 /* PCI Memory Base */#define MAMBO_PCI_IO_BUS_BASE 0x08000000 /* PCI I/O space on the bus */#define MAMBO_PCI_MEMORY_BUS_BASE 0x00000000 /* PCI Memory Base on the bus */// Misc#define MAMBO_DMABLE_MEM_SIZE 0x00400000 /* reserve first part of memory for DMA *//* * System Block * * Base Address : MAMBO_SYSTEM_BASE */// Clock generator resgiers #define SYS_clkgen_base 0x0000#define SYS_clkgen0_pll (SYS_clkgen_base + 0x00)#define SYS_clkgen0_div (SYS_clkgen_base + 0x04)#define SYS_clkgen1_pll (SYS_clkgen_base + 0x08)#define SYS_clkgen1_div (SYS_clkgen_base + 0x0c)#define SYS_clkgen2_pll (SYS_clkgen_base + 0x10)#define SYS_clkgen2_div (SYS_clkgen_base + 0x14)#define SYS_clkgen3_pll (SYS_clkgen_base + 0x18)#define SYS_clkgen3_div (SYS_clkgen_base + 0x1c)#define SYS_avclk_mux (SYS_clkgen_base + 0x38)#define SYS_sysclk_mux (SYS_clkgen_base + 0x3c)// Clock cycle counters #define SYS_clk_cnt (SYS_clkgen_base + 0x40)#define SYS_xtal_in_cnt (SYS_clkgen_base + 0x48)#define SYS_xcvo0_in_cnt (SYS_clkgen_base + 0x50)#define SYS_vcxo1_in_cnt (SYS_clkgen_base + 0x58)#define SYS_rclk_out_cnt (SYS_clkgen_base + 0x60)#define SYS_set_clk_cnt (SYS_clkgen_base + 0x6c)// MBUS arbiter #define MARB_base 0x0200#define MARB_mid01_cfg (MARB_base + 0x00)#define MARB_mid21_cfg (MARB_base + 0x04)#define MARB_mid02_cfg (MARB_base + 0x08)#define MARB_mid22_cfg (MARB_base + 0x0c)#define MARB_mid04_cfg (MARB_base + 0x10)#define MARB_mid24_cfg (MARB_base + 0x14)#define MARB_mid25_cfg (MARB_base + 0x18)#define MARB_mid08_cfg (MARB_base + 0x1c)#define MARB_mid28_cfg (MARB_base + 0x20)#define MARB_mid29_cfg (MARB_base + 0x24)#define MARB_mid0c_cfg (MARB_base + 0x28)#define MARB_mid2c_cfg (MARB_base + 0x2c)#define MARB_mid10_cfg (MARB_base + 0x30)#define MARB_mid30_cfg (MARB_base + 0x34)#define MARB_mid31_cfg (MARB_base + 0x38)#define MARB_mid12_cfg (MARB_base + 0x3c)#define MARB_mid32_cfg (MARB_base + 0x40)// VBUS arbiter #define VARB_base 0x0300#define VARB_mid01_cfg (VARB_base + 0x00)#define VARB_mid02_cfg (VARB_base + 0x04)#define VARB_mid21_cfg (VARB_base + 0x08)#define VARB_mid22_cfg (VARB_base + 0x0c)#define VARB_mid23_cfg (VARB_base + 0x10)#define VARB_mid24_cfg (VARB_base + 0x14)#define VARB_mid25_cfg (VARB_base + 0x18)#define VARB_mid26_cfg (VARB_base + 0x1c)#define VARB_mid27_cfg (VARB_base + 0x20)#define VARB_mid28_cfg (VARB_base + 0x24)#define VARB_mid29_cfg (VARB_base + 0x28)#define VARB_mid2a_cfg (VARB_base + 0x2c)#define VARB_mid10_cfg (VARB_base + 0x30)#define VARB_mid30_cfg (VARB_base + 0x34)#define VARB_mid31_cfg (VARB_base + 0x38)// IBUS arbiter#define IARB_base 0x0400#define IARB_mid01_cfg (IARB_base + 0x00)#define IARB_mid02_cfg (IARB_base + 0x04)// GPIO #define SYS_gpio_base 0x0500#define SYS_gpio_dir (SYS_gpio_base + 0x00)#define SYS_gpio_data (SYS_gpio_base + 0x04)#define SYS_gpio_irq (SYS_gpio_base + 0x08)#define SYS_gpio15_pwm (SYS_gpio_base + 0x10)#define SYS_gpio14_pwm (SYS_gpio_base + 0x14)#define GPIO_DIR_INPUT(gpio) ((1 << (16 + (gpio))))#define GPIO_DIR_OUTPUT(gpio) ((1 << (16 + (gpio))) | (1 << (gpio)))#define GPIO_DATA_SET(gpio) ((1 << (16 + (gpio))) | (1 << (gpio)))#define GPIO_DATA_CLEAR(gpio) ((1 << (16 + (gpio))))/* * Host Interface * * Base Address : MAMBO_HOST_BASE */// Peripheral bus Registers#define HOST_pb0_base 0x0000#define HOST_pb1_base 0x0200#define HOST_pb2_base 0x0400#define HOST_pb3_base 0x0600// Peripheral bus CS #0 : IDE // Peripheral bus CS #1 : IDE #define PB_ide_base (HOST_pb0_base)#define PB_ide_data (PB_ide_base + 0x0000)#define PB_ide_error (PB_ide_base + 0x0004)#define PB_ide_count (PB_ide_base + 0x0008)#define PB_ide_start_sector (PB_ide_base + 0x000c)#define PB_ide_cylinder_lo (PB_ide_base + 0x0010)#define PB_ide_cylinder_hi (PB_ide_base + 0x0014)#define PB_ide_head_device (PB_ide_base + 0x0018)#define PB_ide_cmd_stat0 (PB_ide_base + 0x001c)#define PB_ide_irq_stat (PB_ide_base + 0x0218)#define PB_ide_cmd_stat1 (PB_ide_base + 0x021c)#define MAMBO_IDE_BASE (MAMBO_HOST_BASE + PB_ide_base) // ATAPI registers#define MAMBO_IDE_DMA_BASE (0x00500e00) // IDE bus mastering interface// Peripheral bus CS #2 : Parallel Flash / FlexROM III#define PB_pfla_base (HOST_pb2_base)// Peripheral bus configuration#define PB_cfg_base 0x0800#define PB_timing0 (PB_cfg_base + 0x00)#define PB_timing1 (PB_cfg_base + 0x04)#define PB_timing2 (PB_cfg_base + 0x08)#define PB_timing3 (PB_cfg_base + 0x0c)#define PB_timing4 (PB_cfg_base + 0x10)#define PB_timing5 (PB_cfg_base + 0x14)#define PB_default_timing (PB_cfg_base + 0x18)#define PB_use_timing0 (PB_cfg_base + 0x1c)#define PB_use_timing1 (PB_cfg_base + 0x20)#define PB_use_timing2 (PB_cfg_base + 0x24)#define PB_use_timing3 (PB_cfg_base + 0x28)#define PB_use_timing4 (PB_cfg_base + 0x2c)#define PB_use_timing5 (PB_cfg_base + 0x30)#define PB_cs_config (PB_cfg_base + 0x34)#define PB_automode_start_address (PB_cfg_base + 0x40)#define PB_automode_control (PB_cfg_base + 0x44)// Switch Box #define SBOX_base 0x1000#define SBOX_reset (SBOX_base + 0x00)#define SBOX_route (SBOX_base + 0x04)// Serial flash#define SFLA_base 0xa000#define SFLA_status (SFLA_base + 0x00)#define SFLA_read_parameters (SFLA_base + 0x08)#define SFLA_driver_speed (SFLA_base + 0x10)#define SFLA_n_for_send_get (SFLA_base + 0x20)#define SFLA_read_data (SFLA_base + 0x30)#define SFLA_send_1 (SFLA_base + 0x40)#define SFLA_send_8 (SFLA_base + 0x44)#define SFLA_send_16 (SFLA_base + 0x48)#define SFLA_send_32 (SFLA_base + 0x4c)#define SFLA_send_get_1 (SFLA_base + 0x50)#define SFLA_send_get_8 (SFLA_base + 0x54)#define SFLA_send_get_16 (SFLA_base + 0x58)#define SFLA_send_get_32 (SFLA_base + 0x5c)#define SFLA_chip_select (SFLA_base + 0x60)#define SFLA_chip_deselect (SFLA_base + 0x64)#define SFLA_send_n (SFLA_base + 0x68)#define SFLA_send_n_ (SFLA_base + 0x6c)#define SFLA_get_slaveout (SFLA_base + 0x70)#define SFLA_wait_timer (SFLA_base + 0x74)#define SFLA_send_get_n (SFLA_base + 0x78)#define SFLA_send_get_n_ (SFLA_base + 0x7c)// MBUS interface#define MIF_w0_base 0xb000#define MIF_w1_base 0xb040#define MIF_r0_base 0xb080#define MIF_r1_base 0xb0c0#define MIF_add_offset 0x00#define MIF_cnt_offset 0x04#define MIF_add2_skip_offset 0x08#define MIF_cmd_offset 0x0c#define MIF_w0_add (MIF_w0_base + 0x00)#define MIF_w0_cnt (MIF_w0_base + 0x04)#define MIF_w0_add2_skip (MIF_w0_base + 0x08)#define MIF_w0_cmd (MIF_w0_base + 0x0c)#define MIF_w1_add (MIF_w1_base + 0x00)#define MIF_w1_cnt (MIF_w1_base + 0x04)#define MIF_w1_add2_skip (MIF_w1_base + 0x08)#define MIF_w1_cmd (MIF_w1_base + 0x0c)#define MIF_r0_add (MIF_r0_base + 0x00)#define MIF_r0_cnt (MIF_r0_base + 0x04)#define MIF_r0_add2_skip (MIF_r0_base + 0x08)#define MIF_r0_cmd (MIF_r0_base + 0x0c)#define MIF_r1_add (MIF_r1_base + 0x00)#define MIF_r1_cnt (MIF_r1_base + 0x04)#define MIF_r1_add2_skip (MIF_r1_base + 0x08)#define MIF_r1_cmd (MIF_r1_base + 0x0c)⌨️ 快捷键说明
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