emhwlib_registers_tango2.h

1. 8623L平台

#define demux_cipher_des_flags 0x2e58 /* width RMuint32 */
#define demux_cipher_dvbcsa_key_lsb 0x2e5c /* width RMuint32 */
#define demux_cipher_dvbcsa_key_msb 0x2e5d /* width RMuint32 */
#define demux_cipher_dvbcsa_flags 0x2e5e /* width RMuint32 */
#define demux_cipher_aes_key_1 0x2e60 /* width RMuint32 */
#define demux_cipher_aes_key_2 0x2e61 /* width RMuint32 */
#define demux_cipher_aes_key_3 0x2e62 /* width RMuint32 */
#define demux_cipher_aes_key_4 0x2e63 /* width RMuint32 */
#define demux_cipher_aes_key_5 0x2e64 /* width RMuint32 */
#define demux_cipher_aes_key_6 0x2e65 /* width RMuint32 */
#define demux_cipher_aes_key_7 0x2e66 /* width RMuint32 */
#define demux_cipher_aes_key_8 0x2e67 /* width RMuint32 */
#define demux_cipher_aes_flags 0x2e68 /* width RMuint32 */
#define demux_cipher_aes_IV_1 0x2e69 /* width RMuint32 */
#define demux_cipher_aes_IV_2 0x2e6a /* width RMuint32 */
#define demux_cipher_aes_IV_3 0x2e6b /* width RMuint32 */
#define demux_cipher_aes_IV_4 0x2e6c /* width RMuint32 */
#define demux_cipher_aes_IV_5 0x2e6d /* width RMuint32 */
#define demux_cipher_aes_IV_6 0x2e6e /* width RMuint32 */
#define demux_cipher_aes_IV_7 0x2e6f /* width RMuint32 */
#define demux_cipher_aes_IV_8 0x2e70 /* width RMuint32 */
#define demux_cipher_dvd_cnt 0x2e78 /* width RMuint32 */
#define demux_cipher_dvd_tklo 0x2e7a /* width RMuint32 */
#define demux_cipher_dvd_tkhi 0x2e7b /* width RMuint32 */
#define demux_cipher_dvd_state0 0x2e7c /* width RMuint32 */
#define demux_cipher_dvd_state1 0x2e7d /* width RMuint32 */
#define demux_cw_ram_multi2_syst_key 0x2a00 /* width RMuint32 */
#define demux_cw_ram_multi2_data_key 0x2a80 /* width RMuint32 */
#define demux_cw_ram_multi2_iv 0x2aa0 /* width RMuint32 */
#define demux_cw_ram_rc4_key 0x2ac0 /* width RMuint32 */
#define demux_cw_ram_aes_key 0x2b00 /* width RMuint32 */
#define demux_cw_ram_aes_iv 0x2b08 /* width RMuint32 */
#define demux_cw_ram_dvbcsa_key 0x2b60 /* width RMuint32 */
#define demux_cw_ram_des_key1 0x2b80 /* width RMuint32 */
#define demux_cw_ram_des_key2 0x2ba0 /* width RMuint32 */
#define demux_cw_ram_des_key3 0x2bc0 /* width RMuint32 */
#define demux_cw_ram_des_iv 0x2be0 /* width RMuint32 */
#define demux_section_filter_start 0x3800 /* width RMuint32 */
#define demux_channel_status_control 0x3e08 /* width RMuint32 */
#define demux_channel_config_routing 0x3e09 /* width RMuint32 */
#define demux_ts_frame_size 0x3e0a /* width RMuint32 */
#define demux_pat0_pidentry 0x3cc0 /* width RMuint32 */
#define demux_pat0_outputmask 0x3cc1 /* width RMuint32 */
#define demux_cat0_pidentry 0x3cc2 /* width RMuint32 */
#define demux_cat0_outputmask 0x3cc3 /* width RMuint32 */
#define demux_mgt0_pidentry 0x3cc4 /* width RMuint32 */
#define demux_mgt0_outputmask 0x3cc5 /* width RMuint32 */
#define demux_pcr0_pidentry 0x3cc6 /* width RMuint32 */
#define demux_pat1_pidentry 0x3cc8 /* width RMuint32 */
#define demux_pat1_outputmask 0x3cc9 /* width RMuint32 */
#define demux_cat1_pidentry 0x3cca /* width RMuint32 */
#define demux_cat1_outputmask 0x3ccb /* width RMuint32 */
#define demux_mgt1_pidentry 0x3ccc /* width RMuint32 */
#define demux_mgt1_outputmask 0x3ccd /* width RMuint32 */
#define demux_pcr1_pidentry 0x3cce /* width RMuint32 */
#define demux_pat2_pidentry 0x3cd0 /* width RMuint32 */
#define demux_pat2_outputmask 0x3cd1 /* width RMuint32 */
#define demux_cat2_pidentry 0x3cd2 /* width RMuint32 */
#define demux_cat2_outputmask 0x3cd3 /* width RMuint32 */
#define demux_mgt2_pidentry 0x3cd4 /* width RMuint32 */
#define demux_mgt2_outputmask 0x3cd5 /* width RMuint32 */
#define demux_pcr2_pidentry 0x3cd6 /* width RMuint32 */
#define demux_splice0_status 0x3ce0 /* width RMuint32 */
#define demux_splice1_status 0x3ce1 /* width RMuint32 */
#define demux_splice2_status 0x3ce2 /* width RMuint32 */
#define demux_pid_bank_control 0x3ce8 /* width RMuint32 */
#define demux_pid_bank 0x3d00 /* width RMuint32 */
#define TDMX_gpio_data 0x2e0c /* width RMuint32 */
#define TDMX_gpio_dir 0x2e0d /* width RMuint32 */
#define demux_spi_write_ptr0 0x1e08 /* width RMuint32 */
#define demux_spi_write_ptr1 0x1e09 /* width RMuint32 */
#define demux_spi_write_ptr2 0x1e0a /* width RMuint32 */
#define demux_spi_write_ptr3 0x1e0b /* width RMuint32 */
#define demux_spi_routing 0x1e0c /* width RMuint32 */
#define demux_spi_clk_phase 0x1e0d /* width RMuint32 */
#define demux_spi_sync_bytes 0x1e0e /* width RMuint32 */
#define demux_idma_write_ptr 0x1e18 /* width RMuint32 */
#define demux_idma_cnt 0x1e19 /* width RMuint32 */
#define demux_odma_read_ptr 0x1e20 /* width RMuint32 */
#define demux_odma_cnt 0x1e21 /* width RMuint32 */
#define demux_odma_sc_stat 0x1e22 /* width RMuint32 */
#define demux_odma_sc_match 0x1e23 /* width RMuint32 */
#define demux_sbox_mode 0x1e28 /* width RMuint32 */
#define demux_MISC_UNRESET_MASK 0xd800 /* width RMuint32 */
#define demux_MISC_RESET_MASK 0xd8d8 /* width RMuint32 */
#define demux_SP_init 0x7fe /* width RMuint32 */
/* DemuxEngine registers done */

/* MpegEngine registers */
#define REG_BASE_mpeg_engine_0 0x00080000 /* width RMuint32 */
#define MEM_BASE_mpeg_engine_0 0x00100000 /* width RMuint32 */
#define PMEM_BASE_mpeg_engine_0 0x00100000 /* width RMuint32 */
#define DMEM_BASE_mpeg_engine_0 0x00110000 /* width RMuint32 */
#define REG_BASE_mpeg_engine_1 0x00090000 /* width RMuint32 */
#define MEM_BASE_mpeg_engine_1 0x00120000 /* width RMuint32 */
#define PMEM_BASE_mpeg_engine_1 0x00120000 /* width RMuint32 */
#define DMEM_BASE_mpeg_engine_1 0x00130000 /* width RMuint32 */
#define mpeg_mutex0 0x0fe0 /* width RMuint32 */
#define mpeg_mutex1 0x0fe1 /* width RMuint32 */
#define mpeg_mutex2 0x0fe2 /* width RMuint32 */
#define mpeg_mutex3 0x0fe3 /* width RMuint32 */
#define mpeg_mutex4 0x0fe4 /* width RMuint32 */
#define mpeg_mutex5 0x0fe5 /* width RMuint32 */
#define mpeg_mutex6 0x0fe6 /* width RMuint32 */
#define mpeg_mutex7 0x0fe7 /* width RMuint32 */
#define RBUS_offset 0x4000 /* width RMuint32 */
#define mpeg_MBUSIF_w0_addlo 0xE80 /* width RMuint32 */
#define mpeg_MBUSIF_w0_addhi 0xE81 /* width RMuint32 */
#define mpeg_MBUSIF_w0_xcnt 0xE82 /* width RMuint32 */
#define mpeg_MBUSIF_w0_ycnt 0xE83 /* width RMuint32 */
#define mpeg_MBUSIF_w0_skiplo 0xE84 /* width RMuint32 */
#define mpeg_MBUSIF_w0_skiphi 0xE85 /* width RMuint32 */
#define mpeg_MBUSIF_w0_cmd 0xE86 /* width RMuint32 */
#define mpeg_MBUSIF_w0_vbuf_width 0xE87 /* width RMuint32 */
#define mpeg_MBUSIF_r0_addlo 0xE90 /* width RMuint32 */
#define mpeg_MBUSIF_r0_addhi 0xE91 /* width RMuint32 */
#define mpeg_MBUSIF_r0_xcnt 0xE92 /* width RMuint32 */
#define mpeg_MBUSIF_r0_ycnt 0xE93 /* width RMuint32 */
#define mpeg_MBUSIF_r0_skiplo 0xE94 /* width RMuint32 */
#define mpeg_MBUSIF_r0_skiphi 0xE95 /* width RMuint32 */
#define mpeg_MBUSIF_r0_cmd 0xE96 /* width RMuint32 */
#define mpeg_MBUSIF_r0_vbuf_width 0xE97 /* width RMuint32 */
#define mpeg_MBUSIF_r1_addlo 0xEA0 /* width RMuint32 */
#define mpeg_MBUSIF_r1_addhi 0xEA1 /* width RMuint32 */
#define mpeg_MBUSIF_r1_xcnt 0xEA2 /* width RMuint32 */
#define mpeg_MBUSIF_r1_ycnt 0xEA3 /* width RMuint32 */
#define mpeg_MBUSIF_r1_skiplo 0xEA4 /* width RMuint32 */
#define mpeg_MBUSIF_r1_skiphi 0xEA5 /* width RMuint32 */
#define mpeg_MBUSIF_r1_cmd 0xEA6 /* width RMuint32 */
#define mpeg_MBUSIF_r1_vbuf_width 0xEA7 /* width RMuint32 */
#define mpeg_MBUSIF_w1_addlo 0xEB0 /* width RMuint32 */
#define mpeg_MBUSIF_w1_addhi 0xEB1 /* width RMuint32 */
#define mpeg_MBUSIF_w1_xcnt 0xEB2 /* width RMuint32 */
#define mpeg_MBUSIF_w1_ycnt 0xEB3 /* width RMuint32 */
#define mpeg_MBUSIF_w1_skiplo 0xEB4 /* width RMuint32 */
#define mpeg_MBUSIF_w1_skiphi 0xEB5 /* width RMuint32 */
#define mpeg_MBUSIF_w1_cmd 0xEB6 /* width RMuint32 */
#define mpeg_MBUSIF_w1_vbuf_width 0xEB7 /* width RMuint32 */
#define mpeg_MBUSIF_r2_addlo 0xEC0 /* width RMuint32 */
#define mpeg_MBUSIF_r2_addhi 0xEC1 /* width RMuint32 */
#define mpeg_MBUSIF_r2_xcnt 0xEC2 /* width RMuint32 */
#define mpeg_MBUSIF_r2_ycnt 0xEC3 /* width RMuint32 */
#define mpeg_MBUSIF_r2_skiplo 0xEC4 /* width RMuint32 */
#define mpeg_MBUSIF_r2_skiphi 0xEC5 /* width RMuint32 */
#define mpeg_MBUSIF_r2_cmd 0xEC6 /* width RMuint32 */
#define mpeg_MBUSIF_r2_vbuf_width 0xEC7 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_WADD_LOW 0xFA0 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_WADD_HIGH 0xFA1 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_RADD_LOW 0xFA2 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_RADD_HIGH 0xFA3 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_BYTE 0xFA4 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_WORD 0xFA5 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_DWORD_LOW 0xFA6 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_DWORD_HIGH 0xFA7 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_STATUS 0xFA8 /* width RMuint32 */
#define mpeg_GBUSIF_ISR_WADD_LOW 0xFB0 /* width RMuint32 */
#define mpeg_GBUSIF_ISR_WADD_HIGH 0xFB1 /* width RMuint32 */
#define mpeg_GBUSIF_ISR_RADD_LOW 0xFB2 /* width RMuint32 */
#define mpeg_GBUSIF_ISR_RADD_HIGH 0xFB3 /* width RMuint32 */
#define mpeg_GBUSIF_ISR_BYTE 0xFB4 /* width RMuint32 */
#define mpeg_GBUSIF_ISR_WORD 0xFB5 /* width RMuint32 */
#define mpeg_GBUSIF_ISR_DWORD_LOW 0xFB6 /* width RMuint32 */
#define mpeg_GBUSIF_ISR_DWORD_HIGH 0xFB7 /* width RMuint32 */
#define mpeg_GBUSIF_ISR_STATUS 0xFB8 /* width RMuint32 */
#define mpeg_MISC_dr_mode 0xFF0 /* width RMuint32 */
#define mpeg_MISC_dr_length 0xFF1 /* width RMuint32 */
#define mpeg_MISC_dr_address 0xFF2 /* width RMuint32 */
#define mpeg_MISC_sbox_mode 0xFF3 /* width RMuint32 */
#define mpeg_MISC_dw_mode 0xFF4 /* width RMuint32 */
#define mpeg_MISC_dw_length 0xFF5 /* width RMuint32 */
#define mpeg_MISC_dw_address 0xFF6 /* width RMuint32 */
#define mpeg_MISC_codec_type 0xFF7 /* width RMuint32 */
#define mpeg_MISC_reset0 0xFF8 /* width RMuint32 */
#define mpeg_MISC_reset1 0xFF9 /* width RMuint32 */
#define mpeg_MISC_interrupt 0xFFA /* width RMuint32 */
#define mpeg_MISC_timer_div 0xFFB /* width RMuint32 */
#define mpeg_MISC_timer_count 0xFFC /* width RMuint32 */
#define mpeg_MISC_sbox_read_ctrl 0xFFD /* width RMuint32 */
#define mpeg_MISC_sbox_write_ctrl 0xFFE /* width RMuint32 */
#define mpeg_MISC_reserved2 0xFFF /* width RMuint32 */
#define mpeg_MISC_UNRESET_MASK 0x3500 /* width RMuint32 */
#define mpeg_MISC_RESET_MASK 0x3535 /* width RMuint32 */
#define mpeg_SP_init 0x7fe /* width RMuint32 */
/* MpegEngine registers done */

/* VideoDecoder registers */
/* VideoDecoder registers done */

/* AudioEngine registers */
#define REG_BASE_audio_engine_0 0x000c0000 /* width RMuint32 */
#define MEM_BASE_audio_engine_0 0x00180000 /* width RMuint32 */
#define PMEM_BASE_audio_engine_0 0x00180000 /* width RMuint32 */
#define DMEM_BASE_audio_engine_0 0x00190000 /* width RMuint32 */
#define REG_BASE_audio_engine_1 0x000d0000 /* width RMuint32 */
#define MEM_BASE_audio_engine_1 0x001a0000 /* width RMuint32 */
#define PMEM_BASE_audio_engine_1 0x001a0000 /* width RMuint32 */
#define DMEM_BASE_audio_engine_1 0x001b0000 /* width RMuint32 */
#define audio_SO_L0_DATA 0x3e00 /* width RMuint32 */
#define audio_SO_R0_DATA 0x3e01 /* width RMuint32 */
#define audio_SO_L1_DATA 0x3e02 /* width RMuint32 */
#define audio_SO_R1_DATA 0x3e03 /* width RMuint32 */
#define audio_SO_L2_DATA 0x3e04 /* width RMuint32 */
#define audio_SO_R2_DATA 0x3e05 /* width RMuint32 */
#define audio_SO_LS_DATA 0x3e06 /* width RMuint32 */
#define audio_SO_RS_DATA 0x3e07 /* width RMuint32 */
#define audio_SO_CH_INTR 0x3e08 /* width RMuint32 */
#define audio_SO_CH_CTRL 0x3e09 /* width RMuint32 */
#define audio_SO_SPDIF_CH_STAT 0x3e0a /* width RMuint32 */
#define audio_SO_L3_DATA 0x3e0b /* width RMuint32 */
#define audio_SO_R3_DATA 0x3e0c /* width RMuint32 */
#define audio_SO_L4_DATA 0x3e0d /* width RMuint32 */
#define audio_SO_AUDIO_CLK_DIV 0x3e0e /* width RMuint32 */
#define audio_SO_R4_DATA 0x3e0f /* width RMuint32 */
#define audio_mutex0 0x3e90 /* width RMuint32 */
#define audio_mutex1 0x3e91 /* width RMuint32 */
#define audio_mutex2 0x3e92 /* width RMuint32 */
#define audio_mutex3 0x3e93 /* width RMuint32 */
#define audio_mutex4 0x3e94 /* width RMuint32 */
#define audio_mutex5 0x3e95 /* width RMuint32 */
#define audio_mutex6 0x3e96 /* width RMuint32 */
#define audio_mutex7 0x3e97 /* width RMuint32 */
#define audio_MBUSIF_w0_add 0x3ec0 /* width RMuint32 */
#define audio_MBUSIF_w0_cnt 0x3ec1 /* width RMuint32 */
#define audio_MBUSIF_w0_skip 0x3ec2 /* width RMuint32 */
#define audio_MBUSIF_w0_cmd 0x3ec3 /* width RMuint32 */
#define audio_MBUSIF_r0_add 0x3ed0 /* width RMuint32 */
#define audio_MBUSIF_r0_cnt 0x3ed1 /* width RMuint32 */
#define audio_MBUSIF_r0_skip 0x3ed2 /* width RMuint32 */
#define audio_MBUSIF_r0_cmd 0x3ed3 /* width RMuint32 */
#define audio_GBUSIF_MAIN_WADD 0x3ea0 /* width RMuint32 */
#define audio_GBUSIF_MAIN_RADD 0x3ea1 /* width RMuint32 */
#define audio_GBUSIF_MAIN_BYTE 0x3ea2 /* width RMuint32 */
#define audio_GBUSIF_MAIN_WORD 0x3ea3 /* width RMuint32 */
#define audio_GBUSIF_MAIN_DWORD 0x3ea4 /* width RMuint32 */
#define audio_GBUSIF_MAIN_STATUS 0x3ea5 /* width RMuint32 */
#define audio_GBUSIF_ISR_WADD 0x3ea8 /* width RMuint32 */
#define audio_GBUSIF_ISR_RADD 0x3ea9 /* width RMuint32 */
#define audio_GBUSIF_ISR_BYTE 0x3eaa /* width RMuint32 */
#define audio_GBUSIF_ISR_WORD 0x3eab /* width RMuint32 */
#define audio_GBUSIF_ISR_DWORD 0x3eac /* width RMuint32 */
#define audio_GBUSIF_ISR_STATUS 0x3ead /* width RMuint32 */
#define audio_MISC_dr_mode 0x3e80 /* width RMuint32 */
#define audio_MISC_dr_length 0x3e81 /* width RMuint32 */
#define audio_MISC_dr_address 0x3e82 /* width RMuint32 */
#define audio_MISC_dw_mode 0x3e84 /* width RMuint32 */
#define audio_MISC_dw_length 0x3e85 /* width RMuint32 */
#define audio_MISC_dw_address 0x3e86