emhwlib_registers_tango3.h

1. 8623L平台

#define VO_vid_in_vt_sync 0x0b14 /* width RMuint32 */
#define VO_vid_in_sync_coord 0x0b18 /* width RMuint32 */
#define VO_vid_in_top_vbi 0x0b1c /* width RMuint32 */
#define VO_vid_in_bot_vbi 0x0b20 /* width RMuint32 */
#define VO_vid_in_counters 0x0b24 /* width RMuint32 */
#define VO_vid_in_vbi_size 0x0b28 /* width RMuint32 */
#define VO_vid_in_vbi_vsm 0x0b2c /* width RMuint32 */
#define VO_vid_in_vbi_Voffset 0x0b30 /* width RMuint32 */
#define VO_vid_in_format2 0x0b34 /* width RMuint32 */
#define VO_vid_in_counters2 0x0b38 /* width RMuint32 */
/* DispVideoInput registers done */

/* DispGraphicInput registers */
#define VO_graph_in_reset_bit 0x11 /* width RMuint32 */
#define VO_graph_in_format 0x0c00 /* width RMuint32 */
#define VO_graph_in_alpha_routing 0x0c04 /* width RMuint32 */
#define VO_graph_in_key_color 0x0c08 /* width RMuint32 */
#define VO_graph_in_data_size 0x0c0c /* width RMuint32 */
#define VO_graph_in_data_Xoffset 0x0c10 /* width RMuint32 */
#define VO_graph_in_data_Yoffset 0x0c14 /* width RMuint32 */
#define VO_graph_in_hz_sync 0x0c18 /* width RMuint32 */
#define VO_graph_in_vt_sync 0x0c1c /* width RMuint32 */
#define VO_graph_in_sync_coord 0x0c20 /* width RMuint32 */
#define VO_graph_in_sync_offset 0x0c24 /* width RMuint32 */
#define VO_graph_in_top_vbi 0x0c28 /* width RMuint32 */
#define VO_graph_in_bot_vbi 0x0c2c /* width RMuint32 */
#define VO_graph_in_counters 0x0c30 /* width RMuint32 */
#define VO_graph_in_format2 0x0c34 /* width RMuint32 */
#define VO_graph_in_counters2 0x0c38 /* width RMuint32 */
#define VO_graph_in_vbi_size 0x0c3c /* width RMuint32 */
#define VO_graph_in_vbi_vsm 0x0c40 /* width RMuint32 */
#define VO_graph_in_vbi_Voffset 0x0c44 /* width RMuint32 */
/* DispGraphicInput registers done */

/* DispDigitalOut registers */
#define VO_digit_out_reset_bit 0x12 /* width RMuint32 */
#define VO_digit_out_conv0 0x0e00 /* width RMuint32 */
#define VO_digit_out_conv1 0x0e04 /* width RMuint32 */
#define VO_digit_out_conv2 0x0e08 /* width RMuint32 */
#define VO_digit_out_conv3 0x0e0c /* width RMuint32 */
#define VO_digit_out_conv4 0x0e10 /* width RMuint32 */
#define VO_digit_out_conv5 0x0e14 /* width RMuint32 */
#define VO_digit_out_format 0x0e20 /* width RMuint32 */
#define VO_digit_out_Xoffset 0x0e24 /* width RMuint32 */
#define VO_digit_out_Yoffset 0x0e28 /* width RMuint32 */
#define VO_digit_out_hz_sync 0x0e2c /* width RMuint32 */
#define VO_digit_out_vt_sync 0x0e30 /* width RMuint32 */
#define VO_digit_out_vsync_coord 0x0e34 /* width RMuint32 */
#define VO_digit_out_sync_ext_sync 0x0e38 /* width RMuint32 */
#define VO_digit_out_color_depth 0x0e3c /* width RMuint32 */
#define VO_digit_out_pads_config 0x0020 /* width RMuint32 */
#define VO_digit_out_gamma_lut0 0xf000 /* width RMuint32 */
#define VO_digit_out_temp_lut0 0xf400 /* width RMuint32 */
#define VO_digit_out_sync_ext_sync 0x0e38 /* width RMuint32 */
/* DispDigitalOut registers done */

/* DispMainAnalogOut registers */
#define VO_main_analog_reset_bit 0x13 /* width RMuint32 */
#define VO_main_analog_conv0 0x0f00 /* width RMuint32 */
#define VO_main_analog_conv1 0x0f04 /* width RMuint32 */
#define VO_main_analog_conv2 0x0f08 /* width RMuint32 */
#define VO_main_analog_conv3 0x0f0c /* width RMuint32 */
#define VO_main_analog_conv4 0x0f10 /* width RMuint32 */
#define VO_main_analog_conv5 0x0f14 /* width RMuint32 */
#define VO_main_analog_xoffset_field 0x0f18 /* width RMuint32 */
#define VO_main_analog_yoffset 0x0f1c /* width RMuint32 */
#define VO_main_analog_cvbs_conv0 0x0f20 /* width RMuint32 */
#define VO_main_analog_cvbs_conv1 0x0f24 /* width RMuint32 */
#define VO_main_analog_cvbs_conv2 0x0f28 /* width RMuint32 */
#define VO_main_analog_cvbs_conv3 0x0f2c /* width RMuint32 */
#define VO_main_analog_cvbs_conv4 0x0f30 /* width RMuint32 */
#define VO_main_analog_cvbs_conv5 0x0f34 /* width RMuint32 */
#define VO_main_analog_TV_config 0x0f40 /* width RMuint32 */
#define VO_main_analog_TV_size 0x0f44 /* width RMuint32 */
#define VO_main_analog_TV_hsync 0x0f48 /* width RMuint32 */
#define VO_main_analog_TV_vsync_O_0 0x0f4c /* width RMuint32 */
#define VO_main_analog_TV_vsync_O_1 0x0f50 /* width RMuint32 */
#define VO_main_analog_TV_vsync_E_0 0x0f54 /* width RMuint32 */
#define VO_main_analog_TV_vsync_E_1 0x0f58 /* width RMuint32 */
#define VO_main_analog_TV_HD_hsync_info 0x0f5c /* width RMuint32 */
#define VO_main_analog_TV_HD_vsync 0x0f60 /* width RMuint32 */
#define VO_main_analog_TV_CGMS 0x0f64 /* width RMuint32 */
#define VO_main_analog_TV_CC_AGC 0x0f68 /* width RMuint32 */
#define VO_main_analog_TV_test_config 0x0f6c /* width RMuint32 */
#define VO_main_analog_TV_teletext_config 0x0f70 /* width RMuint32 */
#define VO_main_analog_TV_config2 0x0f74 /* width RMuint32 */
#define VO_main_analog_TV_cav_minmax 0x0f78 /* width RMuint32 */
#define VO_main_analog_TV_timing_sync 0x0f7c /* width RMuint32 */
#define VO_main_analog_TV_MV_N_0_22 0x0f80 /* width RMuint32 */
#define VO_main_analog_TV_MV_N_1_2_3_4 0x0f84 /* width RMuint32 */
#define VO_main_analog_TV_MV_N_5_6_7_8 0x0f88 /* width RMuint32 */
#define VO_main_analog_TV_MV_N_9_10_11 0x0f8c /* width RMuint32 */
#define VO_main_analog_TV_MV_N_12_13_14 0x0f90 /* width RMuint32 */
#define VO_main_analog_TV_MV_N_15_16_17_18 0x0f94 /* width RMuint32 */
#define VO_main_analog_TV_MV_N_19_20_21 0x0f98 /* width RMuint32 */
#define VO_main_analog_vbi_EIA805B_ctrl 0x0fc0 /* width RMuint32 */
#define VO_main_analog_vbi_EIA805B_data0 0x0fc0 /* width RMuint32 */
#define VO_main_analog_vbi_EIA805B_data1 0x0fc4 /* width RMuint32 */
#define VO_main_analog_vbi_EIA805B_data2 0x0fc8 /* width RMuint32 */
#define VO_main_analog_vbi_EIA805B_data3 0x0fd0 /* width RMuint32 */
#define VO_main_analog_tlxt0 0xe000 /* width RMuint32 */
#define VO_main_analog_TV_timing_sync 0x0f7c /* width RMuint32 */
/* DispMainAnalogOut registers done */

/* DispComponentOut registers */
#define VO_component_out_reset_bit 0x14 /* width RMuint32 */
#define VO_component_out_conv0 0x1000 /* width RMuint32 */
#define VO_component_out_conv1 0x1004 /* width RMuint32 */
#define VO_component_out_conv2 0x1008 /* width RMuint32 */
#define VO_component_out_conv3 0x100c /* width RMuint32 */
#define VO_component_out_conv4 0x1010 /* width RMuint32 */
#define VO_component_out_conv5 0x1014 /* width RMuint32 */
#define VO_component_out_xoffset_field 0x1018 /* width RMuint32 */
#define VO_component_out_yoffset 0x101c /* width RMuint32 */
#define VO_component_out_TV_config 0x1040 /* width RMuint32 */
#define VO_component_out_TV_size 0x1044 /* width RMuint32 */
#define VO_component_out_TV_hsync 0x1048 /* width RMuint32 */
#define VO_component_out_TV_vsync_O_0 0x104c /* width RMuint32 */
#define VO_component_out_TV_vsync_O_1 0x1050 /* width RMuint32 */
#define VO_component_out_TV_vsync_E_0 0x1054 /* width RMuint32 */
#define VO_component_out_TV_vsync_E_1 0x1058 /* width RMuint32 */
#define VO_component_out_TV_HD_hsync_info 0x105c /* width RMuint32 */
#define VO_component_out_TV_HD_vsync 0x1060 /* width RMuint32 */
#define VO_component_out_TV_CGMS 0x1064 /* width RMuint32 */
#define VO_component_out_TV_CC_AGC 0x1068 /* width RMuint32 */
#define VO_component_out_TV_test_config 0x106c /* width RMuint32 */
#define VO_component_out_TV_config2 0x1070 /* width RMuint32 */
#define VO_component_out_TV_cav_minmax 0x1074 /* width RMuint32 */
#define VO_component_out_TV_timing_sync 0x1078 /* width RMuint32 */
#define VO_component_out_TV_MV_N_0_22 0x1080 /* width RMuint32 */
#define VO_component_out_TV_MV_N_1_2_3_4 0x1084 /* width RMuint32 */
#define VO_component_out_TV_MV_N_5_6_7_8 0x1088 /* width RMuint32 */
#define VO_component_out_TV_MV_N_9_10_11 0x108c /* width RMuint32 */
#define VO_component_out_TV_MV_N_12_13_14 0x1090 /* width RMuint32 */
#define VO_component_out_TV_MV_N_15_16_17_18 0x1094 /* width RMuint32 */
#define VO_component_out_TV_MV_N_19_20_21 0x1098 /* width RMuint32 */
#define VO_component_out_vbi_EIA805B_ctrl 0x10c0 /* width RMuint32 */
#define VO_component_out_vbi_EIA805B_data0 0x10c0 /* width RMuint32 */
#define VO_component_out_vbi_EIA805B_data1 0x10c4 /* width RMuint32 */
#define VO_component_out_vbi_EIA805B_data2 0x10c8 /* width RMuint32 */
#define VO_component_out_vbi_EIA805B_data3 0x10d0 /* width RMuint32 */
#define VO_component_out_TV_timing_sync 0x1078 /* width RMuint32 */
/* DispComponentOut registers done */

/* DispCompositeOut registers */
#define VO_composite_out_reset_bit 0x15 /* width RMuint32 */
#define VO_composite_out_bcs 0x1100 /* width RMuint32 */
#define VO_composite_out_Xoffset 0x1104 /* width RMuint32 */
#define VO_composite_out_Yoffset 0x1108 /* width RMuint32 */
#define VO_composite_out_TV_config 0x1140 /* width RMuint32 */
#define VO_composite_out_TV_size 0x1144 /* width RMuint32 */
#define VO_composite_out_TV_hsync 0x1148 /* width RMuint32 */
#define VO_composite_out_TV_vsync_O_0 0x114c /* width RMuint32 */
#define VO_composite_out_TV_vsync_O_1 0x1150 /* width RMuint32 */
#define VO_composite_out_TV_vsync_E_0 0x1154 /* width RMuint32 */
#define VO_composite_out_TV_vsync_E_1 0x1158 /* width RMuint32 */
#define VO_composite_out_TV_CGMS 0x1164 /* width RMuint32 */
#define VO_composite_out_TV_CC_AGC 0x1168 /* width RMuint32 */
#define VO_composite_out_TV_test_config 0x116c /* width RMuint32 */
#define VO_composite_out_TV_MV_N_0_22 0x1180 /* width RMuint32 */
#define VO_composite_out_TV_MV_N_1_2_3_4 0x1184 /* width RMuint32 */
#define VO_composite_out_TV_MV_N_5_6_7_8 0x1188 /* width RMuint32 */
#define VO_composite_out_TV_MV_N_9_10_11 0x118c /* width RMuint32 */
#define VO_composite_out_TV_MV_N_12_13_14 0x1190 /* width RMuint32 */
#define VO_composite_out_TV_MV_N_15_16_17_18 0x1194 /* width RMuint32 */
#define VO_composite_out_TV_MV_N_19_20_21 0x1198 /* width RMuint32 */
/* DispCompositeOut registers done */

/* DemuxEngine registers */
#define REG_BASE_demux_engine 0x000A0000 /* width RMuint32 */
#define MEM_BASE_demux_engine 0x00140000 /* width RMuint32 */
#define PMEM_BASE_demux_engine 0x00140000 /* width RMuint32 */
#define DMEM_BASE_demux_engine 0x00150000 /* width RMuint32 */
#define REG_BASE_demux_engine_0 0x000A0000 /* width RMuint32 */
#define MEM_BASE_demux_engine_0 0x00140000 /* width RMuint32 */
#define PMEM_BASE_demux_engine_0 0x00140000 /* width RMuint32 */
#define DMEM_BASE_demux_engine_0 0x00150000 /* width RMuint32 */
#define REG_BASE_demux_engine_1 0x000b0000 /* width RMuint32 */
#define MEM_BASE_demux_engine_1 0x00160000 /* width RMuint32 */
#define PMEM_BASE_demux_engine_1 0x00160000 /* width RMuint32 */
#define DMEM_BASE_demux_engine_1 0x00170000 /* width RMuint32 */
#define demux_MISC_dr_mode 0x2f00 /* width RMuint32 */
#define demux_MISC_dr_length 0x2f01 /* width RMuint32 */
#define demux_MISC_dr_address 0x2f02 /* width RMuint32 */
#define demux_MISC_dw_mode 0x2f04 /* width RMuint32 */
#define demux_MISC_dw_length 0x2f05 /* width RMuint32 */
#define demux_MISC_dw_address 0x2f06 /* width RMuint32 */
#define demux_MISC_reset0 0x2f08 /* width RMuint32 */
#define demux_MISC_reset1 0x2f09 /* width RMuint32 */
#define demux_MISC_interrupt 0x2f0a /* width RMuint32 */
#define demux_MISC_timer_div 0x2f0b /* width RMuint32 */
#define demux_MISC_timer_count 0x2f0c /* width RMuint32 */
#define demux_mutex0 0x2f10 /* width RMuint32 */
#define demux_mutex1 0x2f11 /* width RMuint32 */
#define demux_mutex2 0x2f12 /* width RMuint32 */
#define demux_mutex3 0x2f13 /* width RMuint32 */
#define demux_mutex4 0x2f14 /* width RMuint32 */
#define demux_mutex5 0x2f15 /* width RMuint32 */
#define demux_mutex6 0x2f16 /* width RMuint32 */
#define demux_mutex7 0x2f17 /* width RMuint32 */
#define demux_GBUSIF_MAIN_WADD 0x2ea0 /* width RMuint32 */
#define demux_GBUSIF_MAIN_RADD 0x2ea1 /* width RMuint32 */
#define demux_GBUSIF_MAIN_BYTE 0x2ea2 /* width RMuint32 */
#define demux_GBUSIF_MAIN_WORD 0x2ea3 /* width RMuint32 */
#define demux_GBUSIF_MAIN_DWORD 0x2ea4 /* width RMuint32 */
#define demux_GBUSIF_MAIN_STATUS 0x2ea5 /* width RMuint32 */
#define demux_GBUSIF_ISR_WADD 0x2ea8 /* width RMuint32 */
#define demux_GBUSIF_ISR_RADD 0x2ea9 /* width RMuint32 */
#define demux_GBUSIF_ISR_BYTE 0x2eaa /* width RMuint32 */
#define demux_GBUSIF_ISR_WORD 0x2eab /* width RMuint32 */
#define demux_GBUSIF_ISR_DWORD 0x2eac /* width RMuint32 */
#define demux_GBUSIF_ISR_STATUS 0x2ead /* width RMuint32 */
#define demux_MBUSIF_w0_add 0x2ec0 /* width RMuint32 */
#define demux_MBUSIF_w0_cnt 0x2ec1 /* width RMuint32 */
#define demux_MBUSIF_w0_skip 0x2ec2 /* width RMuint32 */
#define demux_MBUSIF_w0_cmd 0x2ec3 /* width RMuint32 */
#define demux_MBUSIF_r0_add 0x2ed0 /* width RMuint32 */
#define demux_MBUSIF_r0_cnt 0x2ed1 /* width RMuint32 */
#define demux_MBUSIF_r0_skip 0x2ed2 /* width RMuint32 */
#define demux_MBUSIF_r0_cmd 0x2ed3 /* width RMuint32 */
#define demux_cipher_c2_secret_key 0x2c00 /* width RMuint32 */
#define demux_cipher_c2_key_lsb 0x2c70 /* width RMuint32 */
#define demux_cipher_c2_key_msb 0x2c71 /* width RMuint32 */
#define demux_cipher_c2g_ecb_data_lsb 0x2c72 /* width RMuint32 */
#define demux_cipher_c2g_ecb_data_msb 0x2c73 /* width RMuint32 */
#define demux_cipher_c2_flags 0x2c74 /* width RMuint32 */
#define demux_cipher_multi2_syst_key 0x2c80 /* width RMuint32 */
#define demux_cipher_multi2_data_key 0x2c88 /* width RMuint32 */
#define demux_cipher_multi2_iv       0x2c8a /* width RMuint32 */
#define demux_cipher_multi2_flags 0x2c8c /* width RMuint32 */
#define demux_cipher_config 0x2c8f /* width RMuint32 */
#define demux_cipher_rc4_key_0 0x2e40 /* width RMuint32 */
#define demux_cipher_rc4_key_1 0x2e41 /* width RMuint32 */
#define demux_cipher_rc4_key_2 0x2e42 /* width RMuint32 */
#define demux_cipher_rc4_key_3 0x2e43 /* width RMuint32 */
#define demux_cipher_rc4_key_4 0x2e44 /* width RMuint32 */
#define demux_cipher_rc4_key_5 0x2e45 /* width RMuint32 */
#define demux_cipher_rc4_key_6 0x2e46 /* width RMuint32 */
#define demux_cipher_rc4_key_7 0x2e47 /* width RMuint32 */
#define demux_cipher_rc4_flags 0x2e48 /* width RMuint32 */
#define demux_cipher_des_key1_1 0x2e50 /* width RMuint32 */
#define demux_cipher_des_key1_2 0x2e51 /* width RMuint32 */
#define demux_cipher_des_key2_1 0x2e52 /* width RMuint32 */
#define demux_cipher_des_key2_2 0x2e53 /* width RMuint32 */
#define demux_cipher_des_key3_1 0x2e54 /* width RMuint32 */
#define demux_cipher_des_key3_2 0x2e55 /* width RMuint32 */
#define demux_cipher_des_IV_1 0x2e56 /* width RMuint32 */
#define demux_cipher_des_IV_2 0x2e57 /* width RMuint32 */
#define demux_cipher_des_flags 0x2e58 /* width RMuint32 */
#define demux_cipher_dvbcsa_key_lsb 0x2e5c /* width RMuint32 */