emhwlib_registers_tango15.h

1. 8623L平台

#define IDECTRL_pri_drv1tim 0x2120 /* width RMuint32 */
#define IDECTRL_idemisc 0x2130 /* width RMuint32 */
#define IDECTRL_idestatus 0x2140 /* width RMuint32 */
#define IDECTRL_udmactl 0x2150 /* width RMuint32 */
#define IDECTRL_pri_drv0udmatim1 0x2160 /* width RMuint32 */
#define IDECTRL_pri_drv0udmatim2 0x2170 /* width RMuint32 */
#define IDECTRL_pref_st 0x2310 /* width RMuint32 */
#define IDECTRL_pri_ctrlblock 0x2398 /* width RMuint32 */
#define IDECTRL_pri_cmdblock 0x23c0 /* width RMuint32 */
#define IDECTRL_bmic 0x2400 /* width RMuint32 */
#define IDECTRL_bmis 0x2410 /* width RMuint32 */
#define IDECTRL_bmidtp 0x2420 /* width RMuint32 */
#define IDECTRL_ide_dmaptr 0x2780 /* width RMuint32 */
#define IDECTRL_ide_dmalen 0x2790 /* width RMuint32 */
#define IDECTRL_pio_prefetch_data 0x27c0 /* width RMuint32 */
#define PCI_host_reg1 0xfed0 /* width RMuint32 */
#define PCI_host_reg2 0xfed4 /* width RMuint32 */
#define PCI_host_reg3 0xfe80 /* width RMuint32 */
#define PCI_host_reg4 0xfe84 /* width RMuint32 */
#define PCI_pcictrl_reg1 0xfe88 /* width RMuint32 */
#define PCI_pcictrl_reg2 0xfe8c /* width RMuint32 */
#define PCI_pcictrl_reg3 0xfefc /* width RMuint32 */
#define PCI_REG0 0xfee8 /* width RMuint32 */
#define PCI_REG1 0xfeec /* width RMuint32 */
#define PCI_REG2 0xfef0 /* width RMuint32 */
#define PCI_REG3 0xfef4 /* width RMuint32 */
#define PCI_CONFIG 0xfef8 /* width RMuint32 */
#define MIF_W0_ADD 0xb000 /* width RMuint32 */
#define MIF_W0_CNT 0xb004 /* width RMuint32 */
#define MIF_W0_SKIP 0xb008 /* width RMuint32 */
#define MIF_W0_CMD 0xb00c /* width RMuint32 */
#define MIF_W1_ADD 0xb040 /* width RMuint32 */
#define MIF_W1_CNT 0xb044 /* width RMuint32 */
#define MIF_W1_SKIP 0xb048 /* width RMuint32 */
#define MIF_W1_CMD 0xb04c /* width RMuint32 */
#define MIF_R0_ADD 0xb080 /* width RMuint32 */
#define MIF_R0_CNT 0xb084 /* width RMuint32 */
#define MIF_R0_SKIP 0xb088 /* width RMuint32 */
#define MIF_R0_CMD 0xb08c /* width RMuint32 */
#define MIF_R1_ADD 0xb0c0 /* width RMuint32 */
#define MIF_R1_CNT 0xb0c4 /* width RMuint32 */
#define MIF_R1_SKIP 0xb0c8 /* width RMuint32 */
#define MIF_R1_CMD 0xb0cc /* width RMuint32 */
#define MBUS_IDLE 0 /* width RMuint32 */
#define MBUS_LINEAR 1 /* width RMuint32 */
#define MBUS_DOUBLE 2 /* width RMuint32 */
#define MBUS_RECTANGLE 3 /* width RMuint32 */
#define MBUS_VOID 4 /* width RMuint32 */
#define MBUS_LINEAR_VOID 5 /* width RMuint32 */
#define MBUS_DOUBLE_VOID 6 /* width RMuint32 */
#define MBUS_RECTANGLE_VOID 7 /* width RMuint32 */
#define MBUS_TILED 8 /* width RMuint32 */
#define GBUS_MUTEX_XPU 0x14 /* width RMuint32 */
#define GBUS_MUTEX_PT110 0x16 /* width RMuint32 */
#define GBUS_MUTEX_TDMX 0x19 /* width RMuint32 */
#define GBUS_MUTEX_AUDIO_0 0x1b /* width RMuint32 */
#define GBUS_MUTEX_AUDIO_1 0x1c /* width RMuint32 */
#define GBUS_MUTEX_MPEG_0 0x1d /* width RMuint32 */
#define GBUS_MUTEX_MPEG_1 0x1e /* width RMuint32 */
#define GBUS_MUTEX_HOST 0x1f /* width RMuint32 */
#define GBUS_MUTEX_LOCAL 0x10 /* width RMuint32 */
/* SystemBlock registers done */

/* CPUBlock registers */
#define REG_BASE_cpu_block 0x00060000 /* width RMuint32 */
#define CPU_time0_load 0xc500 /* width RMuint32 */
#define CPU_time0_value 0xc504 /* width RMuint32 */
#define CPU_time0_ctrl 0xc508 /* width RMuint32 */
#define CPU_time0_clr 0xc50c /* width RMuint32 */
#define CPU_time1_load 0xc600 /* width RMuint32 */
#define CPU_time1_value 0xc604 /* width RMuint32 */
#define CPU_time1_ctrl 0xc608 /* width RMuint32 */
#define CPU_time1_clr 0xc60c /* width RMuint32 */
#define CPU_rtc_data 0xc800 /* width RMuint32 */
#define CPU_rtc_match 0xc804 /* width RMuint32 */
#define CPU_rtc_stat 0xc808 /* width RMuint32 */
#define CPU_rtc_load 0xc80c /* width RMuint32 */
#define CPU_rtc_ctrl 0xc810 /* width RMuint32 */
#define CPU_irq_status 0xe000 /* width RMuint32 */
#define CPU_irq_rawstat 0xe004 /* width RMuint32 */
#define CPU_irq_enableset 0xe008 /* width RMuint32 */
#define CPU_irq_enableclr 0xe00c /* width RMuint32 */
#define CPU_irq_softset 0xe010 /* width RMuint32 */
#define CPU_irq_softclr 0xe014 /* width RMuint32 */
#define CPU_fiq_status 0xe100 /* width RMuint32 */
#define CPU_fiq_rawstat 0xe104 /* width RMuint32 */
#define CPU_fiq_enableset 0xe108 /* width RMuint32 */
#define CPU_fiq_enableclr 0xe10c /* width RMuint32 */
#define CPU_fiq_softset 0xe110 /* width RMuint32 */
#define CPU_fiq_softclr 0xe114 /* width RMuint32 */
#define CPU_edge_status 0xe200 /* width RMuint32 */
#define CPU_edge_rawstat 0xe204 /* width RMuint32 */
#define CPU_edge_config_rise 0xe208 /* width RMuint32 */
#define CPU_edge_config_fall 0xe20c /* width RMuint32 */
#define CPU_SOFT_INT 0x00000001 /* width RMuint32 */
#define CPU_UART0_INT 0x00000002 /* width RMuint32 */
#define CPU_UART1_INT 0x00000004 /* width RMuint32 */
#define CPU_TIMER0_INT 0x00000020 /* width RMuint32 */
#define CPU_TIMER1_INT 0x00000040 /* width RMuint32 */
#define CPU_HOST_MBUS_W0_INT 0x00000200 /* width RMuint32 */
#define CPU_HOST_MBUS_W1_INT 0x00000400 /* width RMuint32 */
#define CPU_HOST_MBUS_R0_INT 0x00000800 /* width RMuint32 */
#define CPU_HOST_MBUS_R1_INT 0x00001000 /* width RMuint32 */
#define CPU_PCI_INTA 0x00002000 /* width RMuint32 */
#define CPU_PCI_INTB 0x00004000 /* width RMuint32 */
#define CPU_PCI_INTC 0x00008000 /* width RMuint32 */
#define CPU_PCI_INTD 0x00010000 /* width RMuint32 */
#define CPU_PCI_FAULT_INT 0x00100000 /* width RMuint32 */
#define CPU_INFRARED_INT 0x00200000 /* width RMuint32 */
#define PT110_CACHED_START 0x80000000 /* width RMuint32 */
#define CPU_reset_vec 0x0000 /* width RMuint32 */
#define CPU_undef_vec 0x0004 /* width RMuint32 */
#define CPU_swi_vec 0x0008 /* width RMuint32 */
#define CPU_instr_abort 0x000c /* width RMuint32 */
#define CPU_data_abort 0x0010 /* width RMuint32 */
#define CPU_irq_vec 0x0018 /* width RMuint32 */
#define CPU_fiq_vec 0x001c /* width RMuint32 */
#define CPU_RESET_jump 0x0020 /* width RMuint32 */
#define CPU_SMARTCARD_INT 0x00000008 /* width RMuint32 */
#define CPU_SFLA_INT 0x00000010 /* width RMuint32 */
#define CPU_DVD_INT 0x00000080 /* width RMuint32 */
#define CPU_ETH_INT 0x00000100 /* width RMuint32 */
#define CPU_DMAIDE_INT 0x00020000 /* width RMuint32 */
#define CPU_IDE_INT 0x00040000 /* width RMuint32 */
#define CPU_FRONTPANEL_INT 0x00080000 /* width RMuint32 */
#define CPU_I2C_INT 0x00400000 /* width RMuint32 */
#define CPU_GFX_ACCEL_INT 0x00800000 /* width RMuint32 */
#define CPU_VSYNC0_INT 0x01000000 /* width RMuint32 */
#define CPU_VSYNC1_INT 0x02000000 /* width RMuint32 */
#define CPU_VSYNC2_INT 0x04000000 /* width RMuint32 */
#define CPU_VSYNC3_INT 0x08000000 /* width RMuint32 */
#define CPU_VSYNC4_INT 0x10000000 /* width RMuint32 */
#define CPU_VSYNC4BKEND_INT 0x20000000 /* width RMuint32 */
#define CPU_VSYNC5_INT 0x40000000 /* width RMuint32 */
#define CPU_VSYNC5BKEND_INT 0x80000000 /* width RMuint32 */
#define CPU_GPIO0_HI_INT 0x00010000 /* width RMuint32 */
#define CPU_GPIO1_HI_INT 0x00020000 /* width RMuint32 */
#define CPU_GPIO2_HI_INT 0x00040000 /* width RMuint32 */
#define CPU_GPIO3_HI_INT 0x00080000 /* width RMuint32 */
#define CPU_GPIO4_HI_INT 0x00100000 /* width RMuint32 */
#define CPU_GPIO5_HI_INT 0x00200000 /* width RMuint32 */
#define CPU_GPIO6_HI_INT 0x00400000 /* width RMuint32 */
#define CPU_GPIO7_HI_INT 0x00800000 /* width RMuint32 */
#define CPU_GPIO8_HI_INT 0x01000000 /* width RMuint32 */
#define CPU_GPIO9_HI_INT 0x02000000 /* width RMuint32 */
#define CPU_GPIO10_HI_INT 0x04000000 /* width RMuint32 */
#define CPU_GPIO11_HI_INT 0x08000000 /* width RMuint32 */
#define CPU_GPIO12_HI_INT 0x10000000 /* width RMuint32 */
#define CPU_GPIO13_HI_INT 0x20000000 /* width RMuint32 */
#define CPU_GPIO14_HI_INT 0x40000000 /* width RMuint32 */
#define CPU_GPIO15_HI_INT 0x80000000 /* width RMuint32 */
#define CPU_UART_GPIOMODE 0x38 /* width RMuint32 */
#define CPU_UART_GPIODIR 0x30 /* width RMuint32 */
#define CPU_UART_GPIODATA 0x34 /* width RMuint32 */
#define CPU_edge_config_rise_set 0xe210 /* width RMuint32 */
#define CPU_edge_config_rise_clr 0xe214 /* width RMuint32 */
#define CPU_edge_config_fall_set 0xe218 /* width RMuint32 */
#define CPU_edge_config_fall_clr 0xe21c /* width RMuint32 */
#define CPU_edge_config_rise_set_hi 0xe230 /* width RMuint32 */
#define CPU_edge_config_rise_clr_hi 0xe234 /* width RMuint32 */
#define CPU_edge_config_fall_set_hi 0xe238 /* width RMuint32 */
#define CPU_edge_config_fall_clr_hi 0xe23c /* width RMuint32 */
#define REG_BASE_irq_handler_block 0x60000 /* width RMuint32 */
#define CPU_edge_status_hi 0xe220 /* width RMuint32 */
#define CPU_edge_rawstat_hi 0xe224 /* width RMuint32 */
#define CPU_edge_config_rise_hi 0xe228 /* width RMuint32 */
#define CPU_edge_config_fall_hi 0xe22c /* width RMuint32 */
#define CPU_irq_status_hi 0xe018 /* width RMuint32 */
#define CPU_irq_rawstat_hi 0xe01c /* width RMuint32 */
#define CPU_irq_enableset_hi 0xe020 /* width RMuint32 */
#define CPU_irq_enableclr_hi 0xe024 /* width RMuint32 */
#define CPU_fiq_status_hi 0xe118 /* width RMuint32 */
#define CPU_fiq_rawstat_hi 0xe11c /* width RMuint32 */
#define CPU_fiq_enableset_hi 0xe120 /* width RMuint32 */
#define CPU_fiq_enableclr_hi 0xe124 /* width RMuint32 */
#define CPU_remap 0xf000 /* width RMuint32 */
#define G2L_BIST_BUSY 0xffe0 /* width RMuint32 */
#define G2L_BIST_PASS 0xffe4 /* width RMuint32 */
#define G2L_BIST_MASK 0xffe8 /* width RMuint32 */
#define G2L_RESET_CONTROL 0xfffc /* width RMuint32 */
#define CPU_UART0_base 0xc100 /* width RMuint32 */
#define CPU_UART1_base 0xc200 /* width RMuint32 */
#define CPU_UART_RBR 0x00 /* width RMuint32 */
#define CPU_UART_THR 0x04 /* width RMuint32 */
#define CPU_UART_IER 0x08 /* width RMuint32 */
#define CPU_UART_IIR 0x0c /* width RMuint32 */
#define CPU_UART_FCR 0x10 /* width RMuint32 */
#define CPU_UART_LCR 0x14 /* width RMuint32 */
#define CPU_UART_MCR 0x18 /* width RMuint32 */
#define CPU_UART_LSR 0x1c /* width RMuint32 */
#define CPU_UART_MSR 0x20 /* width RMuint32 */
#define CPU_UART_SCR 0x24 /* width RMuint32 */
#define CPU_UART_CLKDIV 0x28 /* width RMuint32 */
#define CPU_UART_CLKSEL 0x2c /* width RMuint32 */
/* CPUBlock registers done */

/* XPUBlock registers */
#define REG_BASE_xpu_block 0x000e0000 /* width RMuint32 */
/* XPUBlock registers done */

/* IPUBlock registers */
#define REG_BASE_ipu_block 0x000f0000 /* width RMuint32 */
/* IPUBlock registers done */

/* DisplayBlock registers */
#define REG_BASE_display_block 0x00070000 /* width RMuint32 */
#define PMEM_BASE_display_block 0x00300000 /* width RMuint32 */
#define VO_run 0x0000 /* width RMuint32 */
#define VO_reset_datapath 0x0004 /* width RMuint32 */
#define VO_reset_timing 0x0008 /* width RMuint32 */
#define VO_reset_config 0x000c /* width RMuint32 */
#define VO_reset_mode_0 0x0014 /* width RMuint32 */
#define VO_reset_mode_1 0x0018 /* width RMuint32 */
#define VIF_w0 0x4000 /* width RMuint32 */
#define VIF_w1 0x4100 /* width RMuint32 */
#define VIF_w2 0x4200 /* width RMuint32 */
#define VIF_w3 0x4F00 /* width RMuint32 */
#define VIF_r0 0x4300 /* width RMuint32 */
#define VIF_r1 0x4400 /* width RMuint32 */
#define VIF_r2 0x4500 /* width RMuint32 */
#define VIF_r3 0x4600 /* width RMuint32 */
#define VIF_r4 0x4700 /* width RMuint32 */
#define VIF_r5 0x4800 /* width RMuint32 */
#define VIF_r6 0x4900 /* width RMuint32 */
#define VIF_r7 0x4A00 /* width RMuint32 */
#define VIF_r8 0x4B00 /* width RMuint32 */
#define VIF_r9 0x4C00 /* width RMuint32 */
#define VIF_r10 0x4D00 /* width RMuint32 */
#define VIF_r11 0x4E00 /* width RMuint32 */
#define VIF_offs 0x0100 /* width RMuint32 */
#define VIF_add 0x0000 /* width RMuint32 */
#define VIF_cnt 0x0004 /* width RMuint32 */
#define VIF_skip 0x0008 /* width RMuint32 */
#define VIF_cmd 0x000c /* width RMuint32 */
#define VIF_addB 0x0010 /* width RMuint32 */
#define VIF_cntB 0x0014 /* width RMuint32 */
#define VIF_skipB 0x0018 /* width RMuint32 */
#define VBUS_IDLE 0x0 /* width RMuint32 */
#define VBUS_LINEAR 0x1 /* width RMuint32 */
#define VBUS_DOUBLE 0x2 /* width RMuint32 */
#define VBUS_RECTANGLE 0x3 /* width RMuint32 */
#define VBUS_DOUBLE_FIELD 0x4 /* width RMuint32 */
#define VBUS_DOUBLE_RECTANGLE 0x5 /* width RMuint32 */
#define VBUS_8BYTE_COLUMN 0x6 /* width RMuint32 */
#define VBUS_VOID 0x8 /* width RMuint32 */
#define VBUS_LINEAR_VOID 0x9 /* width RMuint32 */
#define VBUS_DOUBLE_VOID 0xa /* width RMuint32 */
#define VBUS_RECTANGLE_VOID 0xb /* width RMuint32 */
#define VBUS_DOUBLE_FIELD_VOID 0xc /* width RMuint32 */
#define VBUS_DOUBLE_RECTANGLE_VOID 0xd /* width RMuint32 */
#define VBUS_8BYTE_COLUMN_VOID 0xe /* width RMuint32 */
#define VO_hdmi_reset_bit 0x17 /* width RMuint32 */
#define VO_hdmi_config 0x3d00 /* width RMuint32 */
#define VO_hdmi_i2c 0x3dc0 /* width RMuint32 */
#define VO_hdmi_keymem 0x3e00 /* width RMuint32 */
/* DisplayBlock registers done */

/* DispOSDScaler registers */