play_capture_tw9919.c

1. 8623L平台

		{0x33, 0x08},		//for improving HV shaking on week signal
		//	{0x33, 0xc8},
		{0x36, 0x00},
		//	{0x39, 0x0b},
		{0x39, 0x02}, //A Tho
		{0x6b, 0x26},
		{0x6c, 0x36},
		//	{0x6d, 0x25},		//Changed for v-sync out scheme
		//	{0x6e, 0x40},		//Changed for v-sync out scheme
		{0x6d, 0x00},		//Changed for v-sync out scheme
		{0x6e, 0x20},		//Changed for v-sync out scheme
		//	{0x70, 0x0a},		// for RevE
		{0x70, 0x07}, //A Tho
		{0x73, 0xc0}, //A Tho
		{0x75, 0x04},		// for RevE
		{0x76, 0x95}, //A Tho
		{0x81, 0x08},
		{0x06, 0x80},	//Reset			
		
		//
	};

	capsam_i2c_init(pTW9919, pTW9919->BaseDevice,TW9919E_CCIR_PAL_DataSet);	
	
	return RM_OK;
}

static RMstatus ClearINT1(struct capsam_TW9919_instance *pTW9919)
{
	capsam_i2c_write_dev(pTW9919, pTW9919->BaseDevice, 0xB3, 0xff);		
	return RM_OK;
}

static RMstatus ClearINT2(struct capsam_TW9919_instance *pTW9919)
{
	capsam_i2c_write_dev(pTW9919, pTW9919->BaseDevice, 0xB4, 0xff);		
	return RM_OK;
}

static RMstatus ClearINT3(struct capsam_TW9919_instance *pTW9919)
{

	return RM_OK;
}

static RMstatus HandleINT1(struct capsam_TW9919_instance *pTW9919, 
			   struct capsam_update *pUpdate,
			   RMuint32 reg)
{
	RMstatus err = RM_OK;
	
	return err;
}

static RMstatus HandleINT2(struct capsam_TW9919_instance *pTW9919, 
			   struct capsam_update *pUpdate,
			   RMuint32 reg)
{
	RMstatus err = RM_OK;
	
	return err;
}

static RMstatus HandleINT3(struct capsam_TW9919_instance *pTW9919, 
			   struct capsam_update *pUpdate,
			   RMuint32 reg)
{
	RMstatus err = RM_OK;
	
	return err;
}

/*
********************************************************************************
* Capture Chip API
********************************************************************************
*/

RMstatus capsam_TW9919_open(struct RUA *pRUA, 
			 struct capsam_TW9919_instance **ppTW9919, 
			 RMuint32 I2CModuleID, 
			 struct EMhwlibI2CDeviceParameter *pI2CDevice,
			 RMuint32 XtalClock)
{
	struct capsam_TW9919_instance *pTW9919;
	
	RMDBGLOG((ENABLE, "%s\n",__func__));

	// Sanity checks
	if (ppTW9919 == NULL) return RM_FATALINVALIDPOINTER;
	*ppTW9919 = NULL;
	if (pRUA == NULL) return RM_FATALINVALIDPOINTER;
	if (pI2CDevice == NULL) return RM_FATALINVALIDPOINTER;
	
	// Allocate and clear local instance
	pTW9919 = (struct capsam_TW9919_instance *)RMMalloc(sizeof(struct capsam_TW9919_instance));
	if (pTW9919 == NULL) {
		fprintf(stderr, "FATAL! Not enough memory for struct capsam_TW9919_instance!\n");
		return RM_FATALOUTOFMEMORY;
	}
	RMMemset(pTW9919, 0, sizeof(struct capsam_TW9919_instance));
	*ppTW9919 = pTW9919;
	
	// Set default and startup values
	pTW9919->pRUA = pRUA;
	pTW9919->I2CModuleID = I2CModuleID;
	pTW9919->I2CDevice = *pI2CDevice;
	pTW9919->BaseDevice = pI2CDevice->DevAddr;
	
	// Set initial state
	pTW9919->state = INIT;
	
	// Set board specific configuration
	pTW9919->XtalClock = XtalClock;
	SetBoardSpecificEnv(pTW9919);
	
	return RM_OK;
}

RMstatus capsam_TW9919_close(struct capsam_TW9919_instance *pTW9919)
{
	// Sanity checks
	if (pTW9919 == NULL) return RM_FATALINVALIDPOINTER;
	
	// Free all ressources
	RMFree(pTW9919);
	
	return RM_OK;
}

RMstatus capsam_TW9919_tristate(struct capsam_TW9919_instance *pTW9919)
{
	// Sanity checks
	if (pTW9919 == NULL) return RM_FATALINVALIDPOINTER;
	RMDBGLOG((FUNCNAME, "%s\n",__func__));

	/*
	 * After reset, TW9919 data outputs are tristated.
	 */
	capsam_i2c_write_dev(pTW9919, pTW9919->BaseDevice, 0x06, 0x80); // SRESET=1

	capsam_i2c_write_dev(pTW9919, pTW9919->BaseDevice, 0x03, 0x86); // SRESET=1	
	//	capsam_i2c_write_dev(pTW9919, pTW9919->BaseDevice, 0x06, 0x8f); // SRESET=1 choi	
	return RM_OK;
}

RMstatus capsam_TW9919_init_capture(struct capsam_TW9919_instance *pTW9919,
				  const struct capsam_access *pInput)
{
	RMstatus err = RM_OK;
	
	// input port setting
	err = SetInputPortSetting(pTW9919, pInput->input);

	// memory controller setting
	err = SetMemCtrlSetting(pTW9919);
	
	// 3D comb filter setting
	err = Set3DCombFilterSetting(pTW9919);

	// TV standard autodetect
	err = SetTVStandardAutoDetectSetting(pTW9919);

	// output port setting
	SetVideoBusSetting(pTW9919);

	pTW9919->state = RUN;

	return err;
}

RMstatus capsam_TW9919_init_vbi(struct capsam_TW9919_instance *pTW9919,
			      const struct capsam_access *pInput)
{

	return RM_OK;
}

RMstatus capsam_TW9919_setup_audio(struct capsam_TW9919_instance *pTW9919, 
				struct capsam_update *pUpdate)
{
	//Audio clock generation for frequency of 27 Mhz :
	
	RMuint8 TW9919E_AMCLK_48KHZ_NTSC[][2]={
		//ACKI 0x40 - 0x42
		{0x40,	0x15},
		{0x41,	0x41},
		{0x42,	0x3a},
		//ACKN 0x43 - 0x45
		{0x43,	0xcd},
		{0x44,	0x20},
		{0x45,	0x03},
	};
	
	RMuint8 TW9919E_AMCLK_48KHZ_PAL[][2]={
		//ACKI 0x40 - 0x42
		{0x40,	0x15},
		{0x41,	0x41},
		{0x42,	0x3a},
		//ACKN 0x43 - 0x45
		{0x43,	0x00},
		{0x44,	0xc0},
		{0x45,	0x03},
	};
	RMuint8 TW9919E_AMCLK_44KHZ_NTSC[][2]={
		//ACKI 0x40 - 0x42
		{0x40,	0x65},
		{0x41,	0x85},
		{0x42,	0x35},
		//ACKN 0x43 - 0x45
		{0x43,	0xbc},
		{0x44,	0xdf},
		{0x45,	0x02},
	};
	
	RMuint8 TW9919E_AMCLK_44KHZ_PAL[][2]={
		//ACKI 0x40 - 0x42
		{0x40,	0x65},
		{0x41,	0x85},
		{0x42,	0x35},
		//ACKN 0x43 - 0x45
		{0x43,	0x00},
		{0x44,	0x72},
		{0x45,	0x03},
	};
	
	RMuint8 TW9919E_AMCLK_32KHZ_NTSC[][2]={
		//ACKI 0x40 - 0x42
		{0x40,	0x0e},
		{0x41,	0xd6},
		{0x42,	0x26},
		//ACKN 0x43 - 0x45
		{0x43,	0xde},
		{0x44,	0x15},
		{0x45,	0x02},
	};
	
	RMuint8 TW9919E_AMCLK_32KHZ_PAL[][2]={
		//ACKI 0x40 - 0x42
		{0x40,	0x0e},
		{0x41,	0xd6},
		{0x42,	0x26},
		//ACKN 0x43 - 0x45
		{0x43,	0x00},
		{0x44,	0x80},
		{0x45,	0x02},
	};
	
	RMuint8 TW9919E_AMCLK_8KHZ_NTSC[][2]={
		//ACKI 0x40 - 0x42
		{0x40,	0x83},
		{0x41,	0xb5},
		{0x42,	0x09},
		//ACKN 0x43 - 0x45
		{0x43,	0x78},
		{0x44,	0x85},
		{0x45,	0x00},
	};
	
	RMuint8 TW9919E_AMCLK_8KHZ_PAL[][2]={
		//ACKI 0x40 - 0x42
		{0x40,	0x83},
		{0x41,	0xb5},
		{0x42,	0x09},
		//ACKN 0x43 - 0x45
		{0x43,	0x00},
		{0x44,	0xa0},
		{0x45,	0x00},
	};	

	if (pUpdate->TVStandardValid && pUpdate->TVStandardUpdate) {
		RMbool isNTSC;
		IsNTSC(pUpdate->TVStandard, isNTSC);
		if (isNTSC) {
			/*
			 * when NTSC
			 * 0x07
			 * 0x08
			 * 0x09
			 * 0x0b
			 */
			if (pUpdate->AudioSampleRateValid && pUpdate->AudioSampleRateUpdate) {
				switch( pUpdate->AudioSampleRate){
				case 8000: // 8KHz
					capsam_i2c_init(pTW9919, pTW9919->BaseDevice,TW9919E_AMCLK_8KHZ_NTSC);
					break;
				case 32000: // 32KHz
					capsam_i2c_init(pTW9919, pTW9919->BaseDevice,TW9919E_AMCLK_32KHZ_NTSC);
					break;
				case 44100: // 44.1KHz
					capsam_i2c_init(pTW9919, pTW9919->BaseDevice,TW9919E_AMCLK_44KHZ_NTSC);
					break;
				case 48000: // 48KHz
					capsam_i2c_init(pTW9919, pTW9919->BaseDevice,TW9919E_AMCLK_48KHZ_NTSC);
					break;
				default:
					break;
				}
			}			
		} else {
			/*
			 * PAL
			 */
			if (pUpdate->AudioSampleRateValid && pUpdate->AudioSampleRateUpdate) {
				switch( pUpdate->AudioSampleRate){
				case 8000: // 8KHz
					capsam_i2c_init(pTW9919, pTW9919->BaseDevice,TW9919E_AMCLK_8KHZ_PAL);
					break;
				case 32000: // 32KHz
					capsam_i2c_init(pTW9919, pTW9919->BaseDevice,TW9919E_AMCLK_32KHZ_PAL);
					break;
				case 44100: // 44.1KHz
					capsam_i2c_init(pTW9919, pTW9919->BaseDevice,TW9919E_AMCLK_44KHZ_PAL);
					break;
				case 48000: // 48KHz
					capsam_i2c_init(pTW9919, pTW9919->BaseDevice,TW9919E_AMCLK_48KHZ_PAL);
					break;
				default:
					break;
				}
			}	
		}
	}

	return RM_OK;
}

RMstatus capsam_TW9919_setup_audio_mclk(struct capsam_TW9919_instance *pTW9919)
{
	RMuint8 TW9919E_AMCLK_44KHZ_NTSC[][2]={
		//ACKI 0x40 - 0x42
		{0x40,	0x65},
		{0x41,	0x85},
		{0x42,	0x35},
		//ACKN 0x43 - 0x45
		{0x43,	0xbc},
		{0x44,	0xdf},
		{0x45,	0x02},
	};
	
	RMDBGLOG((FUNCNAME, "%s\n",__func__));
	capsam_i2c_init(pTW9919, pTW9919->BaseDevice,TW9919E_AMCLK_44KHZ_NTSC);
	return RM_OK;

}

RMstatus capsam_TW9919_setup_output(struct capsam_TW9919_instance *pTW9919, 
				 struct capsam_update *pUpdate)
{

	if (pUpdate->VideoOff == TRUE) {
		return RM_ERROR;
	}

	if (pUpdate->TVStandardValid && pUpdate->TVStandardUpdate) {
		RMbool isNTSC;
		IsNTSC(pUpdate->TVStandard, isNTSC);
		if (isNTSC) {
			/*
			 * when NTSC
			 * 0x07
			 * 0x08
			 * 0x09
			 * 0x0b
			 */
			ConfigDefaultNTSC(pTW9919);
		}else{
			/*
			 * PAL
			 */
			ConfigDefaultPAL(pTW9919);
		}
	}
	
	if (pUpdate->TVFormatValid && pUpdate->TVFormatUpdate) {
		
	}

	if (pUpdate->PictureAspectRatioValid && pUpdate->PictureAspectRatioUpdate) {

	}

	if (pUpdate->InputColorSpaceValid && pUpdate->InputColorSpaceUpdate) {

	}

	if (pUpdate->InputColorFormatValid && pUpdate->InputColorFormatUpdate) {
		if(pUpdate->InputColorFormat == 1){

		}
	}
	return RM_OK;
}



RMstatus capsam_TW9919_check_int(struct capsam_TW9919_instance *pTW9919)
{
	/* 
	 * we detect interrupt at capsam_TW9919_handle_int.
	 * so, just return RM_OK here
	 */
	return RM_OK;
}

RMstatus capsam_TW9919_handle_int(struct capsam_TW9919_instance *pTW9919, 
				struct capsam_update *pUpdate)
{
	RMuint32 reg_0xB6 = 0;
	RMuint32 reg_0xB7 = 0;
	RMuint32 reg_0xB8 = 0;

	// read int status register
	capsam_i2c_read_dev(pTW9919, pTW9919->BaseDevice, 0xB6, &reg_0xB6);
	capsam_i2c_read_dev(pTW9919, pTW9919->BaseDevice, 0xB7, &reg_0xB7);
	capsam_i2c_read_dev(pTW9919, pTW9919->BaseDevice, 0xB8, &reg_0xB8);

	if (reg_0xB6) {
		HandleINT1(pTW9919, pUpdate, reg_0xB6);
		ClearINT1(pTW9919);
	}

	if (reg_0xB7) {
		HandleINT2(pTW9919, pUpdate, reg_0xB7);
		ClearINT2(pTW9919);		
	}

	if (reg_0xB8) {
		HandleINT3(pTW9919, pUpdate, reg_0xB8);
		ClearINT3(pTW9919);
	}
	return RM_OK;
}