play_capture_tw9919.c

1. 8623L平台

/*
 *
 * Copyright (c) 2001-2007 Sigma Designs, Inc. 
 * All Rights Reserved. Proprietary and Confidential.
 *
 */

/**
	@file   play_capture_TW9919.c
	@brief  device specific functions for play_capture_main application
	
	@author Christian Wolff Sean.Sekwon.Choi
*/

// to enable or disable the debug messages of this source file, put 1 or 0 below
#if 0
#define LOCALDBG ENABLE
#else
#define LOCALDBG DISABLE
#endif

#include "sample_os.h"
#define ALLOW_OS_CODE 1

#include "../rua/include/rua.h"
#include "../rua/include/rua_property.h"
#include "../dcc/include/dcc.h"
#include "../rmcore/include/rmstatustostring.h"
#include "../rmlibcw/include/rmlibcw.h"

#include "play_capture_common.h"
#include "play_capture_TW9919.h"
#include "play_capture_i2c.h"

enum state_TW9919{
	INIT = 0,
	RUN,
};

enum comb_filter{
	COMB_TEST_MODE_FRAME_DELAY_TEST1 = 0,
	COMB_TEST_MODE_FRAME_DELAY_TEST2,
	COMB_TEST_MODE_COMBINED_Y_MOTION,
	COMB_TEST_MODE_COMBINED_Y_C,
	COMB_FIXED_MODE_3D,
	COMB_FIXED_MODE_2D,
	COMB_ADAPTIVE_MODE_3D_ENABLE,
	COMB_ADAPTIVE_MODE_3D_DISABLE,
};

enum mem_ctrl{
	MEMCFG_16MX1 = 0,
	MEMCFG_16MX2,
	MEMCFG_64MX1,
};

enum video_bus{
	WIDTH_8BIT = 0,
	WIDTH_16BIT,
};

struct capsam_TW9919_instance {
	struct RUA *pRUA;
	RMuint32 I2CModuleID;
	struct EMhwlibI2CDeviceParameter I2CDevice;
	RMuint8 BaseDevice;

	// internal state
	RMuint32 state;

	// board specific configuration
	enum capsam_board board_config;
	enum comb_filter comb_filter_config;
	enum mem_ctrl mem_ctrl_config;
	enum video_bus video_bus_config;
	RMuint32 XtalClock;
};

/*
********************************************************************************
* internal functions (static functions)
********************************************************************************
*/

static RMstatus SetBoardSpecificEnv(struct capsam_TW9919_instance *pTW9919)
{
	/*
	**************************************************************
	 * This is board specific configuration
	 * You need to change this for your specific board schematics
	 ************************************************************** 
	*/

	// Sanity checks
	if (pTW9919 == NULL) return RM_FATALINVALIDPOINTER;

	/*
	 * Sigma DTV 8634 board 
	 */	
	pTW9919->board_config = capsam_sigma844e1dtv;
	pTW9919->comb_filter_config = COMB_ADAPTIVE_MODE_3D_ENABLE;	
	pTW9919->mem_ctrl_config = MEMCFG_64MX1;
	pTW9919->video_bus_config = WIDTH_8BIT;

	return RM_OK;
}

static RMstatus SetInputPortSetting(struct capsam_TW9919_instance *pTW9919,
				    enum capsam_input input)
{
	/*
	 * This is board specific configuration
	 */

	RMuint32 reg_0x02 = 0;
	
	RMuint32 YSEL2 = 0;
	RMuint32 FC27 = 1;
	RMuint32 IFSEL = 0;
	RMuint32 YSEL = 0;
	RMuint32 CSEL = 0;
	RMuint32 VSEL = 0;

	/*
	 * Sigma DTV 8634 board 
	 * You need to change this matix for your board schematics
	 */
	if (pTW9919->board_config == capsam_sigma844e1dtv) {
		switch (input) {
		case capsam_input_tuner1:
			// Tuner CVBS - MUX2
			YSEL = 2;
			// composite video decoding
			IFSEL = 0;
			break;
			
		case capsam_input_cvbs1:
			// VIN1-CVBS - MUX0
			YSEL = 0;
			YSEL2 = 0;
			// composite video decoding
			IFSEL = 0;
			break;
			
		case capsam_input_cvbs2:
			// VIN2-CVBS - MUX3
			YSEL = 3;
			YSEL2 = 0;
			// composite video decoding
			IFSEL = 0;
			break;
			
		case capsam_input_svideo1:
			// VIN1-Y - MUX1
			// VIN1-C - CIN0
			YSEL = 1;
			YSEL2= 0;
			CSEL = 0;
			// S-video decoding
			IFSEL = 1;
			break;
			
		case capsam_input_svideo2:
			// VIN2-Y - MUX4
			// VIN2-C - CIN1
			YSEL = 0;
			YSEL2 = 1;
			CSEL = 0;		
			// S-video decoding
			IFSEL = 1;
			break;
			
		case capsam_input_component1:
		case capsam_input_component2:
			// not routed to TW7719 in this board
			break;
			
		case capsam_input_scart1:
			// SCIN-R - RIN0
			// SCIN-B - BIN0
			// SCIN-G - GIN0
			VSEL = 0;
			// composite video decoding
			IFSEL = 0;
			break;
			
		case capsam_input_scart2:
			// SCIN-R2 - RIN1
			// SCIN-B2 - BIN1
			// SCIN-G2 - GIN1
			VSEL = 1;
			// composite video decoding
			IFSEL = 0;		
			break;
		case capsam_input_none:
		case capsam_input_tuner2:
		case capsam_input_vga:
		case capsam_input_dvi:
		case capsam_input_hdmi:
		case capsam_input_last:
		default:
			break;
		}
	}
	
	RMinsShiftBits(&reg_0x02, YSEL2, 1, 7);
	RMinsShiftBits(&reg_0x02, FC27, 1, 6);
	RMinsShiftBits(&reg_0x02, IFSEL, 2, 4);
	RMinsShiftBits(&reg_0x02, YSEL, 2, 2);
	RMinsShiftBits(&reg_0x02, CSEL, 1, 1);
	RMinsShiftBits(&reg_0x02, VSEL, 1, 0);

	capsam_i2c_write_dev(pTW9919, pTW9919->BaseDevice, 0x02, reg_0x02);

	return RM_OK;
}

static RMstatus SetVideoBusSetting(struct capsam_TW9919_instance *pTW9919)
{
	RMstatus err = RM_OK;
	RMuint32 reg_0x03 = 0;
	RMuint32 LEN = 0;

	capsam_i2c_read_dev(pTW9919, pTW9919->BaseDevice, 0x03, &reg_0x03);
	
	if (pTW9919->video_bus_config == WIDTH_16BIT) {
		LEN = 1;
	} else {
		LEN = 0;
	}

	RMinsShiftBits(&reg_0x03, LEN, 1, 6);
	capsam_i2c_write_dev(pTW9919, pTW9919->BaseDevice, 0x03, reg_0x03);
	return err;
}

static RMstatus SetMemCtrlSetting(struct capsam_TW9919_instance *pTW9919)
{
	/*
	 * This is board specific configuration
	 */

	RMuint32 reg_0x72 = 0;
	RMuint32 MEMCFG = 0;

	capsam_i2c_read_dev(pTW9919, pTW9919->BaseDevice, 0x72, &reg_0x72);

	switch (pTW9919->mem_ctrl_config) {
	case MEMCFG_16MX1:
		MEMCFG = 0;
		break;
	case MEMCFG_16MX2:
		MEMCFG = 1;
		break;
	case MEMCFG_64MX1:
		MEMCFG = 2;
		break;
	default:
		break;
	}

	RMinsShiftBits(&reg_0x72, MEMCFG, 2, 3);
	capsam_i2c_write_dev(pTW9919, pTW9919->BaseDevice, 0x72, reg_0x72);
	return RM_OK;
}

static RMstatus Set3DCombFilterSetting(struct capsam_TW9919_instance *pTW9919)
{
	RMuint32 reg_0x72 = 0;
	RMuint32 TM_3D = 0;
	RMuint32 TEST3D = 0;
	RMuint32 MIXMD1 = 0;
	RMuint32 MIXMD2 = 0;
	RMuint32 EN_3D = 0;

	capsam_i2c_read_dev(pTW9919, pTW9919->BaseDevice, 0x72, &reg_0x72);

	switch (pTW9919->comb_filter_config) {
	case COMB_TEST_MODE_FRAME_DELAY_TEST1:
		EN_3D = 1;
		TEST3D = 1;
		TM_3D = 0;
		break;
	case COMB_TEST_MODE_FRAME_DELAY_TEST2:
		EN_3D = 1;
		TEST3D = 1;
		TM_3D = 1;
		break;
	case COMB_TEST_MODE_COMBINED_Y_MOTION:
		EN_3D = 1;
		TEST3D = 1;
		TM_3D = 2;
		break;
	case COMB_TEST_MODE_COMBINED_Y_C:
		EN_3D = 1;
		TEST3D = 1;
		TM_3D = 3;
		break;
	case COMB_FIXED_MODE_3D:
		EN_3D = 1;
		MIXMD1 = 1;
		MIXMD2 = 0;
		TEST3D = 0;
		break;
	case COMB_FIXED_MODE_2D:
		EN_3D = 0;
		MIXMD1 = 1;
		MIXMD2 = 1;
		TEST3D = 0;
		break;
	case COMB_ADAPTIVE_MODE_3D_ENABLE:
		EN_3D = 1;
		MIXMD1 = 0;
		TEST3D = 0;
		break;
	case COMB_ADAPTIVE_MODE_3D_DISABLE:
		EN_3D = 0;	
		TEST3D = 0;
		MIXMD1 = 0;
		break;
	default:
	break;
	}

	RMinsShiftBits(&reg_0x72, TM_3D, 2, 0);
	RMinsShiftBits(&reg_0x72, TEST3D, 1, 2);	
	RMinsShiftBits(&reg_0x72, MIXMD2, 1, 5);
	RMinsShiftBits(&reg_0x72, MIXMD1, 1, 6);
	RMinsShiftBits(&reg_0x72, EN_3D, 1, 7);

	capsam_i2c_write_dev(pTW9919, pTW9919->BaseDevice, 0x72, reg_0x72);

	return RM_OK;
}

static  RMstatus SetTVStandardAutoDetectSetting(struct capsam_TW9919_instance *pTW9919)
{
	RMuint32 reg_0x1c = 0;
	RMuint32 STD = 0;	
	RMuint32 SDTR = 0xff; // all format detection enable
	
	/*
	 * Auto detection enable
	 */

	capsam_i2c_read_dev(pTW9919, pTW9919->BaseDevice, 0x1c, &reg_0x1c);	

	STD = 0x07;

	RMinsShiftBits(&reg_0x1c, STD, 3, 0);
	
	capsam_i2c_write_dev(pTW9919, pTW9919->BaseDevice, 0x1c, reg_0x1c);	

	/* 
	 * Trigger auto detection
	 */
	
	capsam_i2c_write_dev(pTW9919, pTW9919->BaseDevice, 0x1d, SDTR);		
	
	
	return RM_OK;
}

static RMstatus ConfigDefaultNTSC(struct capsam_TW9919_instance *pTW9919)
{
	RMuint8 TW9919E_CCIR_NTSC_DataSet[][2] = {			
		
		//	 {0x02, 0x70},		// for 27MHz PLL unstable on power reset time
		{0x81, 0x09},		// for MCLK unstable
		{0x03, 0xa2},
		{0x05, 0x00},		// for RevE
		{0x09, 0xf6},
		//	{0x0a, 0x21},		// For adjusting H position	
		{0x0a, 0xf},		// For adjusting H position	
		{0x0f, 0x1},		
		{0x12, 0x12},
		{0x19, 0x57},
		//	{0x19, 0x5f},
		{0x1a, 0x07},
		//	{0x1b, 0x20},		// for RevE clk2--> vclk, clk1 --> clkx1(freerun)
		{0x1b, 0x10}, //A Tho
		{0x21, 0x62},		//for white saturation on low sync level
		//	{0x23, 0xec},		//for RevE, use default value(0xd8)
		{0x23, 0xd8},		// Not sure 
		{0x28, 0x02},		//for solve from even/odd switch suddenly
		{0x29, 0x02},		//Changed for v-sync out scheme
		{0x2d, 0x54},		// for prevent field error on bad tape
		{0x33, 0x08},		//for improving HV shaking on week signal
		//	{0x33, 0x05}, //dung huynh restore default value
		{0x36, 0x00},
		//	{0x39, 0x0b},
		{0x39, 0x02}, //A Tho
		
		{0x55, 0x10},
		{0x6b, 0x26},
		{0x6c, 0x36},
		{0x6d, 0x25},		//Changed for v-sync out scheme
		{0x6e, 0x40},		//Changed for v-sync out scheme
		//	{0x70, 0x0a},		// for RevE
		{0x70, 0x07}, //A Tho
		{0x73, 0xc0}, //A Tho
		{0x75, 0x04},		// for RevE
		{0x76, 0x95}, //A Tho
		{0x81, 0x08},
		{0x06, 0x80},	// Reset .	
		
	};

	capsam_i2c_init(pTW9919, pTW9919->BaseDevice,TW9919E_CCIR_NTSC_DataSet);

	return RM_OK;
}

static RMstatus ConfigDefaultPAL(struct capsam_TW9919_instance *pTW9919)
{
	RMuint8 TW9919E_CCIR_PAL_DataSet[][2] = {		
		//	 {0x02, 0x70},		// for PLL unstable on power reset time
		{0x81, 0x09},		// for MCLK unstable
		{0x03, 0xa2},
		{0x05, 0x88},		// for RevE (Not sure )
		//	{0x0a, 0x16},		// For adjusting H position
		{0x0a, 0xf},		// For adjusting H position
		{0x0f, 0x1},		
		{0x12, 0x12},
		{0x19, 0x57},
		{0x1a, 0x07},
		//	{0x1b, 0x20},		// for RevE clk2--> vclk, clk1 --> clkx1(freerun)
		{0x1b, 0x10}, //A Tho
		{0x21, 0x62},		//for white saturation on low sync level
		//	{0x23, 0xec},		//for RevE, use default value(0xd8)
		{0x23, 0xd8},		// Not sure 
		{0x28, 0x02},		//for solve from even/odd switch suddenly
		{0x29, 0x02},		//Changed for v-sync out scheme
		{0x2d, 0x54},		// for prevent field error on bad tape