de_pl_mpsk.tan.rpt

QPSK的VHDL调制解调 FPGA设计思路思想

+-------+------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------+
; tsu                                                           ;
+-------+--------------+------------+-------+--------+----------+
; Slack ; Required tsu ; Actual tsu ; From  ; To     ; To Clock ;
+-------+--------------+------------+-------+--------+----------+
; N/A   ; None         ; 4.134 ns   ; start ; yy[1]  ; clk      ;
; N/A   ; None         ; 4.134 ns   ; start ; yy[0]  ; clk      ;
; N/A   ; None         ; 4.134 ns   ; start ; yy[2]  ; clk      ;
; N/A   ; None         ; 3.466 ns   ; start ; xx[0]  ; clk      ;
; N/A   ; None         ; 3.466 ns   ; start ; xx[2]  ; clk      ;
; N/A   ; None         ; 3.466 ns   ; start ; xx[1]  ; clk      ;
; N/A   ; None         ; 3.453 ns   ; start ; y~reg0 ; clk      ;
; N/A   ; None         ; 3.316 ns   ; start ; q[2]   ; clk      ;
; N/A   ; None         ; 3.314 ns   ; start ; q[1]   ; clk      ;
; N/A   ; None         ; 3.314 ns   ; start ; q[0]   ; clk      ;
; N/A   ; None         ; 2.999 ns   ; x     ; xx[2]  ; clk      ;
; N/A   ; None         ; 2.882 ns   ; x     ; xx[1]  ; clk      ;
; N/A   ; None         ; 2.873 ns   ; x     ; xx[0]  ; clk      ;
+-------+--------------+------------+-------+--------+----------+


+--------------------------------------------------------------+
; tco                                                          ;
+-------+--------------+------------+--------+----+------------+
; Slack ; Required tco ; Actual tco ; From   ; To ; From Clock ;
+-------+--------------+------------+--------+----+------------+
; N/A   ; None         ; 5.541 ns   ; y~reg0 ; y  ; clk        ;
+-------+--------------+------------+--------+----+------------+


+---------------------------------------------------------------------+
; th                                                                  ;
+---------------+-------------+-----------+-------+--------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To     ; To Clock ;
+---------------+-------------+-----------+-------+--------+----------+
; N/A           ; None        ; -2.634 ns ; x     ; xx[0]  ; clk      ;
; N/A           ; None        ; -2.643 ns ; x     ; xx[1]  ; clk      ;
; N/A           ; None        ; -2.760 ns ; x     ; xx[2]  ; clk      ;
; N/A           ; None        ; -3.075 ns ; start ; q[1]   ; clk      ;
; N/A           ; None        ; -3.075 ns ; start ; q[0]   ; clk      ;
; N/A           ; None        ; -3.077 ns ; start ; q[2]   ; clk      ;
; N/A           ; None        ; -3.214 ns ; start ; y~reg0 ; clk      ;
; N/A           ; None        ; -3.227 ns ; start ; xx[0]  ; clk      ;
; N/A           ; None        ; -3.227 ns ; start ; xx[2]  ; clk      ;
; N/A           ; None        ; -3.227 ns ; start ; xx[1]  ; clk      ;
; N/A           ; None        ; -3.895 ns ; start ; yy[1]  ; clk      ;
; N/A           ; None        ; -3.895 ns ; start ; yy[0]  ; clk      ;
; N/A           ; None        ; -3.895 ns ; start ; yy[2]  ; clk      ;
+---------------+-------------+-----------+-------+--------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition
    Info: Processing started: Sun Mar 16 17:02:21 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off de_PL_MPSK -c de_PL_MPSK --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 500.0 MHz between source register "q[0]" and destination register "yy[1]"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.455 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y7_N27; Fanout = 8; REG Node = 'q[0]'
            Info: 2: + IC(0.254 ns) + CELL(0.228 ns) = 0.482 ns; Loc. = LCCOMB_X31_Y7_N12; Fanout = 3; COMB Node = 'yy[0]~117'
            Info: 3: + IC(0.227 ns) + CELL(0.746 ns) = 1.455 ns; Loc. = LCFF_X31_Y7_N7; Fanout = 2; REG Node = 'yy[1]'
            Info: Total cell delay = 0.974 ns ( 66.94 % )
            Info: Total interconnect delay = 0.481 ns ( 33.06 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.469 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.654 ns) + CELL(0.618 ns) = 2.469 ns; Loc. = LCFF_X31_Y7_N7; Fanout = 2; REG Node = 'yy[1]'
                Info: Total cell delay = 1.472 ns ( 59.62 % )
                Info: Total interconnect delay = 0.997 ns ( 40.38 % )
            Info: - Longest clock path from clock "clk" to source register is 2.469 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.654 ns) + CELL(0.618 ns) = 2.469 ns; Loc. = LCFF_X31_Y7_N27; Fanout = 8; REG Node = 'q[0]'
                Info: Total cell delay = 1.472 ns ( 59.62 % )
                Info: Total interconnect delay = 0.997 ns ( 40.38 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Info: tsu for register "yy[1]" (data pin = "start", clock pin = "clk") is 4.134 ns
    Info: + Longest pin to register delay is 6.513 ns
        Info: 1: + IC(0.000 ns) + CELL(0.790 ns) = 0.790 ns; Loc. = PIN_P17; Fanout = 8; PIN Node = 'start'
        Info: 2: + IC(4.384 ns) + CELL(0.366 ns) = 5.540 ns; Loc. = LCCOMB_X31_Y7_N12; Fanout = 3; COMB Node = 'yy[0]~117'
        Info: 3: + IC(0.227 ns) + CELL(0.746 ns) = 6.513 ns; Loc. = LCFF_X31_Y7_N7; Fanout = 2; REG Node = 'yy[1]'
        Info: Total cell delay = 1.902 ns ( 29.20 % )
        Info: Total interconnect delay = 4.611 ns ( 70.80 % )
    Info: + Micro setup delay of destination is 0.090 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.469 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.654 ns) + CELL(0.618 ns) = 2.469 ns; Loc. = LCFF_X31_Y7_N7; Fanout = 2; REG Node = 'yy[1]'
        Info: Total cell delay = 1.472 ns ( 59.62 % )
        Info: Total interconnect delay = 0.997 ns ( 40.38 % )
Info: tco from clock "clk" to destination pin "y" through register "y~reg0" is 5.541 ns
    Info: + Longest clock path from clock "clk" to source register is 2.469 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.654 ns) + CELL(0.618 ns) = 2.469 ns; Loc. = LCFF_X31_Y7_N17; Fanout = 2; REG Node = 'y~reg0'
        Info: Total cell delay = 1.472 ns ( 59.62 % )
        Info: Total interconnect delay = 0.997 ns ( 40.38 % )
    Info: + Micro clock to output delay of source is 0.094 ns
    Info: + Longest register to pin delay is 2.978 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y7_N17; Fanout = 2; REG Node = 'y~reg0'
        Info: 2: + IC(0.824 ns) + CELL(2.154 ns) = 2.978 ns; Loc. = PIN_T1; Fanout = 0; PIN Node = 'y'
        Info: Total cell delay = 2.154 ns ( 72.33 % )
        Info: Total interconnect delay = 0.824 ns ( 27.67 % )
Info: th for register "xx[0]" (data pin = "x", clock pin = "clk") is -2.634 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.469 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.654 ns) + CELL(0.618 ns) = 2.469 ns; Loc. = LCFF_X31_Y7_N3; Fanout = 4; REG Node = 'xx[0]'
        Info: Total cell delay = 1.472 ns ( 59.62 % )
        Info: Total interconnect delay = 0.997 ns ( 40.38 % )
    Info: + Micro hold delay of destination is 0.149 ns
    Info: - Shortest pin to register delay is 5.252 ns
        Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_T2; Fanout = 3; PIN Node = 'x'
        Info: 2: + IC(3.921 ns) + CELL(0.346 ns) = 5.097 ns; Loc. = LCCOMB_X31_Y7_N2; Fanout = 1; COMB Node = 'xx~1330'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.252 ns; Loc. = LCFF_X31_Y7_N3; Fanout = 4; REG Node = 'xx[0]'
        Info: Total cell delay = 1.331 ns ( 25.34 % )
        Info: Total interconnect delay = 3.921 ns ( 74.66 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 111 megabytes of memory during processing
    Info: Processing ended: Sun Mar 16 17:02:23 2008
    Info: Elapsed time: 00:00:02