📄 de_pl_mpsk.tan.rpt
字号:
Classic Timing Analyzer report for de_PL_MPSK
Sun Mar 16 17:02:22 2008
Quartus II Version 7.1 Build 156 04/30/2007 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+--------+-------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+--------+-------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 4.134 ns ; start ; yy[2] ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 5.541 ns ; y~reg0 ; y ; clk ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -2.634 ns ; x ; xx[0] ; -- ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[0] ; yy[2] ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+--------+-------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2S15F484C3 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[0] ; yy[1] ; clk ; clk ; None ; None ; 1.455 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[0] ; yy[0] ; clk ; clk ; None ; None ; 1.455 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[0] ; yy[2] ; clk ; clk ; None ; None ; 1.455 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[1] ; yy[1] ; clk ; clk ; None ; None ; 1.430 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[1] ; yy[0] ; clk ; clk ; None ; None ; 1.430 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[1] ; yy[2] ; clk ; clk ; None ; None ; 1.430 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[2] ; yy[1] ; clk ; clk ; None ; None ; 1.251 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[2] ; yy[0] ; clk ; clk ; None ; None ; 1.251 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[2] ; yy[2] ; clk ; clk ; None ; None ; 1.251 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[2] ; xx[2] ; clk ; clk ; None ; None ; 1.162 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[1] ; xx[2] ; clk ; clk ; None ; None ; 1.022 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[0] ; xx[1] ; clk ; clk ; None ; None ; 1.019 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[0] ; y~reg0 ; clk ; clk ; None ; None ; 1.006 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[0] ; xx[0] ; clk ; clk ; None ; None ; 0.976 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[0] ; q[2] ; clk ; clk ; None ; None ; 0.974 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[0] ; xx[2] ; clk ; clk ; None ; None ; 0.965 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[1] ; xx[1] ; clk ; clk ; None ; None ; 0.919 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[1] ; y~reg0 ; clk ; clk ; None ; None ; 0.915 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[2] ; xx[0] ; clk ; clk ; None ; None ; 0.909 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; xx[0] ; xx[2] ; clk ; clk ; None ; None ; 0.879 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[2] ; xx[1] ; clk ; clk ; None ; None ; 0.790 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[0] ; q[1] ; clk ; clk ; None ; None ; 0.761 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; yyy[1] ; y~reg0 ; clk ; clk ; None ; None ; 0.761 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; yy[1] ; yyy[0] ; clk ; clk ; None ; None ; 0.689 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; xx[1] ; xx[2] ; clk ; clk ; None ; None ; 0.682 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[2] ; y~reg0 ; clk ; clk ; None ; None ; 0.640 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; yy[1] ; yyy[1] ; clk ; clk ; None ; None ; 0.639 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; yyy[0] ; y~reg0 ; clk ; clk ; None ; None ; 0.607 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; yy[0] ; yyy[1] ; clk ; clk ; None ; None ; 0.604 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; xx[0] ; xx[1] ; clk ; clk ; None ; None ; 0.570 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; xx[0] ; yy[0] ; clk ; clk ; None ; None ; 0.552 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; yy[0] ; yyy[0] ; clk ; clk ; None ; None ; 0.535 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[1] ; xx[0] ; clk ; clk ; None ; None ; 0.531 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[1] ; q[2] ; clk ; clk ; None ; None ; 0.529 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; xx[2] ; yy[2] ; clk ; clk ; None ; None ; 0.529 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[1] ; q[1] ; clk ; clk ; None ; None ; 0.488 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[0] ; q[0] ; clk ; clk ; None ; None ; 0.488 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[2] ; q[2] ; clk ; clk ; None ; None ; 0.488 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; xx[0] ; xx[0] ; clk ; clk ; None ; None ; 0.488 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; xx[2] ; xx[2] ; clk ; clk ; None ; None ; 0.488 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; y~reg0 ; y~reg0 ; clk ; clk ; None ; None ; 0.433 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; yy[2] ; yyy[0] ; clk ; clk ; None ; None ; 0.433 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; yy[2] ; yyy[1] ; clk ; clk ; None ; None ; 0.427 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; xx[1] ; yy[1] ; clk ; clk ; None ; None ; 0.426 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; xx[1] ; xx[1] ; clk ; clk ; None ; None ; 0.396 ns ;
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