de_pl_mpsk.tan.qmsg

QPSK的VHDL调制解调 FPGA设计思路思想

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register q\[0\] yy\[1\] 500.0 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 500.0 MHz between source register \"q\[0\]\" and destination register \"yy\[1\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.455 ns + Longest register register " "Info: + Longest register to register delay is 1.455 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[0\] 1 REG LCFF_X31_Y7_N27 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y7_N27; Fanout = 8; REG Node = 'q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { q[0] } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.254 ns) + CELL(0.228 ns) 0.482 ns yy\[0\]~117 2 COMB LCCOMB_X31_Y7_N12 3 " "Info: 2: + IC(0.254 ns) + CELL(0.228 ns) = 0.482 ns; Loc. = LCCOMB_X31_Y7_N12; Fanout = 3; COMB Node = 'yy\[0\]~117'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.482 ns" { q[0] yy[0]~117 } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.227 ns) + CELL(0.746 ns) 1.455 ns yy\[1\] 3 REG LCFF_X31_Y7_N7 2 " "Info: 3: + IC(0.227 ns) + CELL(0.746 ns) = 1.455 ns; Loc. = LCFF_X31_Y7_N7; Fanout = 2; REG Node = 'yy\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.973 ns" { yy[0]~117 yy[1] } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.974 ns ( 66.94 % ) " "Info: Total cell delay = 0.974 ns ( 66.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.481 ns ( 33.06 % ) " "Info: Total interconnect delay = 0.481 ns ( 33.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.455 ns" { q[0] yy[0]~117 yy[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.455 ns" { q[0] yy[0]~117 yy[1] } { 0.000ns 0.254ns 0.227ns } { 0.000ns 0.228ns 0.746ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.469 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.469 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 12 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.654 ns) + CELL(0.618 ns) 2.469 ns yy\[1\] 3 REG LCFF_X31_Y7_N7 2 " "Info: 3: + IC(0.654 ns) + CELL(0.618 ns) = 2.469 ns; Loc. = LCFF_X31_Y7_N7; Fanout = 2; REG Node = 'yy\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.272 ns" { clk~clkctrl yy[1] } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.62 % ) " "Info: Total cell delay = 1.472 ns ( 59.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.997 ns ( 40.38 % ) " "Info: Total interconnect delay = 0.997 ns ( 40.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.469 ns" { clk clk~clkctrl yy[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.469 ns" { clk clk~combout clk~clkctrl yy[1] } { 0.000ns 0.000ns 0.343ns 0.654ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.469 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.469 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 12 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.654 ns) + CELL(0.618 ns) 2.469 ns q\[0\] 3 REG LCFF_X31_Y7_N27 8 " "Info: 3: + IC(0.654 ns) + CELL(0.618 ns) = 2.469 ns; Loc. = LCFF_X31_Y7_N27; Fanout = 8; REG Node = 'q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.272 ns" { clk~clkctrl q[0] } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.62 % ) " "Info: Total cell delay = 1.472 ns ( 59.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.997 ns ( 40.38 % ) " "Info: Total interconnect delay = 0.997 ns ( 40.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.469 ns" { clk clk~clkctrl q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.469 ns" { clk clk~combout clk~clkctrl q[0] } { 0.000ns 0.000ns 0.343ns 0.654ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.469 ns" { clk clk~clkctrl yy[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.469 ns" { clk clk~combout clk~clkctrl yy[1] } { 0.000ns 0.000ns 0.343ns 0.654ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.469 ns" { clk clk~clkctrl q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.469 ns" { clk clk~combout clk~clkctrl q[0] } { 0.000ns 0.000ns 0.343ns 0.654ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.455 ns" { q[0] yy[0]~117 yy[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.455 ns" { q[0] yy[0]~117 yy[1] } { 0.000ns 0.254ns 0.227ns } { 0.000ns 0.228ns 0.746ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.469 ns" { clk clk~clkctrl yy[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.469 ns" { clk clk~combout clk~clkctrl yy[1] } { 0.000ns 0.000ns 0.343ns 0.654ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.469 ns" { clk clk~clkctrl q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.469 ns" { clk clk~combout clk~clkctrl q[0] } { 0.000ns 0.000ns 0.343ns 0.654ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { yy[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { yy[1] } {  } {  } "" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 19 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "yy\[1\] start clk 4.134 ns register " "Info: tsu for register \"yy\[1\]\" (data pin = \"start\", clock pin = \"clk\") is 4.134 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.513 ns + Longest pin register " "Info: + Longest pin to register delay is 6.513 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.790 ns) 0.790 ns start 1 PIN PIN_P17 8 " "Info: 1: + IC(0.000 ns) + CELL(0.790 ns) = 0.790 ns; Loc. = PIN_P17; Fanout = 8; PIN Node = 'start'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { start } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.384 ns) + CELL(0.366 ns) 5.540 ns yy\[0\]~117 2 COMB LCCOMB_X31_Y7_N12 3 " "Info: 2: + IC(4.384 ns) + CELL(0.366 ns) = 5.540 ns; Loc. = LCCOMB_X31_Y7_N12; Fanout = 3; COMB Node = 'yy\[0\]~117'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.750 ns" { start yy[0]~117 } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.227 ns) + CELL(0.746 ns) 6.513 ns yy\[1\] 3 REG LCFF_X31_Y7_N7 2 " "Info: 3: + IC(0.227 ns) + CELL(0.746 ns) = 6.513 ns; Loc. = LCFF_X31_Y7_N7; Fanout = 2; REG Node = 'yy\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.973 ns" { yy[0]~117 yy[1] } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.902 ns ( 29.20 % ) " "Info: Total cell delay = 1.902 ns ( 29.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.611 ns ( 70.80 % ) " "Info: Total interconnect delay = 4.611 ns ( 70.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.513 ns" { start yy[0]~117 yy[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.513 ns" { start start~combout yy[0]~117 yy[1] } { 0.000ns 0.000ns 4.384ns 0.227ns } { 0.000ns 0.790ns 0.366ns 0.746ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.469 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.469 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 12 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.654 ns) + CELL(0.618 ns) 2.469 ns yy\[1\] 3 REG LCFF_X31_Y7_N7 2 " "Info: 3: + IC(0.654 ns) + CELL(0.618 ns) = 2.469 ns; Loc. = LCFF_X31_Y7_N7; Fanout = 2; REG Node = 'yy\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.272 ns" { clk~clkctrl yy[1] } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.62 % ) " "Info: Total cell delay = 1.472 ns ( 59.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.997 ns ( 40.38 % ) " "Info: Total interconnect delay = 0.997 ns ( 40.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.469 ns" { clk clk~clkctrl yy[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.469 ns" { clk clk~combout clk~clkctrl yy[1] } { 0.000ns 0.000ns 0.343ns 0.654ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.513 ns" { start yy[0]~117 yy[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.513 ns" { start start~combout yy[0]~117 yy[1] } { 0.000ns 0.000ns 4.384ns 0.227ns } { 0.000ns 0.790ns 0.366ns 0.746ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.469 ns" { clk clk~clkctrl yy[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.469 ns" { clk clk~combout clk~clkctrl yy[1] } { 0.000ns 0.000ns 0.343ns 0.654ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk y y~reg0 5.541 ns register " "Info: tco from clock \"clk\" to destination pin \"y\" through register \"y~reg0\" is 5.541 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.469 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.469 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 12 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.654 ns) + CELL(0.618 ns) 2.469 ns y~reg0 3 REG LCFF_X31_Y7_N17 2 " "Info: 3: + IC(0.654 ns) + CELL(0.618 ns) = 2.469 ns; Loc. = LCFF_X31_Y7_N17; Fanout = 2; REG Node = 'y~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.272 ns" { clk~clkctrl y~reg0 } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 19 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.62 % ) " "Info: Total cell delay = 1.472 ns ( 59.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.997 ns ( 40.38 % ) " "Info: Total interconnect delay = 0.997 ns ( 40.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.469 ns" { clk clk~clkctrl y~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.469 ns" { clk clk~combout clk~clkctrl y~reg0 } { 0.000ns 0.000ns 0.343ns 0.654ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 19 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.978 ns + Longest register pin " "Info: + Longest register to pin delay is 2.978 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns y~reg0 1 REG LCFF_X31_Y7_N17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y7_N17; Fanout = 2; REG Node = 'y~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { y~reg0 } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 19 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.824 ns) + CELL(2.154 ns) 2.978 ns y 2 PIN PIN_T1 0 " "Info: 2: + IC(0.824 ns) + CELL(2.154 ns) = 2.978 ns; Loc. = PIN_T1; Fanout = 0; PIN Node = 'y'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.978 ns" { y~reg0 y } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.154 ns ( 72.33 % ) " "Info: Total cell delay = 2.154 ns ( 72.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.824 ns ( 27.67 % ) " "Info: Total interconnect delay = 0.824 ns ( 27.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.978 ns" { y~reg0 y } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.978 ns" { y~reg0 y } { 0.000ns 0.824ns } { 0.000ns 2.154ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.469 ns" { clk clk~clkctrl y~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.469 ns" { clk clk~combout clk~clkctrl y~reg0 } { 0.000ns 0.000ns 0.343ns 0.654ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.978 ns" { y~reg0 y } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.978 ns" { y~reg0 y } { 0.000ns 0.824ns } { 0.000ns 2.154ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "xx\[0\] x clk -2.634 ns register " "Info: th for register \"xx\[0\]\" (data pin = \"x\", clock pin = \"clk\") is -2.634 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.469 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.469 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 12 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.654 ns) + CELL(0.618 ns) 2.469 ns xx\[0\] 3 REG LCFF_X31_Y7_N3 4 " "Info: 3: + IC(0.654 ns) + CELL(0.618 ns) = 2.469 ns; Loc. = LCFF_X31_Y7_N3; Fanout = 4; REG Node = 'xx\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.272 ns" { clk~clkctrl xx[0] } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.62 % ) " "Info: Total cell delay = 1.472 ns ( 59.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.997 ns ( 40.38 % ) " "Info: Total interconnect delay = 0.997 ns ( 40.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.469 ns" { clk clk~clkctrl xx[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.469 ns" { clk clk~combout clk~clkctrl xx[0] } { 0.000ns 0.000ns 0.343ns 0.654ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" {  } { { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.252 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.252 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.830 ns) 0.830 ns x 1 PIN PIN_T2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_T2; Fanout = 3; PIN Node = 'x'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { x } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.921 ns) + CELL(0.346 ns) 5.097 ns xx~1330 2 COMB LCCOMB_X31_Y7_N2 1 " "Info: 2: + IC(3.921 ns) + CELL(0.346 ns) = 5.097 ns; Loc. = LCCOMB_X31_Y7_N2; Fanout = 1; COMB Node = 'xx~1330'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.267 ns" { x xx~1330 } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 5.252 ns xx\[0\] 3 REG LCFF_X31_Y7_N3 4 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.252 ns; Loc. = LCFF_X31_Y7_N3; Fanout = 4; REG Node = 'xx\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { xx~1330 xx[0] } "NODE_NAME" } } { "de_PL_MPSK.vhd" "" { Text "D:/work1/work2/de_PL_MPSK.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.331 ns ( 25.34 % ) " "Info: Total cell delay = 1.331 ns ( 25.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.921 ns ( 74.66 % ) " "Info: Total interconnect delay = 3.921 ns ( 74.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.252 ns" { x xx~1330 xx[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.252 ns" { x x~combout xx~1330 xx[0] } { 0.000ns 0.000ns 3.921ns 0.000ns } { 0.000ns 0.830ns 0.346ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.469 ns" { clk clk~clkctrl xx[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.469 ns" { clk clk~combout clk~clkctrl xx[0] } { 0.000ns 0.000ns 0.343ns 0.654ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.252 ns" { x xx~1330 xx[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.252 ns" { x x~combout xx~1330 xx[0] } { 0.000ns 0.000ns 3.921ns 0.000ns } { 0.000ns 0.830ns 0.346ns 0.155ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}