de_pl_mpsk.map.rpt

QPSK的VHDL调制解调 FPGA设计思路思想

; HDL message level                                                           ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                             ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                    ; 100                ; 100                ;
; Clock MUX Protection                                                        ; On                 ; On                 ;
; Use smart compilation                                                       ; Off                ; Off                ;
+-----------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                               ;
+----------------------------------+-----------------+-----------------+-------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path  ;
+----------------------------------+-----------------+-----------------+-------------------------------+
; de_PL_MPSK.vhd                   ; yes             ; User VHDL File  ; D:/work1/work2/de_PL_MPSK.vhd ;
+----------------------------------+-----------------+-----------------+-------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+-----------------------------------------------+-------+
; Resource                                      ; Usage ;
+-----------------------------------------------+-------+
; Estimated ALUTs Used                          ; 11    ;
; Dedicated logic registers                     ; 12    ;
;                                               ;       ;
; Estimated ALUTs Unavailable                   ; 4     ;
;                                               ;       ;
; Total combinational functions                 ; 11    ;
; Combinational ALUT usage by number of inputs  ;       ;
;     -- 7 input functions                      ; 1     ;
;     -- 6 input functions                      ; 1     ;
;     -- 5 input functions                      ; 3     ;
;     -- 4 input functions                      ; 2     ;
;     -- <=3 input functions                    ; 4     ;
;                                               ;       ;
; Combinational ALUTs by mode                   ;       ;
;     -- normal mode                            ; 10    ;
;     -- extended LUT mode                      ; 1     ;
;     -- arithmetic mode                        ; 0     ;
;     -- shared arithmetic mode                 ; 0     ;
;                                               ;       ;
; Estimated ALUT/register pairs used            ; 15    ;
;                                               ;       ;
; Total registers                               ; 12    ;
;     -- Dedicated logic registers              ; 12    ;
;     -- I/O registers                          ; 0     ;
;                                               ;       ;
; Estimated ALMs:  partially or completely used ; 8     ;
;                                               ;       ;
; I/O pins                                      ; 4     ;
; Maximum fan-out node                          ; clk   ;
; Maximum fan-out                               ; 12    ;
; Total fan-out                                 ; 78    ;
; Average fan-out                               ; 2.89  ;
+-----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                           ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; |de_PL_MPSK                ; 11 (11)           ; 12 (12)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 4    ; 0            ; |de_PL_MPSK         ; work         ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 12    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 6     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 4:1                ; 2 bits    ; 4 ALUTs       ; 4 ALUTs              ; 0 ALUTs                ; Yes        ; |de_PL_MPSK|yyy[1]         ;
; 6:1                ; 3 bits    ; 12 ALUTs      ; 12 ALUTs             ; 0 ALUTs                ; Yes        ; |de_PL_MPSK|q[0]           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition
    Info: Processing started: Sun Mar 16 17:01:17 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off de_PL_MPSK -c de_PL_MPSK
Info: Found 2 design units, including 1 entities, in source file de_PL_MPSK.vhd
    Info: Found design unit 1: de_PL_MPSK-behav
    Info: Found entity 1: de_PL_MPSK
Info: Elaborating entity "de_PL_MPSK" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at de_PL_MPSK.vhd(40): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Implemented 18 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 1 output pins
    Info: Implemented 14 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Allocated 154 megabytes of memory during processing
    Info: Processing ended: Sun Mar 16 17:01:25 2008
    Info: Elapsed time: 00:00:08