de_pl_mpsk.map.summary

来自「QPSK的VHDL调制解调 FPGA设计思路思想」· SUMMARY 代码 · 共 16 行

Analysis & Synthesis Status : Successful - Sun Mar 16 17:01:25 2008
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Web Edition
Revision Name : de_PL_MPSK
Top-level Entity Name : de_PL_MPSK
Family : Stratix II
Logic utilization : N/A
    Combinational ALUTs : 11
    Dedicated logic registers : 12
Total registers : 12
Total pins : 4
Total virtual pins : 0
Total block memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0