de_pl_mpsk.fit.summary

QPSK的VHDL调制解调 FPGA设计思路思想

Fitter Status : Successful - Sun Mar 16 17:01:48 2008
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Web Edition
Revision Name : de_PL_MPSK
Top-level Entity Name : de_PL_MPSK
Family : Stratix II
Device : EP2S15F484C3
Timing Models : Final
Logic utilization : < 1 %
    Combinational ALUTs : 11 / 12,480 ( < 1 % )
    Dedicated logic registers : 12 / 12,480 ( < 1 % )
Total registers : 12
Total pins : 4 / 343 ( 1 % )
Total virtual pins : 0
Total block memory bits : 0 / 419,328 ( 0 % )
DSP block 9-bit elements : 0 / 96 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )