📄 tone.c
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/*
* Copyright 2003 by Spectrum Digital Incorporated.
* All rights reserved. Property of Spectrum Digital Incorporated.
*/
/*
* ======== tone.c ========
*
* This example uses the AIC23 codec module of the 5502 EVM Board Support
* Library to generate a 1KHz sine wave on the audio outputs for 5 seconds.
* The sine wave data is pre-calculated in an array called sinetable. The
* codec operates at 48KHz by default. Since the sine wave table has 48
* entries per period, each pass through the inner loop takes 1 millisecond.
* 5000 passes through the inner loop takes 5 seconds.
*
* Please see the 5502 EVM help file under Software/Examples for more
* detailed information.
*/
/*
* DSP/BIOS is configured using the DSP/BIOS configuration tool. Settings
* for this example are stored in a configuration file called tone.cdb. At
* compile time, Code Composer will auto-generate DSP/BIOS related files
* based on these settings. A header file called tonecfg.h contains the
* results of the autogeneration and must be included for proper operation.
* The name of the file is taken from tone.cdb and adding cfg.h.
*/
/*
* The 5502 EVM Board Support Library is divided into several modules, each
* of which has its own include file. The file evm5502.h must be included
* in every program that uses the BSL. This example also includes
* evm5502_aic23.h because it uses the AIC23 codec module.
*/
#include "stdio.h"
#include "tonecfg.h"
#include "evm5502.h"
#include "evm5502_aic23.h"
#include "evm5502_led.h"
#include "evm5502_dip.h"
#include <csl_irq.h>
#include <csl_dma.h>
#include <csl_mcbsp.h>
#include <csl.h>
#include <log.h>
/* Length of sine wave table */
#define SINE_TABLE_SIZE 48
#define BUFFSIZE 96
/* Handles */
DMA_Handle hDmaRcv;
/* Function prototypes */
void initIrq(void);
void initDma(void);
// void copyData(Int16 *inbuf, Int16 *outbuf, Int16 length);
// void processBuffer(void);
// void blinkLED(void);
// void blinkLED0(void);
// void load(void);
// void powerDown(void);
// void dmaHwi(void);
/* Config Structures */
/* CSL config structure for DMAs */
static DMA_Config dmaCfgReceive = {
DMA_DMACSDP_RMK(
DMA_DMACSDP_DSTBEN_NOBURST,
DMA_DMACSDP_DSTPACK_OFF,
DMA_DMACSDP_DST_DARAMPORT1,
DMA_DMACSDP_SRCBEN_NOBURST,
DMA_DMACSDP_SRCPACK_OFF,
DMA_DMACSDP_SRC_PERIPH,
DMA_DMACSDP_DATATYPE_16BIT
), /* DMACDSP */
DMA_DMACCR_RMK(
DMA_DMACCR_DSTAMODE_POSTINC,
DMA_DMACCR_SRCAMODE_CONST,
DMA_DMACCR_ENDPROG_OFF,
DMA_DMACCR_WP_DEFAULT, /*Write Posting: Buffering Writes to Internal Memory
The DMA controller can take advantage of the write-posting capability of the
internal memory interface. When the write posting bit is set (WP = 1 in
DMACCR), the DMA controller can initiate a write and then can receive
acknowledgement from the internal memory interface before the data is
actually written to memory. The DMA controller is free to begin the next
operation while the internal memory interface assumes control of the posted
data.
When write posting is disabled (WP = 0), the DMA controller waits for the
internal memory interface to finish the memory access before continuing with
the next operation. It might be useful during debugging to disable write posting.*/
DMA_DMACCR_REPEAT_OFF,
DMA_DMACCR_AUTOINIT_OFF,
DMA_DMACCR_EN_STOP,
DMA_DMACCR_PRIO_HI,
DMA_DMACCR_FS_DISABLE,
DMA_DMACCR_SYNC_REVT1
), /* DMACCR */
DMA_DMACICR_RMK(
DMA_DMACICR_AERRIE_OFF,/*Address Error Condition
If the DMA controller accesses a reserved address in the I/O space of the DSP,
an address error signal is generated in the DMA controller. In response, activity
in the effected DMA channel stops. If the corresponding interrupt enable bit is
set (AERRIE = 1 in DMACICR), the DMA controller also sets the address error
status bit (AERR = 1 in DMACSR) and sends a channel interrupt request to
the CPU. The CPU can respond to the interrupt request or ignore the interrupt
request.
Before the next DMA transfer is initiated, the CPU must clear the address error
condition by making EN = 0 in DMACCR.*/
DMA_DMACICR_BLOCKIE_OFF,
DMA_DMACICR_LASTIE_OFF,
DMA_DMACICR_FRAMEIE_ON,
DMA_DMACICR_FIRSTHALFIE_OFF,
DMA_DMACICR_DROPIE_OFF,
DMA_DMACICR_TIMEOUTIE_OFF
), /* DMACICR */
(DMA_AdrPtr)((Uint32)(_MCBSP_DRR11_ADDR<<1)), /* DMACSSAL */
0, /* DMACSSAU */
NULL, /* DMACDSAL, to be loaded by submit */
0, /* DMACDSAU */
BUFFSIZE, /* DMACEN */
1, /* DMACFN */
0, /* DMACFI */
0 /* DMACEI */
};
Int16 gBufferRcvPing[BUFFSIZE]; // Receive PING buffer
#pragma DATA_SECTION (gBufferRcvPong, "buffer_sect");
Int16 gBufferRcvPong[BUFFSIZE]; // Receive PONG buffer
/*
* initDma() - Initialize the DMA controller.
*/
void initDma(void)
{
volatile Int16 i;
/* Set transmit and receive buffer addresses in config structures */
dmaCfgReceive.dmacdsal = (DMA_AdrPtr)(((Uint32)(&gBufferRcvPing) << 1) & 0xFFFF);
dmaCfgReceive.dmacdsau = (Uint16)((Uint32)(&gBufferRcvPing) >> 15);
/* Open DMA channels */
hDmaRcv = DMA_open(DMA_CHA4, DMA_OPEN_RESET);
/* Configure DMA channels */
DMA_config(hDmaRcv, &dmaCfgReceive);
/* Clear the DMA status registers to receive new interrupts */
i = DMA_RGETH(hDmaRcv, DMACSR);
DMA_RSET(DMAGCR, 0x0);
/* Clear any garbage from the codec data port */
if (MCBSP_rrdy(EVM5502_AIC23_DATAHANDLE))
MCBSP_read16(EVM5502_AIC23_DATAHANDLE);
// Start the DMA
DMA_start(hDmaRcv);
}
Uint16 eventIdRcv;
void initIrq(void)
{
// Get Event ID associated with DMA channel interrupt. Event IDs are a
// CSL abstraction that lets code describe a logical event that gets
// mapped to a real physical event at run time. This helps to improve
// code portability.
eventIdRcv = DMA_getEventId(hDmaRcv);
// Clear any pending receive channel interrupts (IFR)
IRQ_clear(eventIdRcv);
// Enable receive DMA interrupt (IMR)
IRQ_enable(eventIdRcv);
// Make sure global interrupts are enabled
IRQ_globalEnable();
}
extern LOG_Obj trace;
/* Codec configuration settings */
EVM5502_AIC23_Config config = { \
0x001a, /* 0 EVM5502_AIC23_LEFTINVOL Left line input channel volume */ \
0x001a, /* 1 EVM5502_AIC23_RIGHTINVOL Right line input channel volume */\
0x01c0, /* 2 EVM5502_AIC23_LEFTHPVOL Left channel headphone volume */ \
0x01c0, /* 3 EVM5502_AIC23_RIGHTHPVOL Right channel headphone volume */ \
0x0011, /* 4 EVM5502_AIC23_ANAPATH Analog audio path control */ \
0x0000, /* 5 EVM5502_AIC23_DIGPATH Digital audio path control */ \
0x0000, /* 6 EVM5502_AIC23_POWERDOWN Power down control */ \
0x0043, /* 7 EVM5502_AIC23_DIGIF Digital audio interface format */ \
0x0023, /* 8 EVM5502_AIC23_SAMPLERATE Sample rate control */ \
0x0001 /* 9 EVM5502_AIC23_DIGACT Digital interface activation */ \
};
/* The eighth register of CODEC determine the Codec sample rate
* Refrence the following table:
* Sample Rate REG VALUE
* ---------------------------------------------
* 96KHz 0X001D/0X009D
* 48KHz 0X0001/0X0081
* 44.1KHz 0X0023/0X00A3
* 32KHz 0X0019/0X0099
* 24KHz 0X0041/0X00C1
* 16KHz 0X0059/0X00D9
* 8KHz 0X000D/0X008D
* ----------------------------------------------
*/
// Pre-generated sine wave data, 16-bit signed samples
Int16 sinetable[SINE_TABLE_SIZE] = {
0x0000, 0x10b4, 0x2120, 0x30fb, 0x3fff, 0x4dea, 0x5a81, 0x658b,
0x6ed8, 0x763f, 0x7ba1, 0x7ee5, 0x7ffd, 0x7ee5, 0x7ba1, 0x76ef,
0x6ed8, 0x658b, 0x5a81, 0x4dea, 0x3fff, 0x30fb, 0x2120, 0x10b4,
0x0000, 0xef4c, 0xdee0, 0xcf06, 0xc002, 0xb216, 0xa57f, 0x9a75,
0x9128, 0x89c1, 0x845f, 0x811b, 0x8002, 0x811b, 0x845f, 0x89c1,
0x9128, 0x9a76, 0xa57f, 0xb216, 0xc002, 0xcf06, 0xdee0, 0xef4c
};
/**/
/*
* main() - Main code routine, initializes BSL and generates tone
*/
void main()
{
EVM5502_AIC23_CodecHandle hCodec;
Int16 y,i,j,hundun;
Int16 *data;
double x,xishu;
Uint16 dip0,dip1,dip3;
x=0.00265741465465;
xishu=3.8945687457554;
/* Initialize the board support library, must be called first */
EVM5502_init();
EVM5502_LED_init();
EVM5502_DIP_init();
/* Start the codec */
hCodec = EVM5502_AIC23_openCodec(0, &config);
printf("Hello world\n");
while (1)
{
/* Switch 0 pressed, turn LED #0 on and encode the information
Switch 1 pressed, turn LED #1 on and decode the information
switch 2 pressed, turn on the LED#3 to choose witch channel to sellect:0->aic23;1->sinetable
*/
if (EVM5502_DIP_get(3)){
EVM5502_LED_on(3);
dip3=1;
}
else {
EVM5502_LED_off(3);
dip3=0;
}
if (EVM5502_DIP_get(0)){
EVM5502_LED_on(0);
dip0=1;
if (EVM5502_DIP_get(1)){
EVM5502_LED_on(1);
dip1=1;
}
else{
EVM5502_LED_off(1);
dip1=0;
}
}
else{
EVM5502_LED_off(0);
EVM5502_LED_off(1);
dip0=0;
dip1=0;
}
for (j=0;j<SINE_TABLE_SIZE;j++){
if (dip3){
while (!EVM5502_AIC23_write16(hCodec, sinetable[j]));
y=sinetable[j];
}
else{
while(!EVM5502_AIC23_read16(hCodec,data));
y=*data;
while (!EVM5502_AIC23_write16(hCodec, y));
}
/* Check DIP switch to decide which sound is sellected and if it need encode and decode */
if (dip3) y=sinetable[j];
else{
while(!EVM5502_AIC23_read16(hCodec,data));
y=*data;
}
if (dip0 == 1){
/* calculate the hundun */
hundun=0;
for(i=1;i<=16;i++){
x=xishu*x*(1-x);
if (x>0.5)
hundun=(hundun<<1)+1;
else
hundun=(hundun<<1);
}
y=hundun^y;
if (dip1) y=hundun^y;
}
LOG_printf(&trace,"y=%d\n",y);
while (!EVM5502_AIC23_write16(hCodec, y));
}
}
/* Close the codec */
// EVM5502_AIC23_closeCodec(hCodec);
}
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