lpc_enet.h

NXP LPC系列AMR7的开发程序源码（LCD

/*************************************************************************
 *
 *    Used with ICCARM and AARM.
 *
 *    (c) Copyright IAR Systems 2006
 *
 *    File name   : lpc_enet.h
 *    Description : MAC/DMA Controller with DMA (ENET) driver include file
 *
 *    History :
 *    1. Data        : June 19, 2006
 *       Author      : Todor Atanasov
 *       Description : Created
 *
 *    $Revision: 7118 $
 **************************************************************************/
#include <includes.h>

#ifndef __LPC_ENET_H
#define __LPC_ENET_H


#define UIP_ETHADDR0    0x00  /**< The first octet of the Ethernet
				 address if UIP_FIXEDETHADDR is
				 1. \hideinitializer */
#define UIP_ETHADDR1    0xFF  /**< The second octet of the Ethernet
				 address if UIP_FIXEDETHADDR is
				 1. \hideinitializer */
#define UIP_ETHADDR2    0xFF  /**< The third octet of the Ethernet
				 address if UIP_FIXEDETHADDR is
				 1. \hideinitializer */
#define UIP_ETHADDR3    0xFF  /**< The fourth octet of the Ethernet
				 address if UIP_FIXEDETHADDR is
				 1. \hideinitializer */
#define UIP_ETHADDR4    0xFF  /**< The fifth octet of the Ethernet
				 address if UIP_FIXEDETHADDR is
				 1. \hideinitializer */
#define UIP_ETHADDR5    0xFF  /**< The sixth octet of the Ethernet
				 address if UIP_FIXEDETHADDR is
				 1. \hideinitializer */

#define EMAC_MAX_PACKET_SIZE 1520
#define ENET_OK  (1)
#define ENET_NOK (0)

// MMI PHY Address
#define MII_PHY_ADDR        0x5

// Description of common PHY registers STE100
#define MAC_MII_REG_XCR     0x00000000  // XCVR Control Register
#define MAC_MII_REG_XSR     0x00000001  // XCVR Status Register
#define MAC_MII_REG_PID1    0x00000002  // PHY Identifier 1
#define MAC_MII_REG_PID2    0x00000003  // PHY Identifier 2
#define MAC_MII_REG_ANA     0x00000004  // Auto-Negotiation Advertisement Register
#define MAC_MII_REG_ANLPA   0x00000005  // Auto-Negotiation Link Partner Ability Register
#define MAC_MII_REG_ANE     0x00000006  // Auto-Negotiation Expansion Register
#define MAC_MII_REG_XCIIS   0x00000011  // XCVR Configuration Information and Interrupt Status Register
#define MAC_MII_REG_XIE     0x00000012  // XCVR Interrupt Enable Register
#define MAC_MII_REG_100CTR  0x00000013  // 100Base-TX PHY Control/Status Register
#define MAC_MII_REG_XMC     0x00000014  // XCVR Mode Control Register

// ENET_OperatingMode
#define PHY_OPR_MODE        0x2100      //  Set the full-duplex mode at 100 Mb/s

typedef union _EnetRxCR_t
{
  Int32U Data;
  struct {
    Int32U  DMA_XFERCOUNT :12;
    Int32U  CONT_EN       : 1;
    Int32U                : 1;
    Int32U  NXT_EN        : 1;
    Int32U  DLY_EN        : 1;
    Int32U                : 1;
    Int32U  ENTRY_TRIG    : 5;
    Int32U  ADDR_WRAP     :10;
  };
} EnetRxCR_t, * pEnetRxCR_t;

typedef union _EnetRxSR_t
{
  Int32U Data;
  struct {
    Int32U  FrameLength     :11;
    Int32U                  : 1;
    Int32U  Overlength      : 1;
    Int32U  FalseCarrier    : 1;
    Int32U  WatchdogTO      : 1;
    Int32U  RuntFrame       : 1;
    Int32U  Valid           : 1;
    Int32U  LateCollision   : 1;
    Int32U  FrameType       : 1;
    Int32U  MIIError        : 1;
    Int32U  ExtraBits       : 1;
    Int32U  CRCError        : 1;
    Int32U  OneLevelVLAN    : 1;
    Int32U  TwoLevelVLAN    : 1;
    Int32U  LengthError     : 1;
    Int32U  ControlFrame    : 1;
    Int32U  UnsupportedFrame: 1;
    Int32U  MulticastFrame  : 1;
    Int32U  BroadcastFrame  : 1;
    Int32U  FilteringFail   : 1;
    Int32U  PacketFilter    : 1;
    Int32U  FrameAbort      : 1;
  };
} EnetRxSR_t, * pEnetRxSR_t;

typedef union _EnetTxSR_t
{
  Int32U Data;
  struct {
    Int32U  FrameAborted    : 1;
    Int32U                  : 1;
    Int32U  NoCarrier       : 1;
    Int32U  LossOfCarrier   : 1;
    Int32U  ExcessiveDef    : 1;
    Int32U  LateCollision   : 1;
    Int32U  ExcessiveColl   : 1;
    Int32U  UnderRun        : 1;
    Int32U  Deferred        : 1;
    Int32U  LateCollisionObs: 1;
    Int32U  CollisionCount  : 4;
    Int32U                  : 2;
    Int32U  Valid           : 1;
    Int32U                  : 1;
    Int32U  ByteCounter     :13;
    Int32U  PacketRetry     : 1;
  };
} EnetTxSR_t, * pEnetTxSR_t;

typedef union _EnetDmaDesc_t
{
  Int32U Data[4];
  // Rx DMA descriptor
  struct
  {
    EnetRxCR_t              EnetRxCR;
    pInt32U                 pBuffer;
    union _EnetDmaDesc_t *  EnetDmaNextDesc;
    EnetRxSR_t              EnetRxSR;
  } Rx;
  // Tx DMA descriptor
  struct
  {
    EnetRxCR_t              EnetTxCR;
    pInt32U                 pBuffer;
    union _EnetDmaDesc_t *  EnetDmaNextDesc;
    EnetTxSR_t              EnetTxSR;
  } Tx;

} EnetDmaDesc_t, * pEnetDmaDesc_t;

/*************************************************************************
 * Function Name:
 * Parameters: None
 *
 * Return: None
 *
 * Description: Init  MAC/DMA Controller
 *
 *************************************************************************/
void tapdev_init(void);

/*************************************************************************
 * Function Name: tapdev_read
 * Parameters:
 * Return:
 *
 * Description: Read data for MAC/DMA Controller
 *
 *************************************************************************/
Int32U tapdev_read(void * pPacket);

/*************************************************************************
 * Function Name: tapdev_send
 * Parameters:
 * Return:
 *
 * Description: Send data to MAC/DMA Controller
 *
 *************************************************************************/
void tapdev_send (void *pPacket, Int32U size);

/*************************************************************************
 * Function Name: ENET_MIIWriteRegister
 * Parameters: Int8U DevId, Int8U RegAddr, Int32U Value
 * Return: none
 *
 * Description: Writes a value on the PHY registers
 *
 *************************************************************************/
static void ENET_MIIWriteRegister (Int8U DevId, Int8U RegAddr, Int32U Value);

/*************************************************************************
 * Function Name: ENET_MIIReadRegister
 * Parameters: Int8U DevId, Int8U RegAddr, Int32U Value
 * Return: Int32U
 *
 * Description: Read a value from the PHY registers
 *
 *************************************************************************/
static Int32U ENET_MIIReadRegister (Int8U DevId, Int8U RegAddr);

#endif // __LPC_ENET_H