lpc29xx.h

来自「NXP LPC系列AMR7的开发程序源码（LCD」· C头文件 代码 · 共 903 行 · 第 1/5 页

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#define U0THR                (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
#define U0DLL                (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
#define U0DLM                (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))
#define U0IER                (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))
#define U0IIR                (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))
#define U0FCR                (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))
#define U0LCR                (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x0C))
#define U0LSR                (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x14))

#define UART1_BASE_ADDR      0xE0046000
#define U1RBR                (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
#define U1THR                (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
#define U1DLL                (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
#define U1DLM                (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))
#define U1IER                (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))
#define U1IIR                (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))
#define U1FCR                (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))
#define U1LCR                (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x0C))
#define U1LSR                (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x14))

/* SPIx register base */
#define SPI0_BASE_ADDR       0xE0047000
#define SPI0_CONFIG          (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x000))
#define SPI0_SLV_ENABLE      (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x004))
#define SPI0_TX_FIFO_FLUSH   (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x008))
#define SPI0_FIFO_DATA       (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00C))
#define SPI0_FIFO_POP        (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x010))
#define SPI0_RD_FIFO_RDMODE  (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x014))
#define SPI0_STAT            (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x01C))
#define SPI0_SLV0_SET1       (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x024))
#define SPI0_SLV0_SET2       (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x028))
#define SPI0_SLV1_SET1       (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x02C))
#define SPI0_SLV1_SET2       (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x030))
#define SPI0_SLV2_SET1       (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x034))
#define SPI0_SLV2_SET2       (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x038))
#define SPI0_SLV3_SET1       (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x03C))
#define SPI0_SLV3_SET2       (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x040))

#define SPI0_INT_THRESHOLD   (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0xFD4))
#define SPI0_INT_CLR_ENABLE  (*(volatile unsigned long *)(SPi0_BASE_ADDR + 0xFD8))
#define SPI0_INT_SET_ENABLE  (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0xFDC))
#define SPI0_INT_STATUS      (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0xFE0))
#define SPI0_INT_ENABLE      (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0xFE4))
#define SPI0_INT_CLR_STATUS  (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0xFE8))
#define SPI0_INT_SET_STATUS  (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0xFEC))

#define SPI1_BASE_ADDR       0xE0048000
#define SPI1_CONFIG          (*(volatile unsigned long *)(SPI1_BASE_ADDR + 0x000))
#define SPI1_SLV_ENABLE      (*(volatile unsigned long *)(SPI1_BASE_ADDR + 0x004))
#define SPI1_TX_FIFO_FLUSH   (*(volatile unsigned long *)(SPI1_BASE_ADDR + 0x008))
#define SPI1_FIFO_DATA       (*(volatile unsigned long *)(SPI1_BASE_ADDR + 0x00C))
#define SPI1_FIFO_POP        (*(volatile unsigned long *)(SPI1_BASE_ADDR + 0x010))
#define SPI1_RD_FIFO_RDMODE  (*(volatile unsigned long *)(SPI1_BASE_ADDR + 0x014))
#define SPI1_STAT            (*(volatile unsigned long *)(SPI1_BASE_ADDR + 0x01C))
#define SPI1_SLV0_SET1       (*(volatile unsigned long *)(SPI1_BASE_ADDR + 0x024))
#define SPI1_SLV0_SET2       (*(volatile unsigned long *)(SPI1_BASE_ADDR + 0x028))
#define SPI1_SLV1_SET1       (*(volatile unsigned long *)(SPI1_BASE_ADDR + 0x02C))
#define SPI1_SLV1_SET2       (*(volatile unsigned long *)(SPI1_BASE_ADDR + 0x030))
#define SPI1_SLV2_SET1       (*(volatile unsigned long *)(SPI1_BASE_ADDR + 0x034))
#define SPI1_SLV2_SET2       (*(volatile unsigned long *)(SPI1_BASE_ADDR + 0x038))
#define SPI1_SLV3_SET1       (*(volatile unsigned long *)(SPI1_BASE_ADDR + 0x03C))
#define SPI1_SLV3_SET2       (*(volatile unsigned long *)(SPI1_BASE_ADDR + 0x040))

#define SPI1_INT_THRESHOLD   (*(volatile unsigned long *)(SPI1_BASE_ADDR + 0xFD4))
#define SPI1_INT_CLR_ENABLE  (*(volatile unsigned long *)(SPI1_BASE_ADDR + 0xFD8))
#define SPI1_INT_SET_ENABLE  (*(volatile unsigned long *)(SPI1_BASE_ADDR + 0xFDC))
#define SPI1_INT_STATUS      (*(volatile unsigned long *)(SPI1_BASE_ADDR + 0xFE0))
#define SPI1_INT_ENABLE      (*(volatile unsigned long *)(SPI1_BASE_ADDR + 0xFE4))
#define SPI1_INT_CLR_STATUS  (*(volatile unsigned long *)(SPI1_BASE_ADDR + 0xFE8))
#define SPI1_INT_SET_STATUS  (*(volatile unsigned long *)(SPI1_BASE_ADDR + 0xFEC))

#define SPI2_BASE_ADDR       0xE0049000
#define SPI2_CONFIG          (*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x000))
#define SPI2_SLV_ENABLE      (*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x004))
#define SPI2_TX_FIFO_FLUSH   (*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x008))
#define SPI2_FIFO_DATA       (*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x00C))
#define SPI2_FIFO_POP        (*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x010))
#define SPI2_RD_FIFO_RDMODE  (*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x014))
#define SPI2_STAT            (*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x01C))
#define SPI2_SLV0_SET1       (*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x024))
#define SPI2_SLV0_SET2       (*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x028))
#define SPI2_SLV1_SET1       (*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x02C))
#define SPI2_SLV1_SET2       (*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x030))
#define SPI2_SLV2_SET1       (*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x034))
#define SPI2_SLV2_SET2       (*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x038))
#define SPI2_SLV3_SET1       (*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x03C))
#define SPI2_SLV3_SET2       (*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x040))

#define SPI2_INT_THRESHOLD   (*(volatile unsigned long *)(SPI2_BASE_ADDR + 0xFD4))
#define SPI2_INT_CLR_ENABLE  (*(volatile unsigned long *)(SPI2_BASE_ADDR + 0xFD8))
#define SPI2_INT_SET_ENABLE  (*(volatile unsigned long *)(SPI2_BASE_ADDR + 0xFDC))
#define SPI2_INT_STATUS      (*(volatile unsigned long *)(SPI2_BASE_ADDR + 0xFE0))
#define SPI2_INT_ENABLE      (*(volatile unsigned long *)(SPI2_BASE_ADDR + 0xFE4))
#define SPI2_INT_CLR_STATUS  (*(volatile unsigned long *)(SPI2_BASE_ADDR + 0xFE8))
#define SPI2_INT_SET_STATUS  (*(volatile unsigned long *)(SPI2_BASE_ADDR + 0xFEC))

/* GPIO register controller base address */
#define GPIO0_BASE_ADDR      0xE004A000
#define GPIO0_PINS           (*(volatile unsigned long *)(GPIO0_BASE_ADDR + 0x000))
#define GPIO0_OR             (*(volatile unsigned long *)(GPIO0_BASE_ADDR + 0x004))
#define GPIO0_DR             (*(volatile unsigned long *)(GPIO0_BASE_ADDR + 0x008))

#define GPIO1_BASE_ADDR      0xE004B000
#define GPIO1_PINS           (*(volatile unsigned long *)(GPIO1_BASE_ADDR + 0x000))
#define GPIO1_OR             (*(volatile unsigned long *)(GPIO1_BASE_ADDR + 0x004))
#define GPIO1_DR             (*(volatile unsigned long *)(GPIO1_BASE_ADDR + 0x008))

#define GPIO2_BASE_ADDR      0xE004C000
#define GPIO2_PINS           (*(volatile unsigned long *)(GPIO2_BASE_ADDR + 0x000))
#define GPIO2_OR             (*(volatile unsigned long *)(GPIO2_BASE_ADDR + 0x004))
#define GPIO2_DR             (*(volatile unsigned long *)(GPIO2_BASE_ADDR + 0x008))

#define GPIO3_BASE_ADDR      0xE004D000
#define GPIO3_PINS           (*(volatile unsigned long *)(GPIO3_BASE_ADDR + 0x000))
#define GPIO3_OR             (*(volatile unsigned long *)(GPIO3_BASE_ADDR + 0x004))
#define GPIO3_DR             (*(volatile unsigned long *)(GPIO3_BASE_ADDR + 0x008))

/* CAN related registers */
#define CAN0_BASE_ADDR		0xE0080000
#define CAN0MOD 	(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x00))  	
#define CAN0CMR 	(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x04))  	
#define CAN0GSR 	(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x08))  	
#define CAN0ICR 	(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x0C))  	
#define CAN0IER 	(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x10))
#define CAN0BTR 	(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x14))  	
#define CAN0EWL 	(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x18))  	
#define CAN0SR 		(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x1C))  	
#define CAN0RFS 	(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x20))  	
#define CAN0RID 	(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x24))
#define CAN0RDA 	(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x28))  	
#define CAN0RDB 	(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x2C))
  	
#define CAN0TFI1 	(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x30))  	
#define CAN0TID1 	(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x34))  	
#define CAN0TDA1 	(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x38))
#define CAN0TDB1 	(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x3C))  	
#define CAN0TFI2 	(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x40))  	
#define CAN0TID2 	(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x44))  	
#define CAN0TDA2 	(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x48))  	
#define CAN0TDB2 	(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x4C))
#define CAN0TFI3 	(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x50))  	
#define CAN0TID3 	(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x54))  	
#define CAN0TDA3 	(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x58))  	
#define CAN0TDB3 	(*(volatile unsigned long *)(CAN0_BASE_ADDR + 0x5C))

#define CAN1_BASE_ADDR		0xE0081000
#define CAN1MOD 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00))  	
#define CAN1CMR 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04))  	
#define CAN1GSR 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08))  	
#define CAN1ICR 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C))  	
#define CAN1IER 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10))
#define CAN1BTR 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14))  	
#define CAN1EWL 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18))  	
#define CAN1SR 		(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C))  	
#define CAN1RFS 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20))  	
#define CAN1RID 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24))
#define CAN1RDA 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28))  	
#define CAN1RDB 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C))
  	
#define CAN1TFI1 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30))  	
#define CAN1TID1 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34))  	
#define CAN1TDA1 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38))
#define CAN1TDB1 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C))  	
#define CAN1TFI2 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40))  	
#define CAN1TID2 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44))  	
#define CAN1TDA2 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48))  	
#define CAN1TDB2 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C))
#define CAN1TFI3 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50))  	
#define CAN1TID3 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54))  	
#define CAN1TDA3 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58))  	
#define CAN1TDB3 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C))

#define CAN_AFR_BASE_ADDR			0xE0086000

/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
#define CAN_ACCEPT_BASE_ADDR		0xE0087000
#define CAN_AFMR		(*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00))  	
#define CAN_SFF_SA 		(*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04))  	
#define CAN_SFF_GRP_SA 	(*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08))
#define CAN_EFF_SA 		(*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C))
#define CAN_EFF_GRP_SA 	(*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10))
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lpc29xx.h - 源码说明

本页面展示了「NXP LPC系列AMR7的开发程序源码（LCD」中的 lpc29xx.h 源码文件，采用 C头文件 编程语言编写，共 903 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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