lpc29xx.h

来自「NXP LPC系列AMR7的开发程序源码（LCD」· C头文件 代码 · 共 903 行 · 第 1/5 页

#define SFSP1_19             (*(volatile unsigned long *)(SFSP1_BASE + 0x4C))
#define SFSP1_20             (*(volatile unsigned long *)(SFSP1_BASE + 0x50))
#define SFSP1_21             (*(volatile unsigned long *)(SFSP1_BASE + 0x54))
#define SFSP1_22             (*(volatile unsigned long *)(SFSP1_BASE + 0x58))
#define SFSP1_23             (*(volatile unsigned long *)(SFSP1_BASE + 0x5C))
#define SFSP1_24             (*(volatile unsigned long *)(SFSP1_BASE + 0x60))
#define SFSP1_25             (*(volatile unsigned long *)(SFSP1_BASE + 0x64))
#define SFSP1_26             (*(volatile unsigned long *)(SFSP1_BASE + 0x68))
#define SFSP1_27             (*(volatile unsigned long *)(SFSP1_BASE + 0x6C))
#define SFSP1_28             (*(volatile unsigned long *)(SFSP1_BASE + 0x70))
#define SFSP1_29             (*(volatile unsigned long *)(SFSP1_BASE + 0x74))
#define SFSP1_30             (*(volatile unsigned long *)(SFSP1_BASE + 0x78))
#define SFSP1_31             (*(volatile unsigned long *)(SFSP1_BASE + 0x7C))

#define SFSP2_BASE           (SCU_BASE_ADDR + 0x200)
#define SFSP2_0              (*(volatile unsigned long *)(SFSP2_BASE + 0x00))
#define SFSP2_1              (*(volatile unsigned long *)(SFSP2_BASE + 0x04))
#define SFSP2_2              (*(volatile unsigned long *)(SFSP2_BASE + 0x08))
#define SFSP2_3              (*(volatile unsigned long *)(SFSP2_BASE + 0x0C))
#define SFSP2_4              (*(volatile unsigned long *)(SFSP2_BASE + 0x10))
#define SFSP2_5              (*(volatile unsigned long *)(SFSP2_BASE + 0x14))
#define SFSP2_6              (*(volatile unsigned long *)(SFSP2_BASE + 0x18))
#define SFSP2_7              (*(volatile unsigned long *)(SFSP2_BASE + 0x1C))
#define SFSP2_8              (*(volatile unsigned long *)(SFSP2_BASE + 0x20))
#define SFSP2_9              (*(volatile unsigned long *)(SFSP2_BASE + 0x24))
#define SFSP2_10             (*(volatile unsigned long *)(SFSP2_BASE + 0x28))
#define SFSP2_11             (*(volatile unsigned long *)(SFSP2_BASE + 0x2C))
#define SFSP2_12             (*(volatile unsigned long *)(SFSP2_BASE + 0x30))
#define SFSP2_13             (*(volatile unsigned long *)(SFSP2_BASE + 0x34))
#define SFSP2_14             (*(volatile unsigned long *)(SFSP2_BASE + 0x38))
#define SFSP2_15             (*(volatile unsigned long *)(SFSP2_BASE + 0x3C))
#define SFSP2_16             (*(volatile unsigned long *)(SFSP2_BASE + 0x40))
#define SFSP2_17             (*(volatile unsigned long *)(SFSP2_BASE + 0x44))
#define SFSP2_18             (*(volatile unsigned long *)(SFSP2_BASE + 0x48))
#define SFSP2_19             (*(volatile unsigned long *)(SFSP2_BASE + 0x4C))
#define SFSP2_20             (*(volatile unsigned long *)(SFSP2_BASE + 0x50))
#define SFSP2_21             (*(volatile unsigned long *)(SFSP2_BASE + 0x54))
#define SFSP2_22             (*(volatile unsigned long *)(SFSP2_BASE + 0x58))
#define SFSP2_23             (*(volatile unsigned long *)(SFSP2_BASE + 0x5C))
#define SFSP2_24             (*(volatile unsigned long *)(SFSP2_BASE + 0x60))
#define SFSP2_25             (*(volatile unsigned long *)(SFSP2_BASE + 0x64))
#define SFSP2_26             (*(volatile unsigned long *)(SFSP2_BASE + 0x68))
#define SFSP2_27             (*(volatile unsigned long *)(SFSP2_BASE + 0x6C))

#define SFSP3_BASE           (SCU_BASE_ADDR + 0x300)
#define SFSP3_0              (*(volatile unsigned long *)(SFSP3_BASE + 0x00))
#define SFSP3_1              (*(volatile unsigned long *)(SFSP3_BASE + 0x04))
#define SFSP3_2              (*(volatile unsigned long *)(SFSP3_BASE + 0x08))
#define SFSP3_3              (*(volatile unsigned long *)(SFSP3_BASE + 0x0C))
#define SFSP3_4              (*(volatile unsigned long *)(SFSP3_BASE + 0x10))
#define SFSP3_5              (*(volatile unsigned long *)(SFSP3_BASE + 0x14))
#define SFSP3_6              (*(volatile unsigned long *)(SFSP3_BASE + 0x18))
#define SFSP3_7              (*(volatile unsigned long *)(SFSP3_BASE + 0x1C))
#define SFSP3_8              (*(volatile unsigned long *)(SFSP3_BASE + 0x20))
#define SFSP3_9              (*(volatile unsigned long *)(SFSP3_BASE + 0x24))
#define SFSP3_10             (*(volatile unsigned long *)(SFSP3_BASE + 0x28))
#define SFSP3_11             (*(volatile unsigned long *)(SFSP3_BASE + 0x2C))
#define SFSP3_12             (*(volatile unsigned long *)(SFSP3_BASE + 0x30))
#define SFSP3_13             (*(volatile unsigned long *)(SFSP3_BASE + 0x34))
#define SFSP3_14             (*(volatile unsigned long *)(SFSP3_BASE + 0x38))
#define SFSP3_15             (*(volatile unsigned long *)(SFSP3_BASE + 0x3C))

/* Event Router register base */
#define ER_BASE_ADDR      0xE0002000
#define ER_PEND              (*(volatile unsigned long *)(ER_BASE_ADDR + 0xC00))
#define ER_INT_CLR           (*(volatile unsigned long *)(ER_BASE_ADDR + 0xC20))
#define ER_INT_SET           (*(volatile unsigned long *)(ER_BASE_ADDR + 0xC40))
#define ER_MASK              (*(volatile unsigned long *)(ER_BASE_ADDR + 0xC60))
#define ER_MASK_CLR          (*(volatile unsigned long *)(ER_BASE_ADDR + 0xC80))
#define ER_MASK_SET          (*(volatile unsigned long *)(ER_BASE_ADDR + 0xCA0))
#define ER_APR               (*(volatile unsigned long *)(ER_BASE_ADDR + 0xCC0))
#define ER_ATR               (*(volatile unsigned long *)(ER_BASE_ADDR + 0xCE0))
#define ER_RSR               (*(volatile unsigned long *)(ER_BASE_ADDR + 0xD20))

/* Watchdog register base */
#define WDT_BASE_ADDR      0xE0040000
#define WDT_WTCR             (*(volatile unsigned long *)(WDT_BASE_ADDR + 0x000))
#define WDT_TC               (*(volatile unsigned long *)(WDT_BASE_ADDR + 0x004))
#define WDT_PR               (*(volatile unsigned long *)(WDT_BASE_ADDR + 0x008))
#define WDT_WD_KEY           (*(volatile unsigned long *)(WDT_BASE_ADDR + 0x038))
#define WDT_TIMEOUT          (*(volatile unsigned long *)(WDT_BASE_ADDR + 0x03C))
#define WDT_DEBUG            (*(volatile unsigned long *)(WDT_BASE_ADDR + 0x040))
#define WDT_INT_CLR_ENABLE   (*(volatile unsigned long *)(WDT_BASE_ADDR + 0xFD8))
#define WDT_INT_SET_ENABLE   (*(volatile unsigned long *)(WDT_BASE_ADDR + 0xFDC))
#define WDT_INT_STATUS       (*(volatile unsigned long *)(WDT_BASE_ADDR + 0xFE0))
#define WDT_INT_ENABLE       (*(volatile unsigned long *)(WDT_BASE_ADDR + 0xFE4))
#define WDT_INT_CLR_STATUS   (*(volatile unsigned long *)(WDT_BASE_ADDR + 0xFE8))
#define WDT_INT_SET_STATUS   (*(volatile unsigned long *)(WDT_BASE_ADDR + 0xFEC))

/* Timer related reqiesters */
#define TMR0_BASE_ADDR       0xE0041000
#define TIM0_TCR             (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x000))
#define TIM0_TC              (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x004))
#define TIM0_PR              (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x008))
#define TIM0_MCR             (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00C))
#define TIM0_EMR             (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x010))
#define TIM0_MR0             (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x014))
#define TIM0_MR1             (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x018))
#define TIM0_MR2             (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x01C))
#define TIM0_MR3             (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x020))
#define TIM0_CCR             (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x024))
#define TIM0_CR0             (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x028))
#define TIM0_CR1             (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x02C))
#define TIM0_CR2             (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x030))
#define TIM0_CR3             (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x034))
#define TIM0_INT_CLR_ENABLE  (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0xFD8))
#define TIM0_INT_SET_ENABLE  (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0xFDC))
#define TIM0_INT_STATUS      (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0xFE0))
#define TIM0_INT_ENABLE      (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0xFE4))
#define TIM0_INT_CLR_STATUS  (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0xFE8))
#define TIM0_INT_SET_STATUS  (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0xFEC))

#define TMR1_BASE_ADDR       0xE0042000
#define TIM1_TCR             (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x000))
#define TIM1_TC              (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x004))
#define TIM1_PR              (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x008))
#define TIM1_MCR             (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00C))
#define TIM1_EMR             (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x010))
#define TIM1_MR0             (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x014))
#define TIM1_MR1             (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x018))
#define TIM1_MR2             (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x01C))
#define TIM1_MR3             (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x020))
#define TIM1_CCR             (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x024))
#define TIM1_CR0             (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x028))
#define TIM1_CR1             (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x02C))
#define TIM1_CR2             (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x030))
#define TIM1_CR3             (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x034))
#define TIM1_INT_CLR_ENABLE  (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0xFD8))
#define TIM1_INT_SET_ENABLE  (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0xFDC))
#define TIM1_INT_STATUS      (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0xFE0))
#define TIM1_INT_ENABLE      (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0xFE4))
#define TIM1_INT_CLR_STATUS  (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0xFE8))
#define TIM1_INT_SET_STATUS  (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0xFEC))

#define TMR2_BASE_ADDR       0xE0043000
#define TIM2_TCR             (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x000))
#define TIM2_TC              (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x004))
#define TIM2_PR              (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x008))
#define TIM2_MCR             (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00C))
#define TIM2_EMR             (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x010))
#define TIM2_MR0             (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x014))
#define TIM2_MR1             (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x018))
#define TIM2_MR2             (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x01C))
#define TIM2_MR3             (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x020))
#define TIM2_CCR             (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x024))
#define TIM2_CR0             (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x028))
#define TIM2_CR1             (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x02C))
#define TIM2_CR2             (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x030))
#define TIM2_CR3             (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x034))
#define TIM2_INT_CLR_ENABLE  (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0xFD8))
#define TIM2_INT_SET_ENABLE  (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0xFDC))
#define TIM2_INT_STATUS      (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0xFE0))
#define TIM2_INT_ENABLE      (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0xFE4))
#define TIM2_INT_CLR_STATUS  (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0xFE8))
#define TIM2_INT_SET_STATUS  (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0xFEC))

#define TMR3_BASE_ADDR       0xE0044000
#define TIM3_TCR             (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x000))
#define TIM3_TC              (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x004))
#define TIM3_PR              (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x008))
#define TIM3_MCR             (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00C))
#define TIM3_EMR             (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x010))
#define TIM3_MR0             (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x014))
#define TIM3_MR1             (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x018))
#define TIM3_MR2             (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x01C))
#define TIM3_MR3             (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x020))
#define TIM3_CCR             (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x024))
#define TIM3_CR0             (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x028))
#define TIM3_CR1             (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x02C))
#define TIM3_CR2             (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x030))
#define TIM3_CR3             (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x034))
#define TIM3_INT_CLR_ENABLE  (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0xFD8))
#define TIM3_INT_SET_ENABLE  (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0xFDC))
#define TIM3_INT_STATUS      (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0xFE0))
#define TIM3_INT_ENABLE      (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0xFE4))
#define TIM3_INT_CLR_STATUS  (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0xFE8))
#define TIM3_INT_SET_STATUS  (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0xFEC))

/* UART register base */
#define UART0_BASE_ADDR      0xE0045000
#define U0RBR                (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))