lpc29xx.h

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/*****************************************************************************
 *   lpc29xx.h:  Master Header file for NXP LPC29xx Family Microprocessors
 *
 *   Copyright(C) 2007, NXP Semiconductor
 *   All rights reserved.
 *
 *   History
 *   2007.09.01  ver 1.00    Prelimnary version, first Release
 *
******************************************************************************/
#ifndef __LPC29XX_H
#define __LPC29XX_H

/* Embedded flash memory controller */
#define FMC_BASE_ADDR        0x20200000
#define FCTR                 (*(volatile unsigned long *)(FMC_BASE_ADDR + 0x000))
#define   FS_LOADREQ         (1 << 15)
#define   FS_CACHECLR        (1 << 14)
#define   FS_CACHEBYP        (1 << 13)
#define   FS_PROGREQ         (1 << 12)
#define   FS_RLS             (1 << 11)
#define   FS_PDL             (1 << 10)
#define   FS_PD              (1 <<  9)
#define   FS_WPB             (1 <<  7)
#define   FS_ISS             (1 <<  6)
#define   FS_RLD             (1 <<  5)
#define   FS_DCR             (1 <<  4)
#define   FS_WEB             (1 <<  2)
#define   FS_WRE             (1 <<  1)
#define   FS_CS              (1 <<  0)
#define FPTR                 (*(volatile unsigned long *)(FMC_BASE_ADDR + 0x008))
#define FBWST                (*(volatile unsigned long *)(FMC_BASE_ADDR + 0x010))
#define   CACHE2EN           0x8000
#define   SPECALWAYS         0x4000
#define   WST4               4
#define FCRA                 (*(volatile unsigned long *)(FMC_BASE_ADDR + 0x01C))
#define FMSSTART             (*(volatile unsigned long *)(FMC_BASE_ADDR + 0x020))
#define FMSSTOP              (*(volatile unsigned long *)(FMC_BASE_ADDR + 0x024))
#define FMSW0                (*(volatile unsigned long *)(FMC_BASE_ADDR + 0x02C))
#define FMSW1                (*(volatile unsigned long *)(FMC_BASE_ADDR + 0x030))
#define FMSW2                (*(volatile unsigned long *)(FMC_BASE_ADDR + 0x034))
#define FMSW3                (*(volatile unsigned long *)(FMC_BASE_ADDR + 0x038))
#define FMC_INT_CLR_ENABLE   (*(volatile unsigned long *)(FMC_BASE_ADDR + 0xFD8))
#define FMC_INT_SET_ENABLE   (*(volatile unsigned long *)(FMC_BASE_ADDR + 0xFDC))
#define FMC_INT_STATUS       (*(volatile unsigned long *)(FMC_BASE_ADDR + 0xFE0))
#define FMC_INT_ENABLE       (*(volatile unsigned long *)(FMC_BASE_ADDR + 0xFE4))
#define FMC_INT_CLR_STATUS   (*(volatile unsigned long *)(FMC_BASE_ADDR + 0xFE8))
#define FMC_INT_SET_STATUS   (*(volatile unsigned long *)(FMC_BASE_ADDR + 0xFEC))

/* External static memory address */
#define ESMC_BASE_ADDR       0x40000000

/* External static memory controller */
#define SMC_BASE_ADDR        0x60000000
#define SMC_IDCYR0           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x000))
#define SMC_WST1R0           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x004))
#define SMC_WST2R0           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x008))
#define SMC_WSTOENR0         (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x00C))
#define SMC_WSTWENR0         (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x010))
#define SMC_CR0              (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x014))
#define SMC_SR0              (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x018))

#define SMC_IDCYR1           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x01C))
#define SMC_WST1R1           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x020))
#define SMC_WST2R1           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x024))
#define SMC_WSTOENR1         (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x028))
#define SMC_WSTWENR1         (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x02C))
#define SMC_CR1              (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x030))
#define SMC_SR1              (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x034))

#define SMC_IDCYR2           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x038))
#define SMC_WST1R2           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x03C))
#define SMC_WST2R2           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x040))
#define SMC_WSTOENR2         (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x044))
#define SMC_WSTWENR2         (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x048))
#define SMC_CR2              (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x04C))
#define SMC_SR2              (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x050))

#define SMC_IDCYR3           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x054))
#define SMC_WST1R3           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x058))
#define SMC_WST2R3           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x05C))
#define SMC_WSTOENR3         (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x060))
#define SMC_WSTWENR3         (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x064))
#define SMC_CR3              (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x068))
#define SMC_SR3              (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x06C))

#define SMC_IDCYR4           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x070))
#define SMC_WST1R4           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x074))
#define SMC_WST2R4           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x078))
#define SMC_WSTOENR4         (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x07C))
#define SMC_WSTWENR4         (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x080))
#define SMC_CR4              (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x084))
#define SMC_SR4              (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x088))

#define SMC_IDCYR5           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x08C))
#define SMC_WST1R5           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x090))
#define SMC_WST2R5           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x094))
#define SMC_WSTOENR5         (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x098))
#define SMC_WSTWENR5         (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x09C))
#define SMC_CR5              (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x0A0))
#define SMC_SR5              (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x0A4))

#define SMC_IDCYR6           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x0A8))
#define SMC_WST1R6           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x0AC))
#define SMC_WST2R6           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x0B0))
#define SMC_WSTOENR6         (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x0B4))
#define SMC_WSTWENR6         (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x0B8))
#define SMC_CR6              (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x0BC))
#define SMC_SR6              (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x0C0))

#define SMC_IDCYR7           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x0C4))
#define SMC_WST1R7           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x0C8))
#define SMC_WST2R7           (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x0CC))
#define SMC_WSTOENR7         (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x0D0))
#define SMC_WSTWENR7         (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x0D4))
#define SMC_CR7              (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x0D8))
#define SMC_SR7              (*(volatile unsigned long *)(SMC_BASE_ADDR + 0x0DC))

/* Chip/Feature ID register */
#define CFID_BASE_ADDR       0xE0000000
#define CFID_CHIPID          (*(volatile unsigned long *)(CFID_BASE_ADDR + 0x000))
#define CFID_FEAT0           (*(volatile unsigned long *)(CFID_BASE_ADDR + 0x100))
#define CFID_FEAT1           (*(volatile unsigned long *)(CFID_BASE_ADDR + 0x104))
#define CFID_FEAT2           (*(volatile unsigned long *)(CFID_BASE_ADDR + 0x108))

/* System Control Unit register */
#define SCU_BASE_ADDR        0xE0001000
#define SFSP0_BASE           (SCU_BASE_ADDR + 0x000)
#define SFSP0_0              (*(volatile unsigned long *)(SFSP0_BASE + 0x00))
#define SFSP0_1              (*(volatile unsigned long *)(SFSP0_BASE + 0x04))
#define SFSP0_2              (*(volatile unsigned long *)(SFSP0_BASE + 0x08))
#define SFSP0_3              (*(volatile unsigned long *)(SFSP0_BASE + 0x0C))
#define SFSP0_4              (*(volatile unsigned long *)(SFSP0_BASE + 0x10))
#define SFSP0_5              (*(volatile unsigned long *)(SFSP0_BASE + 0x14))
#define SFSP0_6              (*(volatile unsigned long *)(SFSP0_BASE + 0x18))
#define SFSP0_7              (*(volatile unsigned long *)(SFSP0_BASE + 0x1C))
#define SFSP0_8              (*(volatile unsigned long *)(SFSP0_BASE + 0x20))
#define SFSP0_9              (*(volatile unsigned long *)(SFSP0_BASE + 0x24))
#define SFSP0_10             (*(volatile unsigned long *)(SFSP0_BASE + 0x28))
#define SFSP0_11             (*(volatile unsigned long *)(SFSP0_BASE + 0x2C))
#define SFSP0_12             (*(volatile unsigned long *)(SFSP0_BASE + 0x30))
#define SFSP0_13             (*(volatile unsigned long *)(SFSP0_BASE + 0x34))
#define SFSP0_14             (*(volatile unsigned long *)(SFSP0_BASE + 0x38))
#define SFSP0_15             (*(volatile unsigned long *)(SFSP0_BASE + 0x3C))
#define SFSP0_16             (*(volatile unsigned long *)(SFSP0_BASE + 0x40))
#define SFSP0_17             (*(volatile unsigned long *)(SFSP0_BASE + 0x44))
#define SFSP0_18             (*(volatile unsigned long *)(SFSP0_BASE + 0x48))
#define SFSP0_19             (*(volatile unsigned long *)(SFSP0_BASE + 0x4C))
#define SFSP0_20             (*(volatile unsigned long *)(SFSP0_BASE + 0x50))
#define SFSP0_21             (*(volatile unsigned long *)(SFSP0_BASE + 0x54))
#define SFSP0_22             (*(volatile unsigned long *)(SFSP0_BASE + 0x58))
#define SFSP0_23             (*(volatile unsigned long *)(SFSP0_BASE + 0x5C))
#define SFSP0_24             (*(volatile unsigned long *)(SFSP0_BASE + 0x60))
#define SFSP0_25             (*(volatile unsigned long *)(SFSP0_BASE + 0x64))
#define SFSP0_26             (*(volatile unsigned long *)(SFSP0_BASE + 0x68))
#define SFSP0_27             (*(volatile unsigned long *)(SFSP0_BASE + 0x6C))
#define SFSP0_28             (*(volatile unsigned long *)(SFSP0_BASE + 0x70))
#define SFSP0_29             (*(volatile unsigned long *)(SFSP0_BASE + 0x74))
#define SFSP0_30             (*(volatile unsigned long *)(SFSP0_BASE + 0x78))
#define SFSP0_31             (*(volatile unsigned long *)(SFSP0_BASE + 0x7C))

#define SFSP1_BASE           (SCU_BASE_ADDR + 0x100)
#define SFSP1_0              (*(volatile unsigned long *)(SFSP1_BASE + 0x00))
#define SFSP1_1              (*(volatile unsigned long *)(SFSP1_BASE + 0x04))
#define SFSP1_2              (*(volatile unsigned long *)(SFSP1_BASE + 0x08))
#define SFSP1_3              (*(volatile unsigned long *)(SFSP1_BASE + 0x0C))
#define SFSP1_4              (*(volatile unsigned long *)(SFSP1_BASE + 0x10))
#define SFSP1_5              (*(volatile unsigned long *)(SFSP1_BASE + 0x14))
#define SFSP1_6              (*(volatile unsigned long *)(SFSP1_BASE + 0x18))
#define SFSP1_7              (*(volatile unsigned long *)(SFSP1_BASE + 0x1C))
#define SFSP1_8              (*(volatile unsigned long *)(SFSP1_BASE + 0x20))
#define SFSP1_9              (*(volatile unsigned long *)(SFSP1_BASE + 0x24))
#define SFSP1_10             (*(volatile unsigned long *)(SFSP1_BASE + 0x28))
#define SFSP1_11             (*(volatile unsigned long *)(SFSP1_BASE + 0x2C))
#define SFSP1_12             (*(volatile unsigned long *)(SFSP1_BASE + 0x30))
#define SFSP1_13             (*(volatile unsigned long *)(SFSP1_BASE + 0x34))
#define SFSP1_14             (*(volatile unsigned long *)(SFSP1_BASE + 0x38))
#define SFSP1_15             (*(volatile unsigned long *)(SFSP1_BASE + 0x3C))
#define SFSP1_16             (*(volatile unsigned long *)(SFSP1_BASE + 0x40))
#define SFSP1_17             (*(volatile unsigned long *)(SFSP1_BASE + 0x44))
#define SFSP1_18             (*(volatile unsigned long *)(SFSP1_BASE + 0x48))