📄 ma_sfr.h
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#define U0LSR_PE 0x04 /* Bit 2: PE (Parity error) */
#define U0LSR_PE_OK 0x00 /* No parity error */
#define U0LSR_PE_ERROR 0x01 /* Parity error occured */
#define U0LSR_OE 0x02 /* Bit 1: OE (Overrun error) */
#define U0LSR_OE_OK 0x00 /* No overrun error */
#define U0LSR_OE_ERROR 0x01 /* Overrun error occured */
#define U0LSR_DR 0x01 /* Bit 0: DR (Receiver data ready) */
#define U0LSR_DR_EMPTY 0x00 /* Empty */
#define U0LSR_DR_VALID 0x01 /* Valid data in receive buffer register */
/*
**---------------------------------------------------------------------------
** UART0 Scratch Pad Register
**---------------------------------------------------------------------------
*/
#define U0SCR_DATA 0xff /* Bit 7-0: DATA (A readable /writable byte) */
/*
**---------------------------------------------------------------------------
** UART1 Receiver Buffer Register
**---------------------------------------------------------------------------
*/
#define U1RBR_RXD 0xff /* Bit 7-0: RXD (Received data) */
/*
**---------------------------------------------------------------------------
** UART1 Transmit Holding Register
**---------------------------------------------------------------------------
*/
#define U1THR_TXD 0xff /* Bit 7-0: TXD (Transmit data) */
/*
**---------------------------------------------------------------------------
** UART1 Divisor Latch LSB
**---------------------------------------------------------------------------
*/
#define U1DLL_DIVL 0xff /* Bit 7-0: DIVL (Baud rate generator divisor [7:0]) */
/*
**---------------------------------------------------------------------------
** UART1 Divisor Latch MSB
**---------------------------------------------------------------------------
*/
#define U1DLM_DIVM 0xff /* Bit 7-0: DIVM (Baud rate generator divisor [15:8]) */
/*
**---------------------------------------------------------------------------
** UART1 Interrupt Enable Register
**---------------------------------------------------------------------------
*/
#define U1IER_MSIE 0x08 /* Bit 3: MSIE (Modem status interrupt enable (MODEM)) */
#define U1IER_MSIE_DISABLED 0x00 /* Disabled */
#define U1IER_MSIE_ENABLED 0x01 /* Enabled */
#define U1IER_RXLSIE 0x04 /* Bit 2: RXLSIE (Rx Line status interrupt enable (RXLINE)) */
#define U1IER_RXLSIE_DISABLED 0x00 /* Disabled */
#define U1IER_RXLSIE_ENABLED 0x01 /* Enabled */
#define U1IER_THREIE 0x02 /* Bit 1: THREIE (Transmit interrupt enable (THRE)) */
#define U1IER_THREIE_DISABLED 0x00 /* Disabled */
#define U1IER_THREIE_ENABLED 0x01 /* Enabled */
#define U1IER_RDAIE 0x01 /* Bit 0: RDAIE (Receive interrupt enable (RDA)) */
#define U1IER_RDAIE_DISABLED 0x00 /* Disabled */
#define U1IER_RDAIE_ENABLED 0x01 /* Enabled */
/*
**---------------------------------------------------------------------------
** UART1 Interrupt ID Register
**---------------------------------------------------------------------------
*/
#define U1IIR_IIRFE 0xc0 /* Bit 7-6: IIRFE (FIFO enable) */
#define U1IIR_IIRFE_ONE 0x00 /* 1 (Trigger level 0 (=1)) */
#define U1IIR_IIRFE_FOUR 0x01 /* 4 (Trigger level 1 (=4)) */
#define U1IIR_IIRFE_EIGHT 0x02 /* 8 (Trigger level 2 (=8)) */
#define U1IIR_IIRFE_FOURTEEN 0x03 /* 14 (Trigger level 3 (=14)) */
#define U1IIR_IID 0x0e /* Bit 3-1: IID (Interrupt identification) */
#define U1IIR_IID_MODEM_INT 0x00 /* Modem interrupt (Fourth priority) */
#define U1IIR_IID_THRE_INT 0x01 /* Transmit buffer empty interrupt (THRE) (Third priority) */
#define U1IIR_IID_CTI_INT 0x06 /* Character timeout interrupt (CTI) (Second priority) */
#define U1IIR_IID_RDA_INT 0x02 /* Receive data available or Trigger level interrupt code (RDA) (Second priority) */
#define U1IIR_IID_RX_LINE_INT 0x03 /* Receive line status interrupt (Highest priority) */
#define U1IIR_IP 0x01 /* Bit 0: IP (Interrupt pending) */
#define U1IIR_IP_INTERRUPT 0x00 /* Interrupt pending */
#define U1IIR_IP_NO_INTERRUPT 0x01 /* No pending interrupt */
/*
**---------------------------------------------------------------------------
** UART1 FIFO Control Register
**---------------------------------------------------------------------------
*/
#define U1FCR_RTLS 0xc0 /* Bit 7-6: RTLS (Receive FIFO trigger level) */
#define U1FCR_RTLS_ONE 0x00 /* 1 (Trigger level 0 (=1)) */
#define U1FCR_RTLS_FOUR 0x01 /* 4 (Trigger level 1 (=4)) */
#define U1FCR_RTLS_EIGHT 0x02 /* 8 (Trigger level 2 (=8)) */
#define U1FCR_RTLS_FOURTEEN 0x03 /* 14 (Trigger level 3 (=14)) */
#define U1FCR_TFR 0x04 /* Bit 2: TFR (Clear transmit FIFO) */
#define U1FCR_TFR_NOTHING 0x00 /* Nothing happens */
#define U1FCR_TFR_RESET 0x01 /* Reset transfer pointers and clear TX FIFO */
#define U1FCR_RFR 0x02 /* Bit 1: RFR (Clear receive FIFO) */
#define U1FCR_RFR_NOTHING 0x00 /* Nothing happens */
#define U1FCR_RFR_RESET 0x01 /* Reset receive pointers and clear RX FIFO */
#define U1FCR_FCRFE 0x01 /* Bit 0: FCRFE (FIFO enable) */
#define U1FCR_FCRFE_DISABLED 0x00 /* Disabled (Disabled FIFOs) */
#define U1FCR_FCRFE_ENABLED 0x01 /* Enabled (Enable TX and RX FIFOs) */
/*
**---------------------------------------------------------------------------
** UART1 Line Control Register
**---------------------------------------------------------------------------
*/
#define U1LCR_DLAB 0x80 /* Bit 7: DLAB (Divisor latch access bit) */
#define U1LCR_DLAB_TX_RX 0x00 /* Access transmit/receive registers */
#define U1LCR_DLAB_DIVISOR 0x01 /* Access divisor registers (Divisor used for baud rate generator ) */
#define U1LCR_BC 0x40 /* Bit 6: BC (Break control) */
#define U1LCR_BC_DISABLED 0x00 /* Disabled (No break) */
#define U1LCR_BC_ENABLED 0x01 /* Enabled (Send continous 0 on transmit output) */
#define U1LCR_PS 0x30 /* Bit 5-4: PS (Parity select) */
#define U1LCR_PS_ODD 0x00 /* Odd parity */
#define U1LCR_PS_EVEN 0x01 /* Even parity */
#define U1LCR_PS_FORCED_1 0x02 /* Forced "1" stick parity */
#define U1LCR_PS_FORCED_0 0x03 /* Forced "0" stick parity */
#define U1LCR_PE 0x08 /* Bit 3: PE (Parity enable) */
#define U1LCR_PE_DISABLED 0x00 /* Disabled (No parity generation and checking) */
#define U1LCR_PE_ENABLED 0x01 /* Enabled (Parity generation and checking) */
#define U1LCR_SBS 0x04 /* Bit 2: SBS (Stop bit select) */
#define U1LCR_SBS_S1 0x00 /* 1 stop bit */
#define U1LCR_SBS_S2 0x01 /* 2 stop bits ((=1.5 if 5 bit character length is used)) */
#define U1LCR_WLS 0x03 /* Bit 1-0: WLS (Word length select) */
#define U1LCR_WLS_D5 0x00 /* 5 data bits */
#define U1LCR_WLS_D6 0x01 /* 6 data bits */
#define U1LCR_WLS_D7 0x02 /* 7 data bits */
#define U1LCR_WLS_D8 0x03 /* 8 data bits */
/*
**---------------------------------------------------------------------------
** UART1 Modem Control Register
**---------------------------------------------------------------------------
*/
#define U1MCR_LMS 0x10 /* Bit 4: LMS (Loop-back mode select) */
#define U1MCR_LMS_NORMAL 0x00 /* Normal mode */
#define U1MCR_LMS_LOOPBACK 0x01 /* Loop-back mode */
#define U1MCR_RTS 0x02 /* Bit 1: RTS (RTS control) */
#define U1MCR_DTR 0x01 /* Bit 0: DTR (DTR control) */
/*
**---------------------------------------------------------------------------
** UART1 Line Status Register
**---------------------------------------------------------------------------
*/
#define U1LSR_RXFE 0x80 /* Bit 7: RXFE (Receive error) */
#define U1LSR_RXFE_OK 0x00 /* No receive error in FIFO mode or Always 0 in non FIFO mode */
#define U1LSR_RXFE_ERROR 0x01 /* Parity, framing or break indication in the FIFO */
#define U1LSR_TEMT 0x40 /* Bit 6: TEMT (Transmit empty) */
#define U1LSR_TEMT_TRANSMIT 0x00 /* Transmission in progress */
#define U1LSR_TEMT_IDLE 0x01 /* Transmitter idle */
#define U1LSR_THRE 0x20 /* Bit 5: THRE (Transmit holding register empty) */
#define U1LSR_THRE_VALID 0x00 /* Valid data in transmit register */
#define U1LSR_THRE_EMPTY 0x01 /* Empty */
#define U1LSR_BI 0x10 /* Bit 4: BI (Break indicator) */
#define U1LSR_BI_NO 0x00 /* No break */
#define U1LSR_BI_BREAK 0x01 /* Break condition detected on receive input line */
#define U1LSR_FE 0x08 /* Bit 3: FE (Framing error) */
#define U1LSR_FE_OK 0x00 /* No framing error */
#define U1LSR_FE_ERROR 0x01 /* Framing error occured */
#define U1LSR_PE 0x04 /* Bit 2: PE (Parity error) */
#define U1LSR_PE_OK 0x00 /* No parity error */
#define U1LSR_PE_ERROR 0x01 /* Parity error occured */
#define U1LSR_OE 0x02 /* Bit 1: OE (Overrun error) */
#define U1LSR_OE_OK 0x00 /* No overrun error */
#define U1LSR_OE_ERROR 0x01 /* Overrun error occured */
#define U1LSR_DR 0x01 /* Bit 0: DR (Receiver data ready) */
#define U1LSR_DR_EMPTY 0x00 /* Empty */
#define U1LSR_DR_VALID 0x01 /* Valid data in receive buffer register */
/*
**---------------------------------------------------------------------------
** UART1 Modem Status Register
**---------------------------------------------------------------------------
*/
#define U1MSR_DCD 0x80 /* Bit 7: DCD (Data carrier detect) */
#define U1MSR_RI 0x40 /* Bit 6: RI (Ring indicator) */
#define U1MSR_DSR 0x20 /* Bit 5: DSR (Data set ready) */
#define U1MSR_CTS 0x10 /* Bit 4: CTS (Clear to send) */
#define U1MSR_DDCD 0x08 /* Bit 3: DDCD (Delta status change of DCD) */
#define U1MSR_DDCD_NO 0x00 /* No change */
#define U1MSR_DDCD_CHANGED 0x01 /* DCD changed */
#define U1MSR_TERI 0x04 /* Bit 2: TERI (Trailing edge change of RI) */
#define U1MSR_TERI_NO 0x00 /* No change */
#define U1MSR_TERI_CHANGED 0x01 /* RI changed */
#define U1MSR_DDSR 0x02 /* Bit 1: DDSR (Delta status change of DSR) */
#define U1MSR_DDSR_NO 0x00 /* No change */
#define U1MSR_DDSR_CHANGED 0x01 /* DSR changed */
#define U1MSR_DCTS 0x01 /* Bit 0: DCTS (Delta status change of CTS) */
#define U1MSR_DCTS_NO 0x00 /* No change */
#define U1MSR_DCTS_CHANGED 0x01 /* CTS changed */
/*
**---------------------------------------------------------------------------
** UART1 Scratch Pad Register
**---------------------------------------------------------------------------
*/
#define U1SCR_DATA 0xff /* Bit 7-0: DATA (A readable /writable byte) */
/*
**---------------------------------------------------------------------------
** PWM Interrupt Register
**---------------------------------------------------------------------------
*/
#define PWMIR_MR6INT 0x400 /* Bit 10: MR6INT (Interrupt flag for PWM match channel 6) */
#define PWMIR_MR6INT_NO_INTERRUPT 0x00 /* No interrupt */
#define PWMIR_MR6INT_INTERRUPT 0x01 /* Interrupt */
#define PWMIR_MR5INT 0x200 /* Bit 9: MR5INT (Interrupt flag for PWM match channel 5) */
#define PWMIR_MR5INT_NO_INTERRUPT 0x00 /* No interrupt */
#define PWMIR_MR5INT_INTERRUPT 0x01 /* Interrupt */
#define PWMIR_MR4INT 0x100 /* Bit 8: MR4INT (Interrupt flag for PWM match channel 4) */
#define PWMIR_MR4INT_NO_INTERRUPT 0x00 /* No interrupt */
#define PWMIR_MR4INT_INTERRUPT 0x01 /* Interrupt */
#define PWMIR_MR3INT 0x08 /* Bit 3: MR3INT (Interrupt flag for PWM match channel 3) */
#define PWMIR_MR3INT_NO_INTERRUPT 0x00 /* No interrupt */
#define PWMIR_MR3INT_INTERRUPT 0x01 /* Interrupt */
#define PWMIR_MR2INT 0x04 /* Bit 2: MR2INT (Interrupt flag for PWM match channel 2) */
#define PWMIR_MR2INT_NO_INTERRUPT 0x00 /* No interrupt */
#define PWMIR_MR2INT_INTERRUPT 0x01 /* Interrupt */
#define PWMIR_MR1INT 0x02 /* Bit 1: MR1INT (Interrupt flag for PWM match channel 1) */
#define PWMIR_MR1INT_NO_INTERRUPT 0x00 /* No interrupt */
#define PWMIR_MR1INT_INTERRUPT 0x01 /* Interrupt */
#define PWMIR_MR0INT 0x01 /* Bit 0: MR0INT (Interrupt flag for PWM match channel 0) */
#define PWMIR_MR0INT_NO_INTERRUPT 0x00 /* No interrupt */
#define PWMIR_MR0INT_INTERRUPT 0x01 /* Interrupt */
/*
**---------------------------------------------------------------------------
** PWM Timer Control Register
**---------------------------------------------------------------------------
*/
#define PWMTCR_PWMEN 0x08 /* Bit 3: PWMEN (PWM enable) */
#define PWMTCR_PWMEN_DISABLED 0x00 /* Disabled */
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