ma_sfr.h

NXP LPC系列AMR7的开发程序源码（LCD

#define PWMTCR_PWMEN_ENABLED       0x01   /* Enabled (Shadow registers operates) */

#define PWMTCR_CR                  0x02   /* Bit 1: CR (Counter reset) */
#define PWMTCR_CR_NO_RESET         0x00   /* No reset */
#define PWMTCR_CR_RESET            0x01   /* Generate reset */

#define PWMTCR_CE                  0x01   /* Bit 0: CE (Counter enable) */
#define PWMTCR_CE_DISABLED         0x00   /* Disabled */
#define PWMTCR_CE_ENABLED          0x01   /* Enabled */


/*
**---------------------------------------------------------------------------
**  PWM Timer Counter
**---------------------------------------------------------------------------
*/

#define PWMTC_VALUE                0xffffffff /* Bit 31-0: VALUE (PWM counter value) */


/*
**---------------------------------------------------------------------------
**  PWM Prescale Register
**---------------------------------------------------------------------------
*/

#define PWMPR_VALUE                0xffffffff /* Bit 31-0: VALUE (PWM prescaler max value) */


/*
**---------------------------------------------------------------------------
**  PWM Prescale Counter
**---------------------------------------------------------------------------
*/

#define PWMPC_VALUE                0xffffffff /* Bit 31-0: VALUE (PWM prescale counter value) */


/*
**---------------------------------------------------------------------------
**  PWM Match Control Register
**---------------------------------------------------------------------------
*/

#define PWMMCR_MR6STOP             0x100000 /* Bit 20: MR6STOP (Stop on MR6) */
#define PWMMCR_MR6STOP_DISABLED    0x00   /* Disabled */
#define PWMMCR_MR6STOP_ENABLED     0x01   /* Enabled */

#define PWMMCR_MR6RES              0x80000 /* Bit 19: MR6RES (Reset on MR6) */
#define PWMMCR_MR6RES_DISABLED     0x00   /* Disabled */
#define PWMMCR_MR6RES_ENABLED      0x01   /* Enabled */

#define PWMMCR_MR6INT              0x40000 /* Bit 18: MR6INT (Interrupt on MR6) */
#define PWMMCR_MR6INT_DISABLED     0x00   /* Disabled */
#define PWMMCR_MR6INT_ENABLED      0x01   /* Enabled */

#define PWMMCR_MR5STOP             0x20000 /* Bit 17: MR5STOP (Stop on MR5) */
#define PWMMCR_MR5STOP_DISABLED    0x00   /* Disabled */
#define PWMMCR_MR5STOP_ENABLED     0x01   /* Enabled */

#define PWMMCR_MR5RES              0x10000 /* Bit 16: MR5RES (Reset on MR5) */
#define PWMMCR_MR5RES_DISABLED     0x00   /* Disabled */
#define PWMMCR_MR5RES_ENABLED      0x01   /* Enabled */

#define PWMMCR_MR5INT              0x8000 /* Bit 15: MR5INT (Interrupt on MR5) */
#define PWMMCR_MR5INT_DISABLED     0x00   /* Disabled */
#define PWMMCR_MR5INT_ENABLED      0x01   /* Enabled */

#define PWMMCR_MR4STOP             0x4000 /* Bit 14: MR4STOP (Stop on MR4) */
#define PWMMCR_MR4STOP_DISABLED    0x00   /* Disabled */
#define PWMMCR_MR4STOP_ENABLED     0x01   /* Enabled */

#define PWMMCR_MR4RES              0x2000 /* Bit 13: MR4RES (Reset on MR4) */
#define PWMMCR_MR4RES_DISABLED     0x00   /* Disabled */
#define PWMMCR_MR4RES_ENABLED      0x01   /* Enabled */

#define PWMMCR_MR4INT              0x1000 /* Bit 12: MR4INT (Interrupt on MR4) */
#define PWMMCR_MR4INT_DISABLED     0x00   /* Disabled */
#define PWMMCR_MR4INT_ENABLED      0x01   /* Enabled */

#define PWMMCR_MR3STOP             0x800  /* Bit 11: MR3STOP (Stop on MR3) */
#define PWMMCR_MR3STOP_DISABLED    0x00   /* Disabled */
#define PWMMCR_MR3STOP_ENABLED     0x01   /* Enabled */

#define PWMMCR_MR3RES              0x400  /* Bit 10: MR3RES (Reset on MR3) */
#define PWMMCR_MR3RES_DISABLED     0x00   /* Disabled */
#define PWMMCR_MR3RES_ENABLED      0x01   /* Enabled */

#define PWMMCR_MR3INT              0x200  /* Bit 9: MR3INT (Interrupt on MR3) */
#define PWMMCR_MR3INT_DISABLED     0x00   /* Disabled */
#define PWMMCR_MR3INT_ENABLED      0x01   /* Enabled */

#define PWMMCR_MR2STOP             0x100  /* Bit 8: MR2STOP (Stop on MR2) */
#define PWMMCR_MR2STOP_DISABLED    0x00   /* Disabled */
#define PWMMCR_MR2STOP_ENABLED     0x01   /* Enabled */

#define PWMMCR_MR2RES              0x80   /* Bit 7: MR2RES (Reset on MR2) */
#define PWMMCR_MR2RES_DISABLED     0x00   /* Disabled */
#define PWMMCR_MR2RES_ENABLED      0x01   /* Enabled */

#define PWMMCR_MR2INT              0x40   /* Bit 6: MR2INT (Interrupt on MR2) */
#define PWMMCR_MR2INT_DISABLED     0x00   /* Disabled */
#define PWMMCR_MR2INT_ENABLED      0x01   /* Enabled */

#define PWMMCR_MR1STOP             0x20   /* Bit 5: MR1STOP (Stop on MR1) */
#define PWMMCR_MR1STOP_DISABLED    0x00   /* Disabled */
#define PWMMCR_MR1STOP_ENABLED     0x01   /* Enabled */

#define PWMMCR_MR1RES              0x10   /* Bit 4: MR1RES (Reset on MR1) */
#define PWMMCR_MR1RES_DISABLED     0x00   /* Disabled */
#define PWMMCR_MR1RES_ENABLED      0x01   /* Enabled */

#define PWMMCR_MR1INT              0x08   /* Bit 3: MR1INT (Interrupt on MR1) */
#define PWMMCR_MR1INT_DISABLED     0x00   /* Disabled */
#define PWMMCR_MR1INT_ENABLED      0x01   /* Enabled */

#define PWMMCR_MR0STOP             0x04   /* Bit 2: MR0STOP (Stop on MR0) */
#define PWMMCR_MR0STOP_DISABLED    0x00   /* Disabled */
#define PWMMCR_MR0STOP_ENABLED     0x01   /* Enabled */

#define PWMMCR_MR0RES              0x02   /* Bit 1: MR0RES (Reset on MR0) */
#define PWMMCR_MR0RES_DISABLED     0x00   /* Disabled */
#define PWMMCR_MR0RES_ENABLED      0x01   /* Enabled */

#define PWMMCR_MR0INT              0x01   /* Bit 0: MR0INT (Interrupt on MR0) */
#define PWMMCR_MR0INT_DISABLED     0x00   /* Disabled */
#define PWMMCR_MR0INT_ENABLED      0x01   /* Enabled */


/*
**---------------------------------------------------------------------------
**  PWM Match Register 0
**---------------------------------------------------------------------------
*/

#define PWMMR0_VALUE               0xffffffff /* Bit 31-0: VALUE (PWM Match value) */


/*
**---------------------------------------------------------------------------
**  PWM Match Register 1
**---------------------------------------------------------------------------
*/

#define PWMMR1_VALUE               0xffffffff /* Bit 31-0: VALUE (PWM Match value) */


/*
**---------------------------------------------------------------------------
**  PWM Match Register 2
**---------------------------------------------------------------------------
*/

#define PWMMR2_VALUE               0xffffffff /* Bit 31-0: VALUE (PWM Match value) */


/*
**---------------------------------------------------------------------------
**  PWM Match Register 3
**---------------------------------------------------------------------------
*/

#define PWMMR3_VALUE               0xffffffff /* Bit 31-0: VALUE (PWM Match value) */


/*
**---------------------------------------------------------------------------
**  PWM Match Register 4
**---------------------------------------------------------------------------
*/

#define PWMMR4_VALUE               0xffffffff /* Bit 31-0: VALUE (PWM Match value) */


/*
**---------------------------------------------------------------------------
**  PWM Match Register 5
**---------------------------------------------------------------------------
*/

#define PWMMR5_VALUE               0xffffffff /* Bit 31-0: VALUE (PWM Match value) */


/*
**---------------------------------------------------------------------------
**  PWM Match Register 6
**---------------------------------------------------------------------------
*/

#define PWMMR6_VALUE               0xffffffff /* Bit 31-0: VALUE (PWM Match value) */


/*
**---------------------------------------------------------------------------
**  PWM Control Register
**---------------------------------------------------------------------------
*/

#define PWMPCR_ENA6                0x4000 /* Bit 14: ENA6 (PWM6 output control) */
#define PWMPCR_ENA6_DISABLED       0x00   /* Disabled */
#define PWMPCR_ENA6_ENABLED        0x01   /* Enabled */

#define PWMPCR_ENA5                0x2000 /* Bit 13: ENA5 (PWM5 output control) */
#define PWMPCR_ENA5_DISABLED       0x00   /* Disabled */
#define PWMPCR_ENA5_ENABLED        0x01   /* Enabled */

#define PWMPCR_ENA4                0x1000 /* Bit 12: ENA4 (PWM4 output control) */
#define PWMPCR_ENA4_DISABLED       0x00   /* Disabled */
#define PWMPCR_ENA4_ENABLED        0x01   /* Enabled */

#define PWMPCR_ENA3                0x800  /* Bit 11: ENA3 (PWM3 output control) */
#define PWMPCR_ENA3_DISABLED       0x00   /* Disabled */
#define PWMPCR_ENA3_ENABLED        0x01   /* Enabled */

#define PWMPCR_ENA2                0x400  /* Bit 10: ENA2 (PWM2 output control) */
#define PWMPCR_ENA2_DISABLED       0x00   /* Disabled */
#define PWMPCR_ENA2_ENABLED        0x01   /* Enabled */

#define PWMPCR_ENA1                0x200  /* Bit 9: ENA1 (PWM1 output control) */
#define PWMPCR_ENA1_DISABLED       0x00   /* Disabled */
#define PWMPCR_ENA1_ENABLED        0x01   /* Enabled */

#define PWMPCR_SEL6                0x40   /* Bit 6: SEL6 (PWM6 select control mode) */
#define PWMPCR_SEL6_SINGLE         0x00   /* Single edge */
#define PWMPCR_SEL6_DOUBLE         0x01   /* Double edge */

#define PWMPCR_SEL5                0x20   /* Bit 5: SEL5 (PWM5 select control mode) */
#define PWMPCR_SEL5_SINGLE         0x00   /* Single edge */
#define PWMPCR_SEL5_DOUBLE         0x01   /* Double edge */

#define PWMPCR_SEL4                0x10   /* Bit 4: SEL4 (PWM4 select control mode) */
#define PWMPCR_SEL4_SINGLE         0x00   /* Single edge */
#define PWMPCR_SEL4_DOUBLE         0x01   /* Double edge */

#define PWMPCR_SEL3                0x08   /* Bit 3: SEL3 (PWM3 select control mode) */
#define PWMPCR_SEL3_SINGLE         0x00   /* Single edge */
#define PWMPCR_SEL3_DOUBLE         0x01   /* Double edge */

#define PWMPCR_SEL2                0x04   /* Bit 2: SEL2 (PWM2 select control mode) */
#define PWMPCR_SEL2_SINGLE         0x00   /* Single edge */
#define PWMPCR_SEL2_DOUBLE         0x01   /* Double edge */

#define PWMPCR_SEL1                0x02   /* Bit 1: SEL1 (PWM1 select control mode) */
#define PWMPCR_SEL1_SINGLE         0x00   /* Single edge */
#define PWMPCR_SEL1_DOUBLE         0x01   /* Double edge */


/*
**---------------------------------------------------------------------------
**  PWM Latch Enable Register
**---------------------------------------------------------------------------
*/

#define PWMLER_EM6L                0x40   /* Bit 6: EM6L (Enable PWM match 6 latch) */
#define PWMLER_EM6L_DISABLED       0x00   /* Disabled */
#define PWMLER_EM6L_ENABLED        0x01   /* Enabled */

#define PWMLER_EM5L                0x20   /* Bit 5: EM5L (Enable PWM match 5 latch) */
#define PWMLER_EM5L_DISABLED       0x00   /* Disabled */
#define PWMLER_EM5L_ENABLED        0x01   /* Enabled */

#define PWMLER_EM4L                0x10   /* Bit 4: EM4L (Enable PWM match 4 latch) */
#define PWMLER_EM4L_DISABLED       0x00   /* Disabled */
#define PWMLER_EM4L_ENABLED        0x01   /* Enabled */

#define PWMLER_EM3L                0x08   /* Bit 3: EM3L (Enable PWM match 3 latch) */
#define PWMLER_EM3L_DISABLED       0x00   /* Disabled */
#define PWMLER_EM3L_ENABLED        0x01   /* Enabled */

#define PWMLER_EM2L                0x04   /* Bit 2: EM2L (Enable PWM match 2 latch) */
#define PWMLER_EM2L_DISABLED       0x00   /* Disabled */
#define PWMLER_EM2L_ENABLED        0x01   /* Enabled */

#define PWMLER_EM1L                0x02   /* Bit 1: EM1L (Enable PWM match 1 latch) */
#define PWMLER_EM1L_DISABLED       0x00   /* Disabled */
#define PWMLER_EM1L_ENABLED        0x01   /* Enabled */

#define PWMLER_EM0L                0x01   /* Bit 0: EM0L (Enable PWM match 0 latch) */
#define PWMLER_EM0L_DISABLED       0x00   /* Disabled */
#define PWMLER_EM0L_ENABLED        0x01   /* Enabled */


/*
**---------------------------------------------------------------------------
**  I2C Control Set Register
**---------------------------------------------------------------------------
*/

#define I2CONSET_I2EN              0x40   /* Bit 6: I2EN (I2C interface enable) */
#define I2CONSET_I2EN_DISABLED     0x00   /* Disabled */
#define I2CONSET_I2EN_ENABLED      0x01   /* Enabled */

#define I2CONSET_STA               0x20   /* Bit 5: STA (Start flag) */
#define I2CONSET_STA_NO_START      0x00   /* No start */
#define I2CONSET_STA_START         0x01   /* Start */

#define I2CONSET_STO               0x10   /* Bit 4: STO (Stop flag) */
#define I2CONSET_STO_NO_STOP       0x00   /* No stop */
#define I2CONSET_ST