ma_sfr.h

NXP LPC系列AMR7的开发程序源码（LCD

/*
**---------------------------------------------------------------------------
**  Timer 1 Capture Control Register
**---------------------------------------------------------------------------
*/

#define T1CCR_CAP3INT              0x800  /* Bit 11: CAP3INT (Interrupt on capture CAP3) */
#define T1CCR_CAP3INT_DISABLED     0x00   /* Disabled */
#define T1CCR_CAP3INT_ENABLED      0x01   /* Enabled */

#define T1CCR_CAP3FE               0x400  /* Bit 10: CAP3FE (Capture on CAP3 falling edge) */
#define T1CCR_CAP3FE_DISABLED      0x00   /* Disabled */
#define T1CCR_CAP3FE_ENABLED       0x01   /* Enabled */

#define T1CCR_CAP3RE               0x200  /* Bit 9: CAP3RE (Capture on CAP3 rising edge) */
#define T1CCR_CAP3RE_DISABLED      0x00   /* Disabled */
#define T1CCR_CAP3RE_ENABLED       0x01   /* Enabled */

#define T1CCR_CAP2INT              0x100  /* Bit 8: CAP2INT (Interrupt on capture CAP2) */
#define T1CCR_CAP2INT_DISABLED     0x00   /* Disabled */
#define T1CCR_CAP2INT_ENABLED      0x01   /* Enabled */

#define T1CCR_CAP2FE               0x80   /* Bit 7: CAP2FE (Capture on CAP2 falling edge) */
#define T1CCR_CAP2FE_DISABLED      0x00   /* Disabled */
#define T1CCR_CAP2FE_ENABLED       0x01   /* Enabled */

#define T1CCR_CAP2RE               0x40   /* Bit 6: CAP2RE (Capture on CAP2 rising edge) */
#define T1CCR_CAP2RE_DISABLED      0x00   /* Disabled */
#define T1CCR_CAP2RE_ENABLED       0x01   /* Enabled */

#define T1CCR_CAP1INT              0x20   /* Bit 5: CAP1INT (Interrupt on capture CAP1) */
#define T1CCR_CAP1INT_DISABLED     0x00   /* Disabled */
#define T1CCR_CAP1INT_ENABLED      0x01   /* Enabled */

#define T1CCR_CAP1FE               0x10   /* Bit 4: CAP1FE (Capture on CAP1 falling edge) */
#define T1CCR_CAP1FE_DISABLED      0x00   /* Disabled */
#define T1CCR_CAP1FE_ENABLED       0x01   /* Enabled */

#define T1CCR_CAP1RE               0x08   /* Bit 3: CAP1RE (Capture on CAP1 rising edge) */
#define T1CCR_CAP1RE_DISABLED      0x00   /* Disabled */
#define T1CCR_CAP1RE_ENABLED       0x01   /* Enabled */

#define T1CCR_CAP0INT              0x04   /* Bit 2: CAP0INT (Interrupt on capture CAP0) */
#define T1CCR_CAP0INT_DISABLED     0x00   /* Disabled */
#define T1CCR_CAP0INT_ENABLED      0x01   /* Enabled */

#define T1CCR_CAP0FE               0x02   /* Bit 1: CAP0FE (Capture on CAP0 falling edge) */
#define T1CCR_CAP0FE_DISABLED      0x00   /* Disabled */
#define T1CCR_CAP0FE_ENABLED       0x01   /* Enabled */

#define T1CCR_CAP0RE               0x01   /* Bit 0: CAP0RE (Capture on CAP0 rising edge) */
#define T1CCR_CAP0RE_DISABLED      0x00   /* Disabled */
#define T1CCR_CAP0RE_ENABLED       0x01   /* Enabled */


/*
**---------------------------------------------------------------------------
**  Timer 1 Capture Register 0
**---------------------------------------------------------------------------
*/

#define T1CR0_VALUE                0xffffffff /* Bit 31-0: VALUE (Timer capture value) */


/*
**---------------------------------------------------------------------------
**  Timer 1 Capture Register 1
**---------------------------------------------------------------------------
*/

#define T1CR1_VALUE                0xffffffff /* Bit 31-0: VALUE (Timer capture value) */


/*
**---------------------------------------------------------------------------
**  Timer 1 Capture Register 2
**---------------------------------------------------------------------------
*/

#define T1CR2_VALUE                0xffffffff /* Bit 31-0: VALUE (Timer capture value) */


/*
**---------------------------------------------------------------------------
**  Timer 1 Capture Register 3
**---------------------------------------------------------------------------
*/

#define T1CR3_VALUE                0xffffffff /* Bit 31-0: VALUE (Timer capture value) */


/*
**---------------------------------------------------------------------------
**  Timer 1 External Match Register
**---------------------------------------------------------------------------
*/

#define T1EMR_EMC3                 0xc00  /* Bit 11-10: EMC3 (External match control 3) */
#define T1EMR_EMC3_NOTHING         0x00   /* Do nothing */
#define T1EMR_EMC3_CLEAR           0x01   /* Clear output to 0 */
#define T1EMR_EMC3_SET             0x02   /* Set output to 1 */
#define T1EMR_EMC3_TOGGLE          0x03   /* Toggle output */

#define T1EMR_EMC2                 0x300  /* Bit 9-8: EMC2 (External match control 2) */
#define T1EMR_EMC2_NOTHING         0x00   /* Do nothing */
#define T1EMR_EMC2_CLEAR           0x01   /* Clear output to 0 */
#define T1EMR_EMC2_SET             0x02   /* Set output to 1 */
#define T1EMR_EMC2_TOGGLE          0x03   /* Toggle output */

#define T1EMR_EMC1                 0xc0   /* Bit 7-6: EMC1 (External match control 1) */
#define T1EMR_EMC1_NOTHING         0x00   /* Do nothing */
#define T1EMR_EMC1_CLEAR           0x01   /* Clear output to 0 */
#define T1EMR_EMC1_SET             0x02   /* Set output to 1 */
#define T1EMR_EMC1_TOGGLE          0x03   /* Toggle output */

#define T1EMR_EMC0                 0x30   /* Bit 5-4: EMC0 (External match control 0) */
#define T1EMR_EMC0_NOTHING         0x00   /* Do nothing */
#define T1EMR_EMC0_CLEAR           0x01   /* Clear output to 0 */
#define T1EMR_EMC0_SET             0x02   /* Set output to 1 */
#define T1EMR_EMC0_TOGGLE          0x03   /* Toggle output */

#define T1EMR_EM3                  0x08   /* Bit 3: EM3 (External match 3) */
#define T1EMR_EM3_LOW              0x00   /* Low */
#define T1EMR_EM3_HIGH             0x01   /* High */

#define T1EMR_EM2                  0x04   /* Bit 2: EM2 (External match 2) */
#define T1EMR_EM2_LOW              0x00   /* Low */
#define T1EMR_EM2_HIGH             0x01   /* High */

#define T1EMR_EM1                  0x02   /* Bit 1: EM1 (External match 1) */
#define T1EMR_EM1_LOW              0x00   /* Low */
#define T1EMR_EM1_HIGH             0x01   /* High */

#define T1EMR_EM0                  0x01   /* Bit 0: EM0 (External match 0) */
#define T1EMR_EM0_LOW              0x00   /* Low */
#define T1EMR_EM0_HIGH             0x01   /* High */


/*
**---------------------------------------------------------------------------
**  UART0 Receiver Buffer Register
**---------------------------------------------------------------------------
*/

#define U0RBR_RXD                  0xff   /* Bit 7-0: RXD (Received data) */


/*
**---------------------------------------------------------------------------
**  UART0 Transmit Holding Register
**---------------------------------------------------------------------------
*/

#define U0THR_TXD                  0xff   /* Bit 7-0: TXD (Transmit data) */


/*
**---------------------------------------------------------------------------
**  UART0 Divisor Latch LSB
**---------------------------------------------------------------------------
*/

#define U0DLL_DIVL                 0xff   /* Bit 7-0: DIVL (Baud rate generator divisor [7:0]) */


/*
**---------------------------------------------------------------------------
**  UART0 Divisor Latch MSB
**---------------------------------------------------------------------------
*/

#define U0DLM_DIVM                 0xff   /* Bit 7-0: DIVM (Baud rate generator divisor [15:8]) */


/*
**---------------------------------------------------------------------------
**  UART0 Interrupt Enable Register
**---------------------------------------------------------------------------
*/

#define U0IER_RXLSIE               0x04   /* Bit 2: RXLSIE (Rx Line status interrupt enable (RXLINE)) */
#define U0IER_RXLSIE_DISABLED      0x00   /* Disabled */
#define U0IER_RXLSIE_ENABLED       0x01   /* Enabled */

#define U0IER_THREIE               0x02   /* Bit 1: THREIE (Transmit interrupt enable (THRE)) */
#define U0IER_THREIE_DISABLED      0x00   /* Disabled */
#define U0IER_THREIE_ENABLED       0x01   /* Enabled */

#define U0IER_RDAIE                0x01   /* Bit 0: RDAIE (Receive interrupt enable (RDA)) */
#define U0IER_RDAIE_DISABLED       0x00   /* Disabled */
#define U0IER_RDAIE_ENABLED        0x01   /* Enabled */


/*
**---------------------------------------------------------------------------
**  UART0 Interrupt ID Register
**---------------------------------------------------------------------------
*/

#define U0IIR_IIRFE                0xc0   /* Bit 7-6: IIRFE (FIFO enable) */
#define U0IIR_IIRFE_ONE            0x00   /* 1 (Trigger level 0 (=1)) */
#define U0IIR_IIRFE_FOUR           0x01   /* 4 (Trigger level 1 (=4)) */
#define U0IIR_IIRFE_EIGHT          0x02   /* 8 (Trigger level 2 (=8)) */
#define U0IIR_IIRFE_FOURTEEN       0x03   /* 14 (Trigger level 3 (=14)) */

#define U0IIR_IID                  0x0e   /* Bit 3-1: IID (Interrupt identification) */
#define U0IIR_IID_THRE_INT         0x01   /* Transmit buffer empty interrupt (THRE) (Third priority) */
#define U0IIR_IID_CTI_INT          0x06   /* Character timeout interrupt (CTI) (Second priority) */
#define U0IIR_IID_RDA_INT          0x02   /* Receive data available or Trigger level interrupt code (RDA) (Second priority) */
#define U0IIR_IID_RX_LINE_INT      0x03   /* Receive line status interrupt (Highest priority) */

#define U0IIR_IP                   0x01   /* Bit 0: IP (Interrupt pending) */
#define U0IIR_IP_INTERRUPT         0x00   /* Interrupt pending  */
#define U0IIR_IP_NO_INTERRUPT      0x01   /* No pending interrupt */


/*
**---------------------------------------------------------------------------
**  UART0 FIFO Control Register
**---------------------------------------------------------------------------
*/

#define U0FCR_RTLS                 0xc0   /* Bit 7-6: RTLS (Receive FIFO trigger level) */
#define U0FCR_RTLS_ONE             0x00   /* 1 (Trigger level 0 (=1)) */
#define U0FCR_RTLS_FOUR            0x01   /* 4 (Trigger level 1 (=4)) */
#define U0FCR_RTLS_EIGHT           0x02   /* 8 (Trigger level 2 (=8)) */
#define U0FCR_RTLS_FOURTEEN        0x03   /* 14 (Trigger level 3 (=14)) */

#define U0FCR_TFR                  0x04   /* Bit 2: TFR (Clear transmit FIFO) */
#define U0FCR_TFR_NOTHING          0x00   /* Nothing happens */
#define U0FCR_TFR_RESET            0x01   /* Reset transfer pointers and clear TX FIFO */

#define U0FCR_RFR                  0x02   /* Bit 1: RFR (Clear receive FIFO) */
#define U0FCR_RFR_NOTHING          0x00   /* Nothing happens */
#define U0FCR_RFR_RESET            0x01   /* Reset receive pointers and clear RX FIFO */

#define U0FCR_FCRFE                0x01   /* Bit 0: FCRFE (FIFO enable) */
#define U0FCR_FCRFE_DISABLED       0x00   /* Disabled (Disabled FIFOs) */
#define U0FCR_FCRFE_ENABLED        0x01   /* Enabled (Enable TX and RX FIFOs) */


/*
**---------------------------------------------------------------------------
**  UART0 Line Control Register
**---------------------------------------------------------------------------
*/

#define U0LCR_DLAB                 0x80   /* Bit 7: DLAB (Divisor latch access bit) */
#define U0LCR_DLAB_TX_RX           0x00   /* Access transmit/receive registers */
#define U0LCR_DLAB_DIVISOR         0x01   /* Access divisor registers (Divisor used for baud rate generator ) */

#define U0LCR_BC                   0x40   /* Bit 6: BC (Break control) */
#define U0LCR_BC_DISABLED          0x00   /* Disabled (No break) */
#define U0LCR_BC_ENABLED           0x01   /* Enabled (Send continous 0 on transmit output) */

#define U0LCR_PS                   0x30   /* Bit 5-4: PS (Parity select) */
#define U0LCR_PS_ODD               0x00   /* Odd parity */
#define U0LCR_PS_EVEN              0x01   /* Even parity */
#define U0LCR_PS_FORCED_1          0x02   /* Forced "1" stick parity */
#define U0LCR_PS_FORCED_0          0x03   /* Forced "0" stick parity */

#define U0LCR_PE                   0x08   /* Bit 3: PE (Parity enable) */
#define U0LCR_PE_DISABLED          0x00   /* Disabled (No parity generation and checking) */
#define U0LCR_PE_ENABLED           0x01   /* Enabled (Parity generation and checking) */

#define U0LCR_SBS                  0x04   /* Bit 2: SBS (Stop bit select) */
#define U0LCR_SBS_S1               0x00   /* 1 stop bit */
#define U0LCR_SBS_S2               0x01   /* 2 stop bits ((=1.5 if 5 bit character length is used)) */

#define U0LCR_WLS                  0x03   /* Bit 1-0: WLS (Word length select) */
#define U0LCR_WLS_D5               0x00   /* 5 data bits */
#define U0LCR_WLS_D6               0x01   /* 6 data bits */
#define U0LCR_WLS_D7               0x02   /* 7 data bits */
#define U0LCR_WLS_D8               0x03   /* 8 data bits */


/*
**---------------------------------------------------------------------------
**  UART0 Line Status Register
**---------------------------------------------------------------------------
*/

#define U0LSR_RXFE                 0x80   /* Bit 7: RXFE (Receive error) */
#define U0LSR_RXFE_OK              0x00   /* No receive error in FIFO mode or Always 0 in non FIFO mode */
#define U0LSR_RXFE_ERROR           0x01   /* Parity, framing or break indication in the FIFO */

#define U0LSR_TEMT                 0x40   /* Bit 6: TEMT (Transmit empty) */
#define U0LSR_TEMT_TRANSMIT        0x00   /* Transmission in progress */
#define U0LSR_TEMT_IDLE            0x01   /* Transmitter idle */

#define U0LSR_THRE                 0x20   /* Bit 5: THRE (Transmit holding register empty) */
#define U0LSR_THRE_VALID           0x00   /* Valid data in transmit register */
#define U0LSR_THRE_EMPTY           0x01   /* Empty */

#define U0LSR_BI                   0x10   /* Bit 4: BI (Break indicator) */
#define U0LSR_BI_NO                0x00   /* No break */
#define U0LSR_BI_BREAK             0x01   /* Break condition detected on receive input line */

#define U0LSR_FE                   0x08   /* Bit 3: FE (Framing error) */
#define U0LSR_FE_OK                0x00   /* No framing error */
#define U0LSR_FE_ERROR             0x01   /* Framing error occured */