📄 ma_sfr.h
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**---------------------------------------------------------------------------
** Timer 0 Match Register 2
**---------------------------------------------------------------------------
*/
#define T0MR2_VALUE 0xffffffff /* Bit 31-0: VALUE (Timer match value) */
/*
**---------------------------------------------------------------------------
** Timer 0 Match Register 3
**---------------------------------------------------------------------------
*/
#define T0MR3_VALUE 0xffffffff /* Bit 31-0: VALUE (Timer match value) */
/*
**---------------------------------------------------------------------------
** Timer 0 Capture Control Register
**---------------------------------------------------------------------------
*/
#define T0CCR_CAP2INT 0x100 /* Bit 8: CAP2INT (Interrupt on capture CAP2) */
#define T0CCR_CAP2INT_DISABLED 0x00 /* Disabled */
#define T0CCR_CAP2INT_ENABLED 0x01 /* Enabled */
#define T0CCR_CAP2FE 0x80 /* Bit 7: CAP2FE (Capture on CAP2 falling edge) */
#define T0CCR_CAP2FE_DISABLED 0x00 /* Disabled */
#define T0CCR_CAP2FE_ENABLED 0x01 /* Enabled */
#define T0CCR_CAP2RE 0x40 /* Bit 6: CAP2RE (Capture on CAP2 rising edge) */
#define T0CCR_CAP2RE_DISABLED 0x00 /* Disabled */
#define T0CCR_CAP2RE_ENABLED 0x01 /* Enabled */
#define T0CCR_CAP1INT 0x20 /* Bit 5: CAP1INT (Interrupt on capture CAP1) */
#define T0CCR_CAP1INT_DISABLED 0x00 /* Disabled */
#define T0CCR_CAP1INT_ENABLED 0x01 /* Enabled */
#define T0CCR_CAP1FE 0x10 /* Bit 4: CAP1FE (Capture on CAP1 falling edge) */
#define T0CCR_CAP1FE_DISABLED 0x00 /* Disabled */
#define T0CCR_CAP1FE_ENABLED 0x01 /* Enabled */
#define T0CCR_CAP1RE 0x08 /* Bit 3: CAP1RE (Capture on CAP1 rising edge) */
#define T0CCR_CAP1RE_DISABLED 0x00 /* Disabled */
#define T0CCR_CAP1RE_ENABLED 0x01 /* Enabled */
#define T0CCR_CAP0INT 0x04 /* Bit 2: CAP0INT (Interrupt on capture CAP0) */
#define T0CCR_CAP0INT_DISABLED 0x00 /* Disabled */
#define T0CCR_CAP0INT_ENABLED 0x01 /* Enabled */
#define T0CCR_CAP0FE 0x02 /* Bit 1: CAP0FE (Capture on CAP0 falling edge) */
#define T0CCR_CAP0FE_DISABLED 0x00 /* Disabled */
#define T0CCR_CAP0FE_ENABLED 0x01 /* Enabled */
#define T0CCR_CAP0RE 0x01 /* Bit 0: CAP0RE (Capture on CAP0 rising edge) */
#define T0CCR_CAP0RE_DISABLED 0x00 /* Disabled */
#define T0CCR_CAP0RE_ENABLED 0x01 /* Enabled */
/*
**---------------------------------------------------------------------------
** Timer 0 Capture Register 0
**---------------------------------------------------------------------------
*/
#define T0CR0_VALUE 0xffffffff /* Bit 31-0: VALUE (Timer capture value) */
/*
**---------------------------------------------------------------------------
** Timer 0 Capture Register 1
**---------------------------------------------------------------------------
*/
#define T0CR1_VALUE 0xffffffff /* Bit 31-0: VALUE (Timer capture value) */
/*
**---------------------------------------------------------------------------
** Timer 0 Capture Register 2
**---------------------------------------------------------------------------
*/
#define T0CR2_VALUE 0xffffffff /* Bit 31-0: VALUE (Timer capture value) */
/*
**---------------------------------------------------------------------------
** Timer 0 Capture Register 3
**---------------------------------------------------------------------------
*/
#define T0CR3_VALUE 0xffffffff /* Bit 31-0: VALUE (Timer capture value) */
/*
**---------------------------------------------------------------------------
** Timer 0 External Match Register
**---------------------------------------------------------------------------
*/
#define T0EMR_EMC2 0x300 /* Bit 9-8: EMC2 (External match control 2) */
#define T0EMR_EMC2_NOTHING 0x00 /* Do nothing */
#define T0EMR_EMC2_CLEAR 0x01 /* Clear output to 0 */
#define T0EMR_EMC2_SET 0x02 /* Set output to 1 */
#define T0EMR_EMC2_TOGGLE 0x03 /* Toggle output */
#define T0EMR_EMC1 0xc0 /* Bit 7-6: EMC1 (External match control 1) */
#define T0EMR_EMC1_NOTHING 0x00 /* Do nothing */
#define T0EMR_EMC1_CLEAR 0x01 /* Clear output to 0 */
#define T0EMR_EMC1_SET 0x02 /* Set output to 1 */
#define T0EMR_EMC1_TOGGLE 0x03 /* Toggle output */
#define T0EMR_EMC0 0x30 /* Bit 5-4: EMC0 (External match control 0) */
#define T0EMR_EMC0_NOTHING 0x00 /* Do nothing */
#define T0EMR_EMC0_CLEAR 0x01 /* Clear output to 0 */
#define T0EMR_EMC0_SET 0x02 /* Set output to 1 */
#define T0EMR_EMC0_TOGGLE 0x03 /* Toggle output */
#define T0EMR_EM2 0x04 /* Bit 2: EM2 (External match 2) */
#define T0EMR_EM2_LOW 0x00 /* Low */
#define T0EMR_EM2_HIGH 0x01 /* High */
#define T0EMR_EM1 0x02 /* Bit 1: EM1 (External match 1) */
#define T0EMR_EM1_LOW 0x00 /* Low */
#define T0EMR_EM1_HIGH 0x01 /* High */
#define T0EMR_EM0 0x01 /* Bit 0: EM0 (External match 0) */
#define T0EMR_EM0_LOW 0x00 /* Low */
#define T0EMR_EM0_HIGH 0x01 /* High */
/*
**---------------------------------------------------------------------------
** Timer 1 Interrupt Register
**---------------------------------------------------------------------------
*/
#define T1IR_CR3INT 0x80 /* Bit 7: CR3INT (Interrupt flag for capture channel 3) */
#define T1IR_CR3INT_NO_INTERRUPT 0x00 /* No interrupt */
#define T1IR_CR3INT_INTERRUPT 0x01 /* Interrupt */
#define T1IR_CR2INT 0x40 /* Bit 6: CR2INT (Interrupt flag for capture channel 2) */
#define T1IR_CR2INT_NO_INTERRUPT 0x00 /* No interrupt */
#define T1IR_CR2INT_INTERRUPT 0x01 /* Interrupt */
#define T1IR_CR1INT 0x20 /* Bit 5: CR1INT (Interrupt flag for capture channel 1) */
#define T1IR_CR1INT_NO_INTERRUPT 0x00 /* No interrupt */
#define T1IR_CR1INT_INTERRUPT 0x01 /* Interrupt */
#define T1IR_CR0INT 0x10 /* Bit 4: CR0INT (Interrupt flag for capture channel 0) */
#define T1IR_CR0INT_NO_INTERRUPT 0x00 /* No interrupt */
#define T1IR_CR0INT_INTERRUPT 0x01 /* Interrupt */
#define T1IR_MR3INT 0x08 /* Bit 3: MR3INT (Interrupt flag for match channel 3) */
#define T1IR_MR3INT_NO_INTERRUPT 0x00 /* No interrupt */
#define T1IR_MR3INT_INTERRUPT 0x01 /* Interrupt */
#define T1IR_MR2INT 0x04 /* Bit 2: MR2INT (Interrupt flag for match channel 2) */
#define T1IR_MR2INT_NO_INTERRUPT 0x00 /* No interrupt */
#define T1IR_MR2INT_INTERRUPT 0x01 /* Interrupt */
#define T1IR_MR1INT 0x02 /* Bit 1: MR1INT (Interrupt flag for match channel 1) */
#define T1IR_MR1INT_NO_INTERRUPT 0x00 /* No interrupt */
#define T1IR_MR1INT_INTERRUPT 0x01 /* Interrupt */
#define T1IR_MR0INT 0x01 /* Bit 0: MR0INT (Interrupt flag for match channel 0) */
#define T1IR_MR0INT_NO_INTERRUPT 0x00 /* No interrupt */
#define T1IR_MR0INT_INTERRUPT 0x01 /* Interrupt */
/*
**---------------------------------------------------------------------------
** Timer 1 Timer Control Register
**---------------------------------------------------------------------------
*/
#define T1TCR_CR 0x02 /* Bit 1: CR (Counter reset) */
#define T1TCR_CR_NO_RESET 0x00 /* No reset */
#define T1TCR_CR_RESET 0x01 /* Generate reset */
#define T1TCR_CE 0x01 /* Bit 0: CE (Counter enable) */
#define T1TCR_CE_DISABLED 0x00 /* Disabled */
#define T1TCR_CE_ENABLED 0x01 /* Enabled */
/*
**---------------------------------------------------------------------------
** Timer 1 Timer Counter
**---------------------------------------------------------------------------
*/
#define T1TC_VALUE 0xffffffff /* Bit 31-0: VALUE (Timer counter value) */
/*
**---------------------------------------------------------------------------
** Timer 1 Prescale Register
**---------------------------------------------------------------------------
*/
#define T1PR_VALUE 0xffffffff /* Bit 31-0: VALUE (Timer prescaler max value) */
/*
**---------------------------------------------------------------------------
** Timer 1 Prescale Counter
**---------------------------------------------------------------------------
*/
#define T1PC_VALUE 0xffffffff /* Bit 31-0: VALUE (Timer prescale counter value) */
/*
**---------------------------------------------------------------------------
** Timer 1 Match Control Register
**---------------------------------------------------------------------------
*/
#define T1MCR_MR3STOP 0x800 /* Bit 11: MR3STOP (Stop on MR3) */
#define T1MCR_MR3STOP_DISABLED 0x00 /* Disabled */
#define T1MCR_MR3STOP_ENABLED 0x01 /* Enabled */
#define T1MCR_MR3RES 0x400 /* Bit 10: MR3RES (Reset on MR3) */
#define T1MCR_MR3RES_DISABLED 0x00 /* Disabled */
#define T1MCR_MR3RES_ENABLED 0x01 /* Enabled */
#define T1MCR_MR3INT 0x200 /* Bit 9: MR3INT (Interrupt on MR3) */
#define T1MCR_MR3INT_DISABLED 0x00 /* Disabled */
#define T1MCR_MR3INT_ENABLED 0x01 /* Enabled */
#define T1MCR_MR2STOP 0x100 /* Bit 8: MR2STOP (Stop on MR2) */
#define T1MCR_MR2STOP_DISABLED 0x00 /* Disabled */
#define T1MCR_MR2STOP_ENABLED 0x01 /* Enabled */
#define T1MCR_MR2RES 0x80 /* Bit 7: MR2RES (Reset on MR2) */
#define T1MCR_MR2RES_DISABLED 0x00 /* Disabled */
#define T1MCR_MR2RES_ENABLED 0x01 /* Enabled */
#define T1MCR_MR2INT 0x40 /* Bit 6: MR2INT (Interrupt on MR2) */
#define T1MCR_MR2INT_DISABLED 0x00 /* Disabled */
#define T1MCR_MR2INT_ENABLED 0x01 /* Enabled */
#define T1MCR_MR1STOP 0x20 /* Bit 5: MR1STOP (Stop on MR1) */
#define T1MCR_MR1STOP_DISABLED 0x00 /* Disabled */
#define T1MCR_MR1STOP_ENABLED 0x01 /* Enabled */
#define T1MCR_MR1RES 0x10 /* Bit 4: MR1RES (Reset on MR1) */
#define T1MCR_MR1RES_DISABLED 0x00 /* Disabled */
#define T1MCR_MR1RES_ENABLED 0x01 /* Enabled */
#define T1MCR_MR1INT 0x08 /* Bit 3: MR1INT (Interrupt on MR1) */
#define T1MCR_MR1INT_DISABLED 0x00 /* Disabled */
#define T1MCR_MR1INT_ENABLED 0x01 /* Enabled */
#define T1MCR_MR0STOP 0x04 /* Bit 2: MR0STOP (Stop on MR0) */
#define T1MCR_MR0STOP_DISABLED 0x00 /* Disabled */
#define T1MCR_MR0STOP_ENABLED 0x01 /* Enabled */
#define T1MCR_MR0RES 0x02 /* Bit 1: MR0RES (Reset on MR0) */
#define T1MCR_MR0RES_DISABLED 0x00 /* Disabled */
#define T1MCR_MR0RES_ENABLED 0x01 /* Enabled */
#define T1MCR_MR0INT 0x01 /* Bit 0: MR0INT (Interrupt on MR0) */
#define T1MCR_MR0INT_DISABLED 0x00 /* Disabled */
#define T1MCR_MR0INT_ENABLED 0x01 /* Enabled */
/*
**---------------------------------------------------------------------------
** Timer 1 Match Register 0
**---------------------------------------------------------------------------
*/
#define T1MR0_VALUE 0xffffffff /* Bit 31-0: VALUE (Timer match value) */
/*
**---------------------------------------------------------------------------
** Timer 1 Match Register 1
**---------------------------------------------------------------------------
*/
#define T1MR1_VALUE 0xffffffff /* Bit 31-0: VALUE (Timer match value) */
/*
**---------------------------------------------------------------------------
** Timer 1 Match Register 2
**---------------------------------------------------------------------------
*/
#define T1MR2_VALUE 0xffffffff /* Bit 31-0: VALUE (Timer match value) */
/*
**---------------------------------------------------------------------------
** Timer 1 Match Register 3
**---------------------------------------------------------------------------
*/
#define T1MR3_VALUE 0xffffffff /* Bit 31-0: VALUE (Timer match value) */
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