rtosinit_lpc2xxx.c

NXP LPC系列AMR7的开发程序源码（LCD

/*********************************************************************
 *
 *  IAR PowerPac - RTOS
 *
 *  (c) Copyright IAR Systems 2006.  All rights reserved.
 *
**********************************************************************
----------------------------------------------------------------------
File    : RTOSInit_LPC2xxx.c   (for Philips LPC2xxx CPUs)
Purpose : Initializes and handles the hardware for the OS as far
          as required by the OS.
          Feel free to modify this file acc. to your
          target system.
--------  END-OF-HEADER  ---------------------------------------------
*/

#include "RTOS.H"

/*********************************************************************
*
*       Configuration
*
*********************************************************************/

#include "OS_Config.h"

/*********************************************************************
*
*       Clock frequency settings
*/

#ifndef OS_FSYS                     /* CPU main clock freqeuncy     */
  #define OS_FSYS 4000000L          /* may depend on PLL            */
#endif

#ifndef OS_PCLK_TIMER               /* Peripheral clock for timer   */
  #define OS_PCLK_TIMER OS_FSYS/4   /* defaults to CPU clock / 4    */
#endif

#ifndef OS_PCLK_UART                /* Peripheral clock for UART    */
  #define OS_PCLK_UART OS_FSYS/4    /* defaults to CPU clock / 4    */
#endif

#ifndef OS_INIT_PLL                 /* PLL may be initialized       */
  #define OS_INIT_PLL 0             /* during startup               */
#endif

#ifndef OS_INIT_MAM                 /* Memory accelerator           */
  #define OS_INIT_MAM 1             /* initialized per default      */
#endif

/****** OS internal timing settings *********************************/

#define _OS_TIMER_INTERVAL (OS_PCLK_TIMER/TICK_PER_SEC)

#if OS_INIT_MAM                     /* Define timer value for MAM   */
  #if   (OS_FSYS < 2000000)
    #define _OS_MAMTIM_VALUE    1
  #elif (OS_FSYS < 4000000)
    #define _OS_MAMTIM_VALUE    2
  #else
    #define _OS_MAMTIM_VALUE    3
  #endif
#endif

/*********************************************************************
*
*       UART settings for OSView
*       If you do not want (or can not due to hardware limitations)
*       to dedicate a UART to OSView, please define it to be -1
*       Currently the standard code enables UART 1 per default
*       and supports UART0 to UART1
*/

#ifndef OS_UART
  #define OS_UART 1
#endif
#ifndef OS_BAUDRATE
  #define OS_BAUDRATE 38400L
#endif

/****** Define behavior of undefined interrupt handling *************/

#ifndef OS_IGNORE_UNDEFINED_INTERRUPT
  #define OS_IGNORE_UNDEFINED_INTERRUPT 0
#endif

/****** End of configuration settings *******************************/

#define OS_UART_USED ((OS_UART == 0) || (OS_UART == 1))

/*********************************************************************
*
*       Local defines (sfrs used in RTOSInit.c)
*
**********************************************************************
*/

/****** UART sfdr definition ****************************************/
/****** UART0 *******************************************************/

#define __UART0_BASE   0xE000C000
#define __UART1_BASE   0xE0010000

#define __UART_RBR_OFFS    0x00
#define __UART_THR_OFFS    0x00
#define __UART_IER_OFFS    0x04
#define __UART_IIR_OFFS    0x08
#define __UART_FCR_OFFS    0x08
#define __UART_LCR_OFFS    0x0C
#define __UART_LSR_OFFS    0x14
#define __UART_SCR_OFFS    0x1C
#define __UART_DLL_OFFS    0x00
#define __UART_DLM_OFFS    0x04

/****** Assign UART sfrs used for OSView communication ***********/

#if OS_UART_USED
  #if   (OS_UART == 0)
    #define _OS_UART_BASE __UART0_BASE
    #define _OS_UART_INT_SOURCE    6
    #define _UART_PCONP_BIT        3
    #define _PINSEL_UART_MODE      ((1 << 0) | (1 << 2))
 #elif (OS_UART == 1)
    #define _OS_UART_BASE __UART1_BASE
    #define _OS_UART_INT_SOURCE    7
    #define _UART_PCONP_BIT        4
    #define _PINSEL_UART_MODE      ((1 << 16) | (1 << 18))
  #endif

  #define _OS_UART_RBR   *(volatile OS_U8*)(_OS_UART_BASE + __UART_RBR_OFFS)
  #define _OS_UART_THR   *(volatile OS_U8*)(_OS_UART_BASE + __UART_THR_OFFS)
  #define _OS_UART_IER   *(volatile OS_U8*)(_OS_UART_BASE + __UART_IER_OFFS)
  #define _OS_UART_IIR   *(volatile OS_U8*)(_OS_UART_BASE + __UART_IIR_OFFS)
  #define _OS_UART_FCR   *(volatile OS_U8*)(_OS_UART_BASE + __UART_FCR_OFFS)
  #define _OS_UART_LCR   *(volatile OS_U8*)(_OS_UART_BASE + __UART_LCR_OFFS)
  #define _OS_UART_LSR   *(volatile OS_U8*)(_OS_UART_BASE + __UART_LSR_OFFS)
  #define _OS_UART_SCR   *(volatile OS_U8*)(_OS_UART_BASE + __UART_SCR_OFFS)
  #define _OS_UART_DLL   *(volatile OS_U8*)(_OS_UART_BASE + __UART_DLL_OFFS)
  #define _OS_UART_DLM   *(volatile OS_U8*)(_OS_UART_BASE + __UART_DLM_OFFS)

  #define _RX_FULL_INT_ENABLE_BIT  0
  #define _TX_EMPTY_INT_ENABLE_BIT 1
  #define _RX_ERROR_INT_ENABLE_BIT 2
  #define _INT_PENDING_BIT         0

  #define _UART_INT_MASK         0x0E
  #define _UART_ERROR_INT_STATUS 0x06
  #define _UART_RX_INT_STATUS    0x04
  #define _UART_TX_INT_STATUS    0x02
#endif    /* OS_UART_USED  */

/****** Port, port mode settings ************************************/

#define __PINSEL0      *(volatile OS_U32*)0xE002C000

/****** Power, reset clock control unit register ********************/

#define __PLLCON       *(volatile OS_U32*)0xE01FC080
#define __PLLCFG       *(volatile OS_U32*)0xE01FC084
#define __PLLSTAT      *(volatile OS_U32*)0xE01FC088
#define __PLLFEED      *(volatile OS_U32*)0xE01FC08C
#define __PCON         *(volatile OS_U32*)0xE01FC0C0
#define __PCONP        *(volatile OS_U32*)0xE01FC0C4
#define __VPBDIV       *(volatile OS_U32*)0xE01FC100

/****** PLL and memeory timing **************************************/

#define __MAMCR       *(volatile OS_U32*)(0xE01FC000)
#define __MAMTIM      *(volatile OS_U32*)(0xE01FC004)


/****** Timer sfr definition ****************************************/

#define __TIM0_BASE     0xE0004000
#define __TIM1_BASE     0xE0008000

#define __TIM_IR_OFFS   0x00
#define __TIM_TCR_OFFS  0x04
#define __TIM_TC_OFFS   0x08
#define __TIM_PR_OFFS   0x0C
#define __TIM_MCR_OFFS  0x14
#define __TIM_MR0_OFFS  0x18

/****** Assign timer sfrs used for OS timer *************************/
/****** initially, we use timer 0        ****************************/

#define _OS_TIM_BASE        __TIM0_BASE
#define _OS_TIM_IR_BIT          0  // Used to reset timer interrupt (Timer IR register), Match channel 0
#define _OS_TIMER_INT_SOURCE    4  // Channel number of timer input t0 VIC
#define _TIMER_PCONP_BIT   1

#define _OS_TIM_IR       *(volatile OS_U32*)(_OS_TIM_BASE + __TIM_IR_OFFS)
#define _OS_TIM_TCR      *(volatile OS_U32*)(_OS_TIM_BASE + __TIM_TCR_OFFS)
#define _OS_TIM_TC       *(volatile OS_U32*)(_OS_TIM_BASE + __TIM_TC_OFFS)
#define _OS_TIM_PR       *(volatile OS_U32*)(_OS_TIM_BASE + __TIM_PR_OFFS)
#define _OS_TIM_MCR      *(volatile OS_U32*)(_OS_TIM_BASE + __TIM_MCR_OFFS)
#define _OS_TIM_MR0      *(volatile OS_U32*)(_OS_TIM_BASE + __TIM_MR0_OFFS)

/****** Vectored interrupt controller (VIC) *************************/

#define __VIC_BASE  0xFFFFF000

#define __VIC_IRQSTATUS       *(volatile OS_U32*)(__VIC_BASE + 0x0000)
#define __VIC_FIQSTATUS       *(volatile OS_U32*)(__VIC_BASE + 0x0004)
#define __VIC_RAWINTERRUPT    *(volatile OS_U32*)(__VIC_BASE + 0x0008)
#define __VIC_INTSELECT       *(volatile OS_U32*)(__VIC_BASE + 0x000C)
#define __VIC_INTENABLE       *(volatile OS_U32*)(__VIC_BASE + 0x0010)
#define __VIC_INTENABLECLEAR  *(volatile OS_U32*)(__VIC_BASE + 0x0014)
#define __VIC_SOFTINT         *(volatile OS_U32*)(__VIC_BASE + 0x0018)
#define __VIC_SOFTINTCLEAR    *(volatile OS_U32*)(__VIC_BASE + 0x001C)
#define __VIC_VECTORADDR      *(volatile OS_U32*)(__VIC_BASE + 0x0030)
#define __VIC_DEFVECTADDR     *(volatile OS_U32*)(__VIC_BASE + 0x0034)

#define __VIC_VECT_BASE       *(volatile OS_U32*)(__VIC_BASE + 0x0100)
#define __VIC_VECTCNTL_BASE   *(volatile OS_U32*)(__VIC_BASE + 0x0200)

#define _NUM_INT_SOURCES  32      // Maximum number of sources. Specific devices may support less
#define _INT_SOURCE_MASK  0x1F

#ifndef _NUM_INT_VECTORS
  #define _NUM_INT_VECTORS  16
#endif

#define _OS_TIMER_INT_INDEX    15 // Assign to lowest priority interrupt channel
#define _OS_UART_INT_INDEX     14 // Assign to low priority interrupt channel

#define __PCON_IDL            (1UL<<0)
/*********************************************************************
*
*       Static data
*
**********************************************************************
*/

static volatile OS_U32 _Dummy;

/*********************************************************************
*
*       Local functions
*
**********************************************************************
*/

/*********************************************************************
*
*       _Init_VIC()
*
* Function description
*   Clears and disables all interrut vectors in VIC.
*/

static void _Init_VIC(void) {
  int Index;

  __VIC_INTENABLECLEAR = 0xFFFFFFFF;            // Disable all source interrupts
  __VIC_VECTORADDR     = 0;                     // Write to vector, reset VIC
  for (Index = 0; Index < _NUM_INT_VECTORS; Index++) {
    OS_ARM_DisableISR(Index);                   // Disable channel
    OS_ARM_AssignISRSource(Index, 0);           // Assign to hardware channel 0
    OS_ARM_InstallISRHandler(Index, NULL);      // Set vector to 0;
  }
  __VIC_SOFTINTCLEAR   = 0xFFFFFFFF;            // Disable all soft interrupts
  __VIC_INTSELECT      = 0;                     // Set all channels to generate IRQ
  __VIC_DEFVECTADDR    = 0;                     // Set default vector to 0
}

/*********************************************************************
*
*       OS_ISR_Tick() interrupt Handler
*/
static void _OS_ISR_Tick(void) {
  _OS_TIM_IR = (1 << _OS_TIM_IR_BIT);  // Clear OS timer interrupt flag
  OS_HandleTick();                     // Call OS tick handler
}

/*********************************************************************
*
*       Global functions
*
**********************************************************************
*/

/*********************************************************************
*
*       __low_level_init()
*
* Function description
*   Called from startup code.
*   Used to initialize PLL and memory accelerator as early as possible
*/
OS_INTERWORK int __low_level_init(void);       /* Avoid "No prototype" warning */
OS_INTERWORK int __low_level_init(void) {
  __PCONP = 0;  // disable all peripherals
  #if OS_INIT_PLL
    OS_InitPLL();
  #else
    #ifndef NDEBUG
      __PLLCON  =  0;          // Disable PLL
      __PLLFEED =  0xAA;       // Update PLL configuration
      __PLLFEED =  0x55;
    #endif
  #endif
  #if OS_INIT_MAM                 // Speedup CPU
    __MAMCR  = 0x00;              // Disable Memory accelerator module
    __MAMTIM = _OS_MAMTIM_VALUE;  // Depends on OS_FSYS
    __MAMCR  = 0x02;              // Fully enable Memory accelerator module
  #endif
  __VPBDIV = 0;                   // pclk = cclk/4
  return 1;                       // Always initialize segments !
};

/*********************************************************************
*
*       OS_InitPLL
*
* Function description
*   Initialize PLL
*   WARNING: Improper settings may lock CPU
*   Please examine whether init sequence fits your harware configuration
*   We assume a CPU running with external oscillator which is multilied by four
*   which is allowed for a maximum external frequency of 15MHz
*/
OS_INTERWORK void OS_InitPLL(void) {
  __PLLCFG  =  0x03        // => Multiplication value = 4
             |(0x01 << 5); // => P Value = 2
  __PLLCON  =  (1 << 0);   // Enable PLL
  __PLLFEED =  0xAA;       // Update PLL configuration
  __PLLFEED =  0x55;
  do {
  } while ((__PLLSTAT & (1 << 10)) == 0); // wait until PLL is locked (bit 10 is set)
  __PLLCON  = (1 << 0) | (1 << 1);        // Enable PLL and select as clock source
  __PLLFEED =  0xAA;                      // Update Pll register
  __PLLFEED =  0x55;