📄 ma_sfr.h
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/*
*****************************************************************************
**
** Project : My project
**
** Component : LPC2106 (LPC2106)
**
** Module name : Support files
**
** File name : ma_sfr.h
**
** Abstract : This file implements the automatically generated
** register and bit field addressing macro definitions.
**
** Date : 2004-05-26 17:21:26
**
** License no. : 9503-663-863-6224 Ivan
**
** Warning : This file has been automatically generated.
** Do not edit this file if you intend to regenerate it.
**
** This file was created by IAR MakeApp version
** 4.02A (NXP LPC210x: 4.00C) for the NXP LPC210x component series.
**
** (c)Copyright 2001-2003 IAR Systems.
** Your rights to this file are explained in the IAR MakeApp
** License Agreement. All other rights reserved.
**
*****************************************************************************
*/
/*
**===========================================================================
** 1 GENERAL
** 1.1 Revisions
**
**
**
**===========================================================================
*/
/*
**===========================================================================
** 1.2 References
**
** No Identification Name or Description
** == ============== =====================
**
**===========================================================================
*/
/*
**===========================================================================
** 1.3 Re-definition guard
**===========================================================================
*/
/*--- Avoid including this file more than once ---*/
#ifndef MA_SFR_DEFINED
#define MA_SFR_DEFINED
/*
**===========================================================================
** 2. INCLUDE FILES
** 2.1 Standard include files
**===========================================================================
*/
/*
**===========================================================================
** 2.2 Application include files
**===========================================================================
*/
/*--- Include the target specific header file ---*/
#include "ma_tgt.h"
/*
**===========================================================================
** 3. DECLARATIONS
** 3.1 Global constants
**===========================================================================
*/
/*
**===========================================================================
** 3.2 Global macros
**===========================================================================
*/
#ifndef MA_UNSIGNED_CHAR
#define MA_UNSIGNED_CHAR *(volatile unsigned char *)
#endif
#ifndef MA_UNSIGNED_SHORT
#define MA_UNSIGNED_SHORT *(volatile unsigned short *)
#endif
#ifndef MA_UNSIGNED_LONG
#define MA_UNSIGNED_LONG *(volatile unsigned long *)
#endif
/*
**---------------------------------------------------------------------------
** Watchdog Mode Register
**---------------------------------------------------------------------------
*/
#define WDMOD_WDINT 0x08 /* Bit 3: WDINT (Watchdog interrupt flag (Read Only)) */
#define WDMOD_WDINT_NO_INTERRUPT 0x00 /* No interrupt */
#define WDMOD_WDINT_INTERRUPT 0x01 /* Interrupt */
#define WDMOD_WDTOF 0x04 /* Bit 2: WDTOF (Watchdog time-out flag) */
#define WDMOD_WDTOF_NO_TIME_OUT 0x00 /* No time-out */
#define WDMOD_WDTOF_TIME_OUT 0x01 /* Time-out */
#define WDMOD_WDRESET 0x02 /* Bit 1: WDRESET (Watchdog reset enable bit (Set Only)) */
#define WDMOD_WDRESET_INTERRUPT 0x00 /* Disabled */
#define WDMOD_WDRESET_WDRESET 0x01 /* Enabled */
#define WDMOD_WDEN 0x01 /* Bit 0: WDEN (Watchdog interrupt enable bit (Set only)) */
#define WDMOD_WDEN_STOPPED 0x00 /* Disabled */
#define WDMOD_WDEN_RUNNING 0x01 /* Enabled (Watchdog interrupt enabled) */
/*
**---------------------------------------------------------------------------
** Watchdog Timer Constant Register
**---------------------------------------------------------------------------
*/
#define WDTC_COUNT 0xffffffff /* Bit 31-0: COUNT (Watchdog time-out interval) */
/*
**---------------------------------------------------------------------------
** Watchdog Feed Sequence Register
**---------------------------------------------------------------------------
*/
#define WDFEED_FEED 0xff /* Bit 7-0: FEED (Watchdog feed) */
/*
**---------------------------------------------------------------------------
** Watchdog Timer Value Register
**---------------------------------------------------------------------------
*/
#define WDTV_COUNT 0xffffffff /* Bit 31-0: COUNT (Watchdog time-out interval) */
/*
**---------------------------------------------------------------------------
** Timer 0 Interrupt Register
**---------------------------------------------------------------------------
*/
#define T0IR_CR2INT 0x40 /* Bit 6: CR2INT (Interrupt flag for capture channel 2) */
#define T0IR_CR2INT_NO_INTERRUPT 0x00 /* No interrupt */
#define T0IR_CR2INT_INTERRUPT 0x01 /* Interrupt */
#define T0IR_CR1INT 0x20 /* Bit 5: CR1INT (Interrupt flag for capture channel 1) */
#define T0IR_CR1INT_NO_INTERRUPT 0x00 /* No interrupt */
#define T0IR_CR1INT_INTERRUPT 0x01 /* Interrupt */
#define T0IR_CR0INT 0x10 /* Bit 4: CR0INT (Interrupt flag for capture channel 0) */
#define T0IR_CR0INT_NO_INTERRUPT 0x00 /* No interrupt */
#define T0IR_CR0INT_INTERRUPT 0x01 /* Interrupt */
#define T0IR_MR3INT 0x08 /* Bit 3: MR3INT (Interrupt flag for match channel 3) */
#define T0IR_MR3INT_NO_INTERRUPT 0x00 /* No interrupt */
#define T0IR_MR3INT_INTERRUPT 0x01 /* Interrupt */
#define T0IR_MR2INT 0x04 /* Bit 2: MR2INT (Interrupt flag for match channel 2) */
#define T0IR_MR2INT_NO_INTERRUPT 0x00 /* No interrupt */
#define T0IR_MR2INT_INTERRUPT 0x01 /* Interrupt */
#define T0IR_MR1INT 0x02 /* Bit 1: MR1INT (Interrupt flag for match channel 1) */
#define T0IR_MR1INT_NO_INTERRUPT 0x00 /* No interrupt */
#define T0IR_MR1INT_INTERRUPT 0x01 /* Interrupt */
#define T0IR_MR0INT 0x01 /* Bit 0: MR0INT (Interrupt flag for match channel 0) */
#define T0IR_MR0INT_NO_INTERRUPT 0x00 /* No interrupt */
#define T0IR_MR0INT_INTERRUPT 0x01 /* Interrupt */
/*
**---------------------------------------------------------------------------
** Timer 0 Timer Control Register
**---------------------------------------------------------------------------
*/
#define T0TCR_CR 0x02 /* Bit 1: CR (Counter reset) */
#define T0TCR_CR_NO_RESET 0x00 /* No reset */
#define T0TCR_CR_RESET 0x01 /* Generate reset */
#define T0TCR_CE 0x01 /* Bit 0: CE (Counter enable) */
#define T0TCR_CE_DISABLED 0x00 /* Disabled */
#define T0TCR_CE_ENABLED 0x01 /* Enabled */
/*
**---------------------------------------------------------------------------
** Timer 0 Timer Counter
**---------------------------------------------------------------------------
*/
#define T0TC_VALUE 0xffffffff /* Bit 31-0: VALUE (Timer counter value) */
/*
**---------------------------------------------------------------------------
** Timer 0 Prescale Register
**---------------------------------------------------------------------------
*/
#define T0PR_VALUE 0xffffffff /* Bit 31-0: VALUE (Timer prescaler max value) */
/*
**---------------------------------------------------------------------------
** Timer 0 Prescale Counter
**---------------------------------------------------------------------------
*/
#define T0PC_VALUE 0xffffffff /* Bit 31-0: VALUE (Timer prescale counter value) */
/*
**---------------------------------------------------------------------------
** Timer 0 Match Control Register
**---------------------------------------------------------------------------
*/
#define T0MCR_MR3STOP 0x800 /* Bit 11: MR3STOP (Stop on MR3) */
#define T0MCR_MR3STOP_DISABLED 0x00 /* Disabled */
#define T0MCR_MR3STOP_ENABLED 0x01 /* Enabled */
#define T0MCR_MR3RES 0x400 /* Bit 10: MR3RES (Reset on MR3) */
#define T0MCR_MR3RES_DISABLED 0x00 /* Disabled */
#define T0MCR_MR3RES_ENABLED 0x01 /* Enabled */
#define T0MCR_MR3INT 0x200 /* Bit 9: MR3INT (Interrupt on MR3) */
#define T0MCR_MR3INT_DISABLED 0x00 /* Disabled */
#define T0MCR_MR3INT_ENABLED 0x01 /* Enabled */
#define T0MCR_MR2STOP 0x100 /* Bit 8: MR2STOP (Stop on MR2) */
#define T0MCR_MR2STOP_DISABLED 0x00 /* Disabled */
#define T0MCR_MR2STOP_ENABLED 0x01 /* Enabled */
#define T0MCR_MR2RES 0x80 /* Bit 7: MR2RES (Reset on MR2) */
#define T0MCR_MR2RES_DISABLED 0x00 /* Disabled */
#define T0MCR_MR2RES_ENABLED 0x01 /* Enabled */
#define T0MCR_MR2INT 0x40 /* Bit 6: MR2INT (Interrupt on MR2) */
#define T0MCR_MR2INT_DISABLED 0x00 /* Disabled */
#define T0MCR_MR2INT_ENABLED 0x01 /* Enabled */
#define T0MCR_MR1STOP 0x20 /* Bit 5: MR1STOP (Stop on MR1) */
#define T0MCR_MR1STOP_DISABLED 0x00 /* Disabled */
#define T0MCR_MR1STOP_ENABLED 0x01 /* Enabled */
#define T0MCR_MR1RES 0x10 /* Bit 4: MR1RES (Reset on MR1) */
#define T0MCR_MR1RES_DISABLED 0x00 /* Disabled */
#define T0MCR_MR1RES_ENABLED 0x01 /* Enabled */
#define T0MCR_MR1INT 0x08 /* Bit 3: MR1INT (Interrupt on MR1) */
#define T0MCR_MR1INT_DISABLED 0x00 /* Disabled */
#define T0MCR_MR1INT_ENABLED 0x01 /* Enabled */
#define T0MCR_MR0STOP 0x04 /* Bit 2: MR0STOP (Stop on MR0) */
#define T0MCR_MR0STOP_DISABLED 0x00 /* Disabled */
#define T0MCR_MR0STOP_ENABLED 0x01 /* Enabled */
#define T0MCR_MR0RES 0x02 /* Bit 1: MR0RES (Reset on MR0) */
#define T0MCR_MR0RES_DISABLED 0x00 /* Disabled */
#define T0MCR_MR0RES_ENABLED 0x01 /* Enabled */
#define T0MCR_MR0INT 0x01 /* Bit 0: MR0INT (Interrupt on MR0) */
#define T0MCR_MR0INT_DISABLED 0x00 /* Disabled */
#define T0MCR_MR0INT_ENABLED 0x01 /* Enabled */
/*
**---------------------------------------------------------------------------
** Timer 0 Match Register 0
**---------------------------------------------------------------------------
*/
#define T0MR0_VALUE 0xffffffff /* Bit 31-0: VALUE (Timer match value) */
/*
**---------------------------------------------------------------------------
** Timer 0 Match Register 1
**---------------------------------------------------------------------------
*/
#define T0MR1_VALUE 0xffffffff /* Bit 31-0: VALUE (Timer match value) */
/*
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