xilinx_xup_v2p_v2_2_0.xbd

Xilinx ISE&EDK 8.2平台的人脸检测系统设计

  PORT SYSACE_CLK    = sysace_clk,     UCF_NET_STRING=("LOC=AH15", "PERIOD = 30000 ps", "IOSTANDARD = LVCMOS25") # Input CLK
  PORT SYSACE_MPA00  = sysace_mpa_0_,  UCF_NET_STRING=("LOC=AF21", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPA01  = sysace_mpa_1_,  UCF_NET_STRING=("LOC=AG21", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPA02  = sysace_mpa_2_,  UCF_NET_STRING=("LOC=AC19", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPA03  = sysace_mpa_3_,  UCF_NET_STRING=("LOC=AD19", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPA04  = sysace_mpa_4_,  UCF_NET_STRING=("LOC=AE22", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPA05  = sysace_mpa_5_,  UCF_NET_STRING=("LOC=AE21", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPA06  = sysace_mpa_6_,  UCF_NET_STRING=("LOC=AH22", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPD00  = sysace_mpd_0_,  UCF_NET_STRING=("LOC=AE15", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPD01  = sysace_mpd_1_,  UCF_NET_STRING=("LOC=AD15", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPD02  = sysace_mpd_2_,  UCF_NET_STRING=("LOC=AG14", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPD03  = sysace_mpd_3_,  UCF_NET_STRING=("LOC=AF14", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPD04  = sysace_mpd_4_,  UCF_NET_STRING=("LOC=AE14", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPD05  = sysace_mpd_5_,  UCF_NET_STRING=("LOC=AD14", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPD06  = sysace_mpd_6_,  UCF_NET_STRING=("LOC=AC15", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPD07  = sysace_mpd_7_,  UCF_NET_STRING=("LOC=AB15", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPD08  = sysace_mpd_8_,  UCF_NET_STRING=("LOC=AJ9", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPD09  = sysace_mpd_9_,  UCF_NET_STRING=("LOC=AH9", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPD10  = sysace_mpd_10_, UCF_NET_STRING=("LOC=AE10", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPD11  = sysace_mpd_11_, UCF_NET_STRING=("LOC=AE9", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPD12  = sysace_mpd_12_, UCF_NET_STRING=("LOC=AD12", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPD13  = sysace_mpd_13_, UCF_NET_STRING=("LOC=AC12", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPD14  = sysace_mpd_14_, UCF_NET_STRING=("LOC=AG10", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPD15  = sysace_mpd_15_, UCF_NET_STRING=("LOC=AF10", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPCE   = sysace_mpce,    UCF_NET_STRING=("LOC=AB16", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPOE   = sysace_mpoe,    UCF_NET_STRING=("LOC=AD17", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPWE   = sysace_mpwe,    UCF_NET_STRING=("LOC=AC16", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT SYSACE_MPIRQ  = sysace_mpirq,   UCF_NET_STRING=("LOC=AD16", "IOSTANDARD = LVCMOS25")

  # 4 LEDS
  PORT LED_0 = LED_0, UCF_NET_STRING=("LOC=AC4", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 12") 
  PORT LED_1 = LED_1, UCF_NET_STRING=("LOC=AC3", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 12")
  PORT LED_2 = LED_2, UCF_NET_STRING=("LOC=AA6", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 12")
  PORT LED_3 = LED_3, UCF_NET_STRING=("LOC=AA5", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 12")

  # 4 Dip Switchs
  PORT SW_0 = SW_0, UCF_NET_STRING=("LOC=AC11", "IOSTANDARD = LVCMOS25") 
  PORT SW_1 = SW_1, UCF_NET_STRING=("LOC=AD11", "IOSTANDARD = LVCMOS25") 
  PORT SW_2 = SW_2, UCF_NET_STRING=("LOC=AF8", "IOSTANDARD = LVCMOS25") 
  PORT SW_3 = SW_3, UCF_NET_STRING=("LOC=AF9", "IOSTANDARD = LVCMOS25") 

  # 5 Push Buttons
  PORT PB_ENTER = PB_ENTER, UCF_NET_STRING=("LOC=AG5", "IOSTANDARD = LVTTL")
  PORT PB_UP    = PB_UP, UCF_NET_STRING=("LOC=AH4", "IOSTANDARD = LVTTL")
  PORT PB_DOWN  = PB_DOWN, UCF_NET_STRING=("LOC=AG3", "IOSTANDARD = LVTTL")
  PORT PB_LEFT  = PB_LEFT, UCF_NET_STRING=("LOC=AH1", "IOSTANDARD = LVTTL")
  PORT PB_RIGHT = PB_RIGHT, UCF_NET_STRING=("LOC=AH2", "IOSTANDARD = LVTTL")

  # DDR SDRAM 64Mx64
  PORT DDR_CLK2   = ddr_1rank_2rank_clk_2_,       UCF_NET_STRING=("LOC=AB23", "IOSTANDARD = SSTL2_II")
  PORT DDR_CLK1   = ddr_1rank_2rank_clk_1_,       UCF_NET_STRING=("LOC=AD29", "IOSTANDARD = SSTL2_II")
  PORT DDR_CLK0   = ddr_1rank_2rank_clk_0_,       UCF_NET_STRING=("LOC=AC27", "IOSTANDARD = SSTL2_II")
  PORT DDR_CLKN2 = ddr_1rank_2rank_clk_n_2_,     UCF_NET_STRING=("LOC=AB24", "IOSTANDARD = SSTL2_II")
  PORT DDR_CLKN1 = ddr_1rank_2rank_clk_n_1_,     UCF_NET_STRING=("LOC=AD30", "IOSTANDARD = SSTL2_II")
  PORT DDR_CLKN0 = ddr_1rank_2rank_clk_n_0_,     UCF_NET_STRING=("LOC=AC28", "IOSTANDARD = SSTL2_II")
  PORT DDR_A12   = ddr_1rank_2rank_addr_12_,  UCF_NET_STRING=("LOC=M24", "IOSTANDARD = SSTL2_II")
  PORT DDR_A11   = ddr_1rank_2rank_addr_11_,  UCF_NET_STRING=("LOC=F30", "IOSTANDARD = SSTL2_II")
  PORT DDR_A10   = ddr_1rank_2rank_addr_10_,  UCF_NET_STRING=("LOC=F28", "IOSTANDARD = SSTL2_II")
  PORT DDR_A9    = ddr_1rank_2rank_addr_9_,   UCF_NET_STRING=("LOC=K24", "IOSTANDARD = SSTL2_II")
  PORT DDR_A8    = ddr_1rank_2rank_addr_8_,   UCF_NET_STRING=("LOC=J24", "IOSTANDARD = SSTL2_II")
  PORT DDR_A7    = ddr_1rank_2rank_addr_7_,   UCF_NET_STRING=("LOC=D26", "IOSTANDARD = SSTL2_II")
  PORT DDR_A6    = ddr_1rank_2rank_addr_6_,   UCF_NET_STRING=("LOC=G26", "IOSTANDARD = SSTL2_II")
  PORT DDR_A5    = ddr_1rank_2rank_addr_5_,   UCF_NET_STRING=("LOC=G25", "IOSTANDARD = SSTL2_II")
  PORT DDR_A4    = ddr_1rank_2rank_addr_4_,   UCF_NET_STRING=("LOC=K30", "IOSTANDARD = SSTL2_II")
  PORT DDR_A3    = ddr_1rank_2rank_addr_3_,   UCF_NET_STRING=("LOC=M29", "IOSTANDARD = SSTL2_II")
  PORT DDR_A2    = ddr_1rank_2rank_addr_2_,   UCF_NET_STRING=("LOC=L26", "IOSTANDARD = SSTL2_II")
  PORT DDR_A1    = ddr_1rank_2rank_addr_1_,   UCF_NET_STRING=("LOC=N25", "IOSTANDARD = SSTL2_II")
  PORT DDR_A0    = ddr_1rank_2rank_addr_0_,   UCF_NET_STRING=("LOC=M25", "IOSTANDARD = SSTL2_II")
  PORT DDR_BA0   = ddr_1rank_2rank_ba_0_,    UCF_NET_STRING=("LOC=M26", "IOSTANDARD = SSTL2_II")
  PORT DDR_BA1   = ddr_1rank_2rank_ba_1_,    UCF_NET_STRING=("LOC=K26", "IOSTANDARD = SSTL2_II")
  PORT DDR_CAS_N = ddr_1rank_2rank_cas_n,    UCF_NET_STRING=("LOC=L27", "IOSTANDARD = SSTL2_II")

  PORT DDR_RAS_N = ddr_1rank_2rank_ras_n,    UCF_NET_STRING=("LOC=N29", "IOSTANDARD = SSTL2_II")
  PORT DDR_WE_N  = ddr_1rank_2rank_we_n,     UCF_NET_STRING=("LOC=N26", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQM0 = ddr_1rank_2rank_dm_0_,     UCF_NET_STRING=("LOC=U26", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQM1 = ddr_1rank_2rank_dm_1_,     UCF_NET_STRING=("LOC=V29", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQM2 = ddr_1rank_2rank_dm_2_,     UCF_NET_STRING=("LOC=W29", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQM3 = ddr_1rank_2rank_dm_3_,     UCF_NET_STRING=("LOC=T22", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQM4 = ddr_1rank_2rank_dm_4_,     UCF_NET_STRING=("LOC=W28", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQM5 = ddr_1rank_2rank_dm_5_,     UCF_NET_STRING=("LOC=W27", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQM6 = ddr_1rank_2rank_dm_6_,     UCF_NET_STRING=("LOC=W26", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQM7 = ddr_1rank_2rank_dm_7_,     UCF_NET_STRING=("LOC=W25", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQS0 = ddr_1rank_2rank_dqs_0_,    UCF_NET_STRING=("LOC=E30", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQS1 = ddr_1rank_2rank_dqs_1_,    UCF_NET_STRING=("LOC=J29", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQS2 = ddr_1rank_2rank_dqs_2_,    UCF_NET_STRING=("LOC=M30", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQS3 = ddr_1rank_2rank_dqs_3_,    UCF_NET_STRING=("LOC=P29", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQS4 = ddr_1rank_2rank_dqs_4_,    UCF_NET_STRING=("LOC=V23", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQS5 = ddr_1rank_2rank_dqs_5_,    UCF_NET_STRING=("LOC=AA25", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQS6 = ddr_1rank_2rank_dqs_6_,    UCF_NET_STRING=("LOC=AC25", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQS7 = ddr_1rank_2rank_dqs_7_,    UCF_NET_STRING=("LOC=AH26", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ63 = ddr_1rank_2rank_dq_63_,    UCF_NET_STRING=("LOC=AH29", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ62 = ddr_1rank_2rank_dq_62_,    UCF_NET_STRING=("LOC=AH27", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ61 = ddr_1rank_2rank_dq_61_,    UCF_NET_STRING=("LOC=AG28", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ60 = ddr_1rank_2rank_dq_60_,    UCF_NET_STRING=("LOC=AD25", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ59 = ddr_1rank_2rank_dq_59_,    UCF_NET_STRING=("LOC=AD26", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ58 = ddr_1rank_2rank_dq_58_,    UCF_NET_STRING=("LOC=AG29", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ57 = ddr_1rank_2rank_dq_57_,    UCF_NET_STRING=("LOC=AG30", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ56 = ddr_1rank_2rank_dq_56_,    UCF_NET_STRING=("LOC=AF25", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ55 = ddr_1rank_2rank_dq_55_,    UCF_NET_STRING=("LOC=AF29", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ54 = ddr_1rank_2rank_dq_54_,    UCF_NET_STRING=("LOC=AF30", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ53 = ddr_1rank_2rank_dq_53_,    UCF_NET_STRING=("LOC=AD27", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ52 = ddr_1rank_2rank_dq_52_,    UCF_NET_STRING=("LOC=AD28", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ51 = ddr_1rank_2rank_dq_51_,    UCF_NET_STRING=("LOC=AA23", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ50 = ddr_1rank_2rank_dq_50_,    UCF_NET_STRING=("LOC=AA24", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ49 = ddr_1rank_2rank_dq_49_,    UCF_NET_STRING=("LOC=AE29", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ48 = ddr_1rank_2rank_dq_48_,    UCF_NET_STRING=("LOC=AB25", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ47 = ddr_1rank_2rank_dq_47_,    UCF_NET_STRING=("LOC=AC29", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ46 = ddr_1rank_2rank_dq_46_,    UCF_NET_STRING=("LOC=AB27", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ45 = ddr_1rank_2rank_dq_45_,    UCF_NET_STRING=("LOC=AB28", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ44 = ddr_1rank_2rank_dq_44_,    UCF_NET_STRING=("LOC=W23", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ43 = ddr_1rank_2rank_dq_43_,    UCF_NET_STRING=("LOC=W24", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ42 = ddr_1rank_2rank_dq_42_,    UCF_NET_STRING=("LOC=AA27", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ41 = ddr_1rank_2rank_dq_41_,    UCF_NET_STRING=("LOC=AA28", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ40 = ddr_1rank_2rank_dq_40_,    UCF_NET_STRING=("LOC=Y26", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ39 = ddr_1rank_2rank_dq_39_,    UCF_NET_STRING=("LOC=AA29", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ38 = ddr_1rank_2rank_dq_38_,    UCF_NET_STRING=("LOC=Y29", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ37 = ddr_1rank_2rank_dq_37_,    UCF_NET_STRING=("LOC=V25", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ36 = ddr_1rank_2rank_dq_36_,    UCF_NET_STRING=("LOC=V26", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ35 = ddr_1rank_2rank_dq_35_,    UCF_NET_STRING=("LOC=U23", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ34 = ddr_1rank_2rank_dq_34_,    UCF_NET_STRING=("LOC=U24", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ33 = ddr_1rank_2rank_dq_33_,    UCF_NET_STRING=("LOC=Y30", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ32 = ddr_1rank_2rank_dq_32_,    UCF_NET_STRING=("LOC=V27", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ31 = ddr_1rank_2rank_dq_31_,    UCF_NET_STRING=("LOC=N28", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ30 = ddr_1rank_2rank_dq_30_,    UCF_NET_STRING=("LOC=N27", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ29 = ddr_1rank_2rank_dq_29_,    UCF_NET_STRING=("LOC=P24", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ28 = ddr_1rank_2rank_dq_28_,    UCF_NET_STRING=("LOC=P23", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ27 = ddr_1rank_2rank_dq_27_,    UCF_NET_STRING=("LOC=P30", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ26 = ddr_1rank_2rank_dq_26_,    UCF_NET_STRING=("LOC=M28", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ25 = ddr_1rank_2rank_dq_25_,    UCF_NET_STRING=("LOC=M27", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ24 = ddr_1rank_2rank_dq_24_,    UCF_NET_STRING=("LOC=R22", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ23 = ddr_1rank_2rank_dq_23_,    UCF_NET_STRING=("LOC=K28", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ22 = ddr_1rank_2rank_dq_22_,    UCF_NET_STRING=("LOC=K27", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ21 = ddr_1rank_2rank_dq_21_,    UCF_NET_STRING=("LOC=N24", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ20 = ddr_1rank_2rank_dq_20_,    UCF_NET_STRING=("LOC=N23", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ19 = ddr_1rank_2rank_dq_19_,    UCF_NET_STRING=("LOC=L29", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ18 = ddr_1rank_2rank_dq_18_,    UCF_NET_STRING=("LOC=K29", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ17 = ddr_1rank_2rank_dq_17_,    UCF_NET_STRING=("LOC=J28", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ16 = ddr_1rank_2rank_dq_16_,    UCF_NET_STRING=("LOC=J27", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ15 = ddr_1rank_2rank_dq_15_,    UCF_NET_STRING=("LOC=H28", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ14 = ddr_1rank_2rank_dq_14_,    UCF_NET_STRING=("LOC=H27", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ13 = ddr_1rank_2rank_dq_13_,    UCF_NET_STRING=("LOC=L24", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ12 = ddr_1rank_2rank_dq_12_,    UCF_NET_STRING=("LOC=L23", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ11 = ddr_1rank_2rank_dq_11_,    UCF_NET_STRING=("LOC=G30", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ10 = ddr_1rank_2rank_dq_10_,    UCF_NET_STRING=("LOC=G28", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ9  = ddr_1rank_2rank_dq_9_,     UCF_NET_STRING=("LOC=G27", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ8  = ddr_1rank_2rank_dq_8_,     UCF_NET_STRING=("LOC=J26", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ7  = ddr_1rank_2rank_dq_7_,     UCF_NET_STRING=("LOC=E28", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ6  = ddr_1rank_2rank_dq_6_,     UCF_NET_STRING=("LOC=E27", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ5  = ddr_1rank_2rank_dq_5_,     UCF_NET_STRING=("LOC=H26", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ4  = ddr_1rank_2rank_dq_4_,     UCF_NET_STRING=("LOC=H25", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ3  = ddr_1rank_2rank_dq_3_,     UCF_NET_STRING=("LOC=D30", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ2  = ddr_1rank_2rank_dq_2_,     UCF_NET_STRING=("LOC=D29", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ1  = ddr_1rank_2rank_dq_1_,     UCF_NET_STRING=("LOC=D28", "IOSTANDARD = SSTL2_II")
  PORT DDR_DQ0  = ddr_1rank_2rank_dq_0_,     UCF_NET_STRING=("LOC=C27", "IOSTANDARD = SSTL2_II")
  PORT DDR_CLK_FB = ddr_1rank_2rank_clk_fb,  UCF_NET_STRING=("LOC=C16", "IOSTANDARD = SSTL2_II")
  PORT DDR_CLK_FB_OUT = ddr_1rank_2rank_clk_fb_out,  UCF_NET_STRING=("LOC=G23", "IOSTANDARD = SSTL2_II")

  PORT DDR_CKE0  = ddr_2rank_cke_0_,   UCF_NET_STRING=("LOC=R26", "IOSTANDARD = SSTL2_II")
  PORT DDR_CKE1  = ddr_2rank_cke_1_,   UCF_NET_STRING=("LOC=R25", "IOSTANDARD = SSTL2_II")
  PORT DDR_CS_N0 = ddr_2rank_cs_n_0_,  UCF_NET_STRING=("LOC=R24", "IOSTANDARD = SSTL2_II")
  PORT DDR_CS_N1 = ddr_2rank_cs_n_1_,  UCF_NET_STRING=("LOC=R23", "IOSTANDARD = SSTL2_II")

  PORT DDR_CKE  = ddr_1rank_cke_,   UCF_NET_STRING=("LOC=R26", "IOSTANDARD = SSTL2_II")
  PORT DDR_CS_N = ddr_1rank_cs_n,  UCF_NET_STRING=("LOC=R24", "IOSTANDARD = SSTL2_II")

  # Dual PS/2 Ports
  PORT PS2_1_CLK   = ps2_1_clk,  UCF_NET_STRING=("LOC=AG2", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
  PORT PS2_1_DATA  = ps2_1_data, UCF_NET_STRING=("LOC=AG1", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
  PORT PS2_2_CLK   = ps2_2_clk,  UCF_NET_STRING=("LOC=AD6", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
  PORT PS2_2_DATA  = ps2_2_data, UCF_NET_STRING=("LOC=AD5", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
 
  # XSGA VGA Outputs (the least two color bits are grounded)
  PORT CLK  = vga_clk, UCF_NET_STRING=("LOC=H12", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT HYSN = vga_hsync, UCF_NET_STRING=("LOC=B8", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 12")
  PORT VSYN = vga_vsync, UCF_NET_STRING=("LOC=D11", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 12")
  PORT BLANK_N = vga_blnk_n, UCF_NET_STRING=("LOC=A8", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT COMP_SYNCH = net_gnd, UCF_NET_STRING=("LOC=G12", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT B0   = net_gnd, UCF_NET_STRING=("LOC=D15", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT B1   = net_gnd, UCF_NET_STRING=("LOC=E15", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT B2   = vga_b_0, UCF_NET_STRING=("LOC=H15", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT B3   = vga_b_1, UCF_NET_STRING=("LOC=J15", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT B4   = vga_b_2, UCF_NET_STRING=("LOC=C13", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT B5   = vga_b_3, UCF_NET_STRING=("LOC=D13", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT B6   = vga_b_4, UCF_NET_STRING=("LOC=D14", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT B7   = vga_b_5, UCF_NET_STRING=("LOC=E14", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT G0   = net_gnd, UCF_NET_STRING=("LOC=G10", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT G1   = net_gnd, UCF_NET_STRING=("LOC=E10", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT G2   = vga_g_0, UCF_NET_STRING=("LOC=D10", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT G3   = vga_g_1, UCF_NET_STRING=("LOC=D8", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT G4   = vga_g_2, UCF_NET_STRING=("LOC=C8", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT G5   = vga_g_3, UCF_NET_STRING=("LOC=H11", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT G6   = vga_g_4, UCF_NET_STRING=("LOC=G11", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT G7   = vga_g_5, UCF_NET_STRING=("LOC=E11", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT R0   = net_gnd, UCF_NET_STRING=("LOC=G8", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT R1   = net_gnd, UCF_NET_STRING=("LOC=H9", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT R2   = vga_r_0, UCF_NET_STRING=("LOC=G9", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT R3   = vga_r_1, UCF_NET_STRING=("LOC=F9", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT R4   = vga_r_2, UCF_NET_STRING=("LOC=F10", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT R5   = vga_r_3, UCF_NET_STRING=("LOC=D7", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT R6   = vga_r_4, UCF_NET_STRING=("LOC=C7", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")
  PORT R7   = vga_r_5, UCF_NET_STRING=("LOC=H10", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 6")

  # AC97 Audio Codec
  PORT AC97_BIT_CLOCK  = ac97_bit_clk,   UCF_NET_STRING=("LOC=F8", "IOSTANDARD = LVTTL") # CLK output
  PORT AC97_AUDIO_RESET_Z  = ac97_reset_n,   UCF_NET_STRING=("LOC=E6", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
  PORT AC97_SDATA_IN   = ac97_sdata_in,  UCF_NET_STRING=("LOC=E9", "IOSTANDARD = LVTTL")
  PORT AC97_SDATA_OUT  = ac97_sdata_out, UCF_NET_STRING=("LOC=E8", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
  PORT AC97_SYNCH      = ac97_sync,      UCF_NET_STRING=("LOC=F7", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
  PORT AC97_BEEP_TONE_IN    = AC97_BEEP_TONE_IN, UCF_NET_STRING=("LOC=E7", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")



END