xilinx_xup_v2p_v2_2_0.xbd

Xilinx ISE&EDK 8.2平台的人脸检测系统设计

 PORT DQS0 = ddr_1rank_2rank_dqs_0_, IO_IS = data_strobe[7]
 PORT DQS1 = ddr_1rank_2rank_dqs_1_, IO_IS = data_strobe[6]
 PORT DQS2 = ddr_1rank_2rank_dqs_2_, IO_IS = data_strobe[5]
 PORT DQS3 = ddr_1rank_2rank_dqs_3_, IO_IS = data_strobe[4]
 PORT DQS4 = ddr_1rank_2rank_dqs_4_, IO_IS = data_strobe[3]
 PORT DQS5 = ddr_1rank_2rank_dqs_5_, IO_IS = data_strobe[2]
 PORT DQS6 = ddr_1rank_2rank_dqs_6_, IO_IS = data_strobe[1]
 PORT DQS7 = ddr_1rank_2rank_dqs_7_, IO_IS = data_strobe[0]

 PORT DQ0 = ddr_1rank_2rank_dq_0_,  IO_IS =  data[63]
 PORT DQ1 = ddr_1rank_2rank_dq_1_,  IO_IS =  data[62]
 PORT DQ2 = ddr_1rank_2rank_dq_2_,  IO_IS =  data[61]
 PORT DQ3 = ddr_1rank_2rank_dq_3_,  IO_IS =  data[60]
 PORT DQ4 = ddr_1rank_2rank_dq_4_,  IO_IS =  data[59]
 PORT DQ5 = ddr_1rank_2rank_dq_5_,  IO_IS =  data[58]
 PORT DQ6 = ddr_1rank_2rank_dq_6_,  IO_IS =  data[57]
 PORT DQ7 = ddr_1rank_2rank_dq_7_,  IO_IS =  data[56]
 PORT DQ8 = ddr_1rank_2rank_dq_8_,  IO_IS =  data[55]
 PORT DQ9 = ddr_1rank_2rank_dq_9_,  IO_IS =  data[54]
 PORT DQ10 = ddr_1rank_2rank_dq_10_, IO_IS = data[53]
 PORT DQ11 = ddr_1rank_2rank_dq_11_, IO_IS = data[52]
 PORT DQ12 = ddr_1rank_2rank_dq_12_, IO_IS = data[51]
 PORT DQ13 = ddr_1rank_2rank_dq_13_, IO_IS = data[50]
 PORT DQ14 = ddr_1rank_2rank_dq_14_, IO_IS = data[49]
 PORT DQ15 = ddr_1rank_2rank_dq_15_, IO_IS = data[48]
 PORT DQ16 = ddr_1rank_2rank_dq_16_, IO_IS = data[47]
 PORT DQ17 = ddr_1rank_2rank_dq_17_, IO_IS = data[46]
 PORT DQ18 = ddr_1rank_2rank_dq_18_, IO_IS = data[45]
 PORT DQ19 = ddr_1rank_2rank_dq_19_, IO_IS = data[44]
 PORT DQ20 = ddr_1rank_2rank_dq_20_, IO_IS = data[43]
 PORT DQ21 = ddr_1rank_2rank_dq_21_, IO_IS = data[42]
 PORT DQ22 = ddr_1rank_2rank_dq_22_, IO_IS = data[41]
 PORT DQ23 = ddr_1rank_2rank_dq_23_, IO_IS = data[40]
 PORT DQ24 = ddr_1rank_2rank_dq_24_, IO_IS = data[39]
 PORT DQ25 = ddr_1rank_2rank_dq_25_, IO_IS = data[38]
 PORT DQ26 = ddr_1rank_2rank_dq_26_, IO_IS = data[37]
 PORT DQ27 = ddr_1rank_2rank_dq_27_, IO_IS = data[36]
 PORT DQ28 = ddr_1rank_2rank_dq_28_, IO_IS = data[35]
 PORT DQ29 = ddr_1rank_2rank_dq_29_, IO_IS = data[34]
 PORT DQ30 = ddr_1rank_2rank_dq_30_, IO_IS = data[33]
 PORT DQ31 = ddr_1rank_2rank_dq_31_, IO_IS = data[32]
 PORT DQ32 = ddr_1rank_2rank_dq_32_, IO_IS = data[31]
 PORT DQ33 = ddr_1rank_2rank_dq_33_, IO_IS = data[30]
 PORT DQ34 = ddr_1rank_2rank_dq_34_, IO_IS = data[29]
 PORT DQ35 = ddr_1rank_2rank_dq_35_, IO_IS = data[28]
 PORT DQ36 = ddr_1rank_2rank_dq_36_, IO_IS = data[27]
 PORT DQ37 = ddr_1rank_2rank_dq_37_, IO_IS = data[26]
 PORT DQ38 = ddr_1rank_2rank_dq_38_, IO_IS = data[25]
 PORT DQ39 = ddr_1rank_2rank_dq_39_, IO_IS = data[24]
 PORT DQ40 = ddr_1rank_2rank_dq_40_, IO_IS = data[23]
 PORT DQ41 = ddr_1rank_2rank_dq_41_, IO_IS = data[22]
 PORT DQ42 = ddr_1rank_2rank_dq_42_, IO_IS = data[21]
 PORT DQ43 = ddr_1rank_2rank_dq_43_, IO_IS = data[20]
 PORT DQ44 = ddr_1rank_2rank_dq_44_, IO_IS = data[19]
 PORT DQ45 = ddr_1rank_2rank_dq_45_, IO_IS = data[18]
 PORT DQ46 = ddr_1rank_2rank_dq_46_, IO_IS = data[17]
 PORT DQ47 = ddr_1rank_2rank_dq_47_, IO_IS = data[16]
 PORT DQ48 = ddr_1rank_2rank_dq_48_, IO_IS = data[15]
 PORT DQ49 = ddr_1rank_2rank_dq_49_, IO_IS = data[14]
 PORT DQ50 = ddr_1rank_2rank_dq_50_, IO_IS = data[13]
 PORT DQ51 = ddr_1rank_2rank_dq_51_, IO_IS = data[12]
 PORT DQ52 = ddr_1rank_2rank_dq_52_, IO_IS = data[11]
 PORT DQ53 = ddr_1rank_2rank_dq_53_, IO_IS = data[10]
 PORT DQ54 = ddr_1rank_2rank_dq_54_, IO_IS = data[9]
 PORT DQ55 = ddr_1rank_2rank_dq_55_, IO_IS = data[8]
 PORT DQ56 = ddr_1rank_2rank_dq_56_, IO_IS = data[7]
 PORT DQ57 = ddr_1rank_2rank_dq_57_, IO_IS = data[6]
 PORT DQ58 = ddr_1rank_2rank_dq_58_, IO_IS = data[5]
 PORT D5Q9 = ddr_1rank_2rank_dq_59_, IO_IS = data[4]
 PORT DQ60 = ddr_1rank_2rank_dq_60_, IO_IS = data[3]
 PORT DQ61 = ddr_1rank_2rank_dq_61_, IO_IS = data[2]
 PORT DQ62 = ddr_1rank_2rank_dq_62_, IO_IS = data[1]
 PORT DQ63 = ddr_1rank_2rank_dq_63_, IO_IS = data[0]

 PORT DDR_FPGA_CK0   = ddr_1rank_2rank_clk_0_,    IO_IS=DDR_Clk_out[2]
 PORT DDR_FPGA_CK1   = ddr_1rank_2rank_clk_1_,    IO_IS=DDR_Clk_out[1]
 PORT DDR_FPGA_CK2   = ddr_1rank_2rank_clk_2_,    IO_IS=DDR_Clk_out[0]
 PORT DDR_FPGA_CK_N0 = ddr_1rank_2rank_clk_n_0_, IO_IS=DDR_Clk_out_n[2]
 PORT DDR_FPGA_CK_N1 = ddr_1rank_2rank_clk_n_1_, IO_IS=DDR_Clk_out_n[1]
 PORT DDR_FPGA_CK_N2 = ddr_1rank_2rank_clk_n_2_, IO_IS=DDR_Clk_out_n[0] 

 PORT DDR_FB_CLK   = ddr_1rank_2rank_clk_fb, IO_IS=feedback_clock, FEEDBACK_PHASE=60
 PORT DDR_FB_CLK_OUT   = ddr_1rank_2rank_clk_fb_out, IO_IS=feedback_clock_out
END


# Dual PS/2 Ports 
BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_DUAL_PS2_V1
  ATTRIBUTE INSTANCE = PS2_Ports
  ATTRIBUTE CORENAME = dual_ps2_ioadapter
  ATTRIBUTE VERSION = 1.00.a
  PORT CLK_IN    = ps2_1_clk_in,   IO_IS=Clkin1
  PORT CLK_OUT   = ps2_1_clk_out,  IO_IS=Clkpd1
  PORT DATA_IN   = ps2_1_data_in,  IO_IS=Rx1
  PORT DATA_OUT  = ps2_1_data_out, IO_IS=Txpd1
  PORT CLK_IN2   = ps2_2_clk_in,   IO_IS=Clkin2
  PORT CLK_OUT2  = ps2_2_clk_out,  IO_IS=Clkpd2
  PORT DATA_IN2  = ps2_2_data_in,  IO_IS=Rx2
  PORT DATA_OUT2 = ps2_2_data_out, IO_IS=Txpd2
END

BEGIN IO_ADAPTER
  ATTRIBUTE CORENAME = dual_ps2_ioadapter
  ATTRIBUTE INSTANCE = PS2_Ports_IO_ADAPTER
  PORT ps2_clk_rx_1 = ps2_1_clk_in
  PORT ps2_clk_tx_1 = ps2_1_clk_out
  PORT ps2_d_rx_1   = ps2_1_data_in
  PORT ps2_d_tx_1   = ps2_1_data_out
  PORT ps2_clk_rx_2 = ps2_2_clk_in
  PORT ps2_clk_tx_2 = ps2_2_clk_out
  PORT ps2_d_rx_2   = ps2_2_data_in
  PORT ps2_d_tx_2   = ps2_2_data_out
  PORT ps2_mouse_clk   = ps2_1_clk
  PORT ps2_mouse_data  = ps2_1_data
  PORT ps2_keyb_clk   = ps2_2_clk
  PORT ps2_keyb_data  = ps2_2_data
END

BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_TFT_V1
  ATTRIBUTE INSTANCE = VGA_FrameBuffer
  PARAMETER HW_VER = 1.00.d
  # BSB does not support DCR BUS
  #  PARAMETER C_DCR_BASEADDR = 0b0100000000
  #  PARAMETER C_DCR_HIGHADDR = 0b0100000001
  # Default base address
  # maps to 0x07E0 0000 128 MB - 2 Mb
  PARAMETER C_DEFAULT_TFT_BASE_ADDR = 0b00000111111 
  PARAMETER C_PIXCLK_IS_BUSCLK_DIVBY4  = 0b1
  PORT CLK  = vga_clk,    IO_IS = pixel_clk
  PORT HYSN = vga_hsync,  IO_IS = horiz_sync
  PORT VSYN = vga_vsync,  IO_IS = vert_sync
  PORT B0   = vga_b_0,    IO_IS = blue[0]
  PORT B1   = vga_b_1,    IO_IS = blue[1]
  PORT B2   = vga_b_2,    IO_IS = blue[2]
  PORT B3   = vga_b_3,    IO_IS = blue[3]
  PORT B4   = vga_b_4,    IO_IS = blue[4]
  PORT B5   = vga_b_5,    IO_IS = blue[5]
  PORT G0   = vga_g_0,    IO_IS = green[0]
  PORT G1   = vga_g_1,    IO_IS = green[1]
  PORT G2   = vga_g_2,    IO_IS = green[2]
  PORT G3   = vga_g_3,    IO_IS = green[3]
  PORT G4   = vga_g_4,    IO_IS = green[4]
  PORT G5   = vga_g_5,    IO_IS = green[5]
  PORT R0   = vga_r_0,    IO_IS = red[0]
  PORT R1   = vga_r_1,    IO_IS = red[1]
  PORT R2   = vga_r_2,    IO_IS = red[2]
  PORT R3   = vga_r_3,    IO_IS = red[3]
  PORT R4   = vga_r_4,    IO_IS = red[4]
  PORT R5   = vga_r_5,    IO_IS = red[5]
  PORT BLNK = vga_blnk_n, IO_IS = blnk_n
END

# National Semiconductor LM4550 AC97 audio CODEC
BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_AC97_V2
  ATTRIBUTE INSTANCE = Audio_Codec
  PORT BIT_CLK     = ac97_bit_clk,   IO_IS=AC97_BIT_CLOCK
  PORT SDATA_IN    = ac97_sdata_in,  IO_IS=AC97_SDATA_IN
  PORT SDATA_OUT   = ac97_sdata_out, IO_IS=AC97_SDATA_OUT
  PORT SYNC        = ac97_sync,      IO_IS=AC97_SYNCH
  PORT BEEP_TONE_IN= ac97_beep_tone, IO_IS=AC97_BEEP_TONE_IN, INITIALVAL = GND
  PORT RESET_N     = ac97_reset_n,   IO_IS=AC97_AUDIO_RESET_Z, INITIALVAL = VCC
END

BEGIN FPGA
  ATTRIBUTE INSTANCE = fpga_0
  ATTRIBUTE FAMILY = virtex2p
  ATTRIBUTE DEVICE = xc2vp30
  ATTRIBUTE PACKAGE = ff896
  ATTRIBUTE SPEED_GRADE = -7
  ATTRIBUTE JTAG_POSITION = 3

  PORT CLK_100MHZ_OSC  = CLK_100MHZ_OSC,  UCF_NET_STRING=("LOC=AJ15", "IOSTANDARD = LVCMOS25") # Input CLK
  PORT EXT_RST_N = sys_rst_n, UCF_NET_STRING=("LOC=AH5", "IOSTANDARD = LVTTL")

  # OneWire Serial Number and Ethernet Address interface
  PORT SSN_DATA = SSN_DATA, UCF_NET_STRING=("LOC=J3", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8") 

  # CPU JTAG DEBUG
  PORT CPU_HALT_N = cpu_halt, UCF_NET_STRING=("LOC=AJ23", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 12")
  PORT CPU_TDO = cpu_tdo, UCF_NET_STRING=("LOC=AG16", "IOSTANDARD = LVCMOS25")
  PORT CPU_TDI = cpu_tdi, UCF_NET_STRING=("LOC=AF15", "IOSTANDARD = LVCMOS25")
  PORT CPU_TCK = cpu_tck, UCF_NET_STRING=("LOC=AG15", "IOSTANDARD = LVCMOS25") # CLK output
  PORT CPU_TMS = cpu_tms, UCF_NET_STRING=("LOC=AJ16", "IOSTANDARD = LVCMOS25")
  PORT CPU_TRST = cpu_trst, UCF_NET_STRING=("LOC=AC21", "IOSTANDARD = LVCMOS25")

  # RS232
  # Note: Pin RS232_DSR_OUT (LOC=AD10) Not used
  PORT CTS = uart1_ctsn, UCF_NET_STRING=("LOC=AE8", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 8")
  PORT RTS = uart1_rtsn, UCF_NET_STRING=("LOC=AK8", "IOSTANDARD = LVCMOS25")
  PORT RXD = uart1_sin, UCF_NET_STRING=("LOC=AJ8", "IOSTANDARD = LVCMOS25")
  PORT TXD = uart1_sout, UCF_NET_STRING=("LOC=AE7", "IOSTANDARD = LVCMOS25", "SLEW = SLOW", "DRIVE = 12")
  
  # 10/100 Ethernet MAC
  PORT PHY_SLW0   = phy_slew0,     UCF_NET_STRING=("LOC=B3", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
  PORT PHY_SLW1   = phy_slew1,     UCF_NET_STRING=("LOC=A3", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
  PORT PHY_RESET  = phy_rst_n,     UCF_NET_STRING=("LOC=G6", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
  PORT PHY_MDINT  = phy_mii_int_n, UCF_NET_STRING=("LOC=G5", "IOSTANDARD = LVTTL")
  PORT PHY_CRS    = phy_crs,       UCF_NET_STRING=("LOC=C5", "IOSTANDARD = LVTTL")
  PORT PHY_COL    = phy_col,       UCF_NET_STRING=("LOC=D5", "IOSTANDARD = LVTTL")
  PORT PHY_TXD3   = phy_tx_data_3, UCF_NET_STRING=("LOC=C2", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
  PORT PHY_TXD2   = phy_tx_data_2, UCF_NET_STRING=("LOC=C1", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
  PORT PHY_TXD1   = phy_tx_data_1, UCF_NET_STRING=("LOC=J8", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
  PORT PHY_TXD0   = phy_tx_data_0, UCF_NET_STRING=("LOC=J7", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
  PORT PHY_TX_EN  = phy_tx_en,     UCF_NET_STRING=("LOC=C4", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
  PORT PHY_TX_CLK = phy_tx_clk,    UCF_NET_STRING=("LOC=D3", "IOSTANDARD = LVTTL")
  PORT PHY_TX_ER  = phy_tx_er,     UCF_NET_STRING=("LOC=H2", "IOSTANDARD = LVTTL")
  PORT PHY_RX_ER  = phy_rx_er,     UCF_NET_STRING=("LOC=J2", "IOSTANDARD = LVTTL")
  PORT PHY_RX_CLK = phy_rx_clk,    UCF_NET_STRING=("LOC=M8", "IOSTANDARD = LVTTL")
  PORT PHY_RX_DV  = phy_dv,        UCF_NET_STRING=("LOC=M7", "IOSTANDARD = LVTTL")
  PORT PHY_RXD0   = phy_rx_data_0, UCF_NET_STRING=("LOC=K6", "IOSTANDARD = LVTTL")
  PORT PHY_RXD1   = phy_rx_data_1, UCF_NET_STRING=("LOC=K5", "IOSTANDARD = LVTTL")
  PORT PHY_RXD2   = phy_rx_data_2, UCF_NET_STRING=("LOC=J1", "IOSTANDARD = LVTTL")
  PORT PHY_RXD3   = phy_rx_data_3, UCF_NET_STRING=("LOC=K1", "IOSTANDARD = LVTTL")
  PORT PHY_MDC    = phy_mii_clk,   UCF_NET_STRING=("LOC=M6", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
  PORT PHY_MDIO   = phy_mii_data,  UCF_NET_STRING=("LOC=M5", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")

  # System ACE
  # Note: Pin RCF_MPBRDY (LOC=AE16) Not used