xilinx_xup_v2p_v2_2_0.xbd

Xilinx ISE&EDK 8.2平台的人脸检测系统设计

 PORT CS1  = ddr_2rank_cs_n_1_, IO_IS=chip_select[0]

 PORT RAS = ddr_1rank_2rank_ras_n,    IO_IS=row_addr_select
 PORT WE  = ddr_1rank_2rank_we_n,     IO_IS=write_enable
 PORT DM0 = ddr_1rank_2rank_dm_0_,  IO_IS = data_mask[7]
 PORT DM1 = ddr_1rank_2rank_dm_1_,  IO_IS = data_mask[6]
 PORT DM2 = ddr_1rank_2rank_dm_2_,  IO_IS = data_mask[5]
 PORT DM3 = ddr_1rank_2rank_dm_3_,  IO_IS = data_mask[4]
 PORT DM4 = ddr_1rank_2rank_dm_4_,  IO_IS = data_mask[3]
 PORT DM5 = ddr_1rank_2rank_dm_5_,  IO_IS = data_mask[2]
 PORT DM6 = ddr_1rank_2rank_dm_6_,  IO_IS = data_mask[1]
 PORT DM7 = ddr_1rank_2rank_dm_7_,  IO_IS = data_mask[0]

 PORT DQS0 = ddr_1rank_2rank_dqs_0_, IO_IS = data_strobe[7]
 PORT DQS1 = ddr_1rank_2rank_dqs_1_, IO_IS = data_strobe[6]
 PORT DQS2 = ddr_1rank_2rank_dqs_2_, IO_IS = data_strobe[5]
 PORT DQS3 = ddr_1rank_2rank_dqs_3_, IO_IS = data_strobe[4]
 PORT DQS4 = ddr_1rank_2rank_dqs_4_, IO_IS = data_strobe[3]
 PORT DQS5 = ddr_1rank_2rank_dqs_5_, IO_IS = data_strobe[2]
 PORT DQS6 = ddr_1rank_2rank_dqs_6_, IO_IS = data_strobe[1]
 PORT DQS7 = ddr_1rank_2rank_dqs_7_, IO_IS = data_strobe[0]

 PORT DQ0 = ddr_1rank_2rank_dq_0_,  IO_IS =  data[63]
 PORT DQ1 = ddr_1rank_2rank_dq_1_,  IO_IS =  data[62]
 PORT DQ2 = ddr_1rank_2rank_dq_2_,  IO_IS =  data[61]
 PORT DQ3 = ddr_1rank_2rank_dq_3_,  IO_IS =  data[60]
 PORT DQ4 = ddr_1rank_2rank_dq_4_,  IO_IS =  data[59]
 PORT DQ5 = ddr_1rank_2rank_dq_5_,  IO_IS =  data[58]
 PORT DQ6 = ddr_1rank_2rank_dq_6_,  IO_IS =  data[57]
 PORT DQ7 = ddr_1rank_2rank_dq_7_,  IO_IS =  data[56]
 PORT DQ8 = ddr_1rank_2rank_dq_8_,  IO_IS =  data[55]
 PORT DQ9 = ddr_1rank_2rank_dq_9_,  IO_IS =  data[54]
 PORT DQ10 = ddr_1rank_2rank_dq_10_, IO_IS = data[53]
 PORT DQ11 = ddr_1rank_2rank_dq_11_, IO_IS = data[52]
 PORT DQ12 = ddr_1rank_2rank_dq_12_, IO_IS = data[51]
 PORT DQ13 = ddr_1rank_2rank_dq_13_, IO_IS = data[50]
 PORT DQ14 = ddr_1rank_2rank_dq_14_, IO_IS = data[49]
 PORT DQ15 = ddr_1rank_2rank_dq_15_, IO_IS = data[48]
 PORT DQ16 = ddr_1rank_2rank_dq_16_, IO_IS = data[47]
 PORT DQ17 = ddr_1rank_2rank_dq_17_, IO_IS = data[46]
 PORT DQ18 = ddr_1rank_2rank_dq_18_, IO_IS = data[45]
 PORT DQ19 = ddr_1rank_2rank_dq_19_, IO_IS = data[44]
 PORT DQ20 = ddr_1rank_2rank_dq_20_, IO_IS = data[43]
 PORT DQ21 = ddr_1rank_2rank_dq_21_, IO_IS = data[42]
 PORT DQ22 = ddr_1rank_2rank_dq_22_, IO_IS = data[41]
 PORT DQ23 = ddr_1rank_2rank_dq_23_, IO_IS = data[40]
 PORT DQ24 = ddr_1rank_2rank_dq_24_, IO_IS = data[39]
 PORT DQ25 = ddr_1rank_2rank_dq_25_, IO_IS = data[38]
 PORT DQ26 = ddr_1rank_2rank_dq_26_, IO_IS = data[37]
 PORT DQ27 = ddr_1rank_2rank_dq_27_, IO_IS = data[36]
 PORT DQ28 = ddr_1rank_2rank_dq_28_, IO_IS = data[35]
 PORT DQ29 = ddr_1rank_2rank_dq_29_, IO_IS = data[34]
 PORT DQ30 = ddr_1rank_2rank_dq_30_, IO_IS = data[33]
 PORT DQ31 = ddr_1rank_2rank_dq_31_, IO_IS = data[32]
 PORT DQ32 = ddr_1rank_2rank_dq_32_, IO_IS = data[31]
 PORT DQ33 = ddr_1rank_2rank_dq_33_, IO_IS = data[30]
 PORT DQ34 = ddr_1rank_2rank_dq_34_, IO_IS = data[29]
 PORT DQ35 = ddr_1rank_2rank_dq_35_, IO_IS = data[28]
 PORT DQ36 = ddr_1rank_2rank_dq_36_, IO_IS = data[27]
 PORT DQ37 = ddr_1rank_2rank_dq_37_, IO_IS = data[26]
 PORT DQ38 = ddr_1rank_2rank_dq_38_, IO_IS = data[25]
 PORT DQ39 = ddr_1rank_2rank_dq_39_, IO_IS = data[24]
 PORT DQ40 = ddr_1rank_2rank_dq_40_, IO_IS = data[23]
 PORT DQ41 = ddr_1rank_2rank_dq_41_, IO_IS = data[22]
 PORT DQ42 = ddr_1rank_2rank_dq_42_, IO_IS = data[21]
 PORT DQ43 = ddr_1rank_2rank_dq_43_, IO_IS = data[20]
 PORT DQ44 = ddr_1rank_2rank_dq_44_, IO_IS = data[19]
 PORT DQ45 = ddr_1rank_2rank_dq_45_, IO_IS = data[18]
 PORT DQ46 = ddr_1rank_2rank_dq_46_, IO_IS = data[17]
 PORT DQ47 = ddr_1rank_2rank_dq_47_, IO_IS = data[16]
 PORT DQ48 = ddr_1rank_2rank_dq_48_, IO_IS = data[15]
 PORT DQ49 = ddr_1rank_2rank_dq_49_, IO_IS = data[14]
 PORT DQ50 = ddr_1rank_2rank_dq_50_, IO_IS = data[13]
 PORT DQ51 = ddr_1rank_2rank_dq_51_, IO_IS = data[12]
 PORT DQ52 = ddr_1rank_2rank_dq_52_, IO_IS = data[11]
 PORT DQ53 = ddr_1rank_2rank_dq_53_, IO_IS = data[10]
 PORT DQ54 = ddr_1rank_2rank_dq_54_, IO_IS = data[9]
 PORT DQ55 = ddr_1rank_2rank_dq_55_, IO_IS = data[8]
 PORT DQ56 = ddr_1rank_2rank_dq_56_, IO_IS = data[7]
 PORT DQ57 = ddr_1rank_2rank_dq_57_, IO_IS = data[6]
 PORT DQ58 = ddr_1rank_2rank_dq_58_, IO_IS = data[5]
 PORT D5Q9 = ddr_1rank_2rank_dq_59_, IO_IS = data[4]
 PORT DQ60 = ddr_1rank_2rank_dq_60_, IO_IS = data[3]
 PORT DQ61 = ddr_1rank_2rank_dq_61_, IO_IS = data[2]
 PORT DQ62 = ddr_1rank_2rank_dq_62_, IO_IS = data[1]
 PORT DQ63 = ddr_1rank_2rank_dq_63_, IO_IS = data[0]

 PORT DDR_FPGA_CK0   = ddr_1rank_2rank_clk_0_,    IO_IS=DDR_Clk_out[2]
 PORT DDR_FPGA_CK1   = ddr_1rank_2rank_clk_1_,    IO_IS=DDR_Clk_out[1]
 PORT DDR_FPGA_CK2   = ddr_1rank_2rank_clk_2_,    IO_IS=DDR_Clk_out[0]
 PORT DDR_FPGA_CK_N0 = ddr_1rank_2rank_clk_n_0_, IO_IS=DDR_Clk_out_n[2]
 PORT DDR_FPGA_CK_N1 = ddr_1rank_2rank_clk_n_1_, IO_IS=DDR_Clk_out_n[1]
 PORT DDR_FPGA_CK_N2 = ddr_1rank_2rank_clk_n_2_, IO_IS=DDR_Clk_out_n[0] 

 PORT DDR_FB_CLK   = ddr_1rank_2rank_clk_fb, IO_IS=feedback_clock, FEEDBACK_PHASE=60
 PORT DDR_FB_CLK_OUT   = ddr_1rank_2rank_clk_fb_out, IO_IS=feedback_clock_out
END

# Total 512 MB arranged as 64Mx64
# Uses  Micron Tech MT4VDDT1664AG-265CC  512MB unbufferd DIMM CL = 2.5 
BEGIN IO_INTERFACE
 ATTRIBUTE IOTYPE = XIL_DDR_V1
 ATTRIBUTE INSTANCE = DDR_512MB_64MX64_rank1_row13_col11_cl2_5
 ATTRIBUTE EXCLUSIVE = ddr_1rank_2rank
 ATTRIBUTE ALERT = 'Micron Tech MT4VDDT1664AG-265CC    512MB unbufferd DIMM module minimum clock frequency of 66Mhz to operate properly.'
 PARAMETER C_NUM_BANKS_MEM = 1, IO_IS=C_NUM_BANKS_MEM
 PARAMETER C_MEM0_BASEADDR = 0x00000000, IO_IS=C_BASEADDR, SHORT_DESC=DDR_SDRAM_64Mx64 Single Rank
 PARAMETER C_MEM0_HIGHADDR = 0x1fffffff, IO_IS=C_HIGHADDR 
 PARAMETER C_NUM_CLK_PAIRS = 3, IO_IS=C_NUM_CLK_PAIRS
 PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 1, IO_IS=C_INCLUDE_BURST_CACHELN_SUPPORT
 PARAMETER C_REG_DIMM = 0, IO_IS=C_REG_DIMM
 PARAMETER C_DDR_TMRD = 20000, IO_IS=C_DDR_TMRD
 PARAMETER C_DDR_TWR = 20000, IO_IS=C_DDR_TWR
 PARAMETER C_DDR_TRAS = 60000, IO_IS=C_DDR_TRAS
 PARAMETER C_DDR_TRC = 90000, IO_IS=C_DDR_TRC
 PARAMETER C_DDR_TRFC = 100000, IO_IS=C_DDR_TRFC
 PARAMETER C_DDR_TRCD = 30000, IO_IS=C_DDR_TRCD
 PARAMETER C_DDR_TRRD = 20000, IO_IS=C_DDR_TRRD
 PARAMETER C_DDR_TRP = 30000, IO_IS=C_DDR_TRP
 PARAMETER C_DDR_TREFC = 70300000, IO_IS=C_DDR_TREFC
 PARAMETER C_DDR_AWIDTH = 13, IO_IS=C_DDR_AWIDTH
 PARAMETER C_DDR_COL_AWIDTH = 11, IO_IS=C_DDR_COL_AWIDTH
 PARAMETER C_DDR_BANK_AWIDTH = 2, IO_IS=C_DDR_BANK_AWIDTH
 PARAMETER C_DDR_DWIDTH = 64, IO_IS=C_DDR_DWIDTH
# Support for 64bit opb_ddr controller starts in EDK 7.1.2
 PORT A0  = ddr_1rank_2rank_addr_0_,  IO_IS=address[12]
 PORT A1  = ddr_1rank_2rank_addr_1_,  IO_IS=address[11]
 PORT A2  = ddr_1rank_2rank_addr_2_,  IO_IS=address[10]
 PORT A3  = ddr_1rank_2rank_addr_3_,  IO_IS=address[9]
 PORT A4  = ddr_1rank_2rank_addr_4_,  IO_IS=address[8]
 PORT A5  = ddr_1rank_2rank_addr_5_,  IO_IS=address[7]
 PORT A6  = ddr_1rank_2rank_addr_6_,  IO_IS=address[6]
 PORT A7  = ddr_1rank_2rank_addr_7_,  IO_IS=address[5]
 PORT A8  = ddr_1rank_2rank_addr_8_,  IO_IS=address[4]
 PORT A9  = ddr_1rank_2rank_addr_9_,  IO_IS=address[3]
 PORT A10 = ddr_1rank_2rank_addr_10_, IO_IS=address[2]
 PORT A11 = ddr_1rank_2rank_addr_11_, IO_IS=address[1]
 PORT A12 = ddr_1rank_2rank_addr_12_, IO_IS=address[0]
 PORT BA0 = ddr_1rank_2rank_ba_0_,    IO_IS=bank_addr[1]
 PORT BA1 = ddr_1rank_2rank_ba_1_,    IO_IS=bank_addr[0]
 PORT CAS = ddr_1rank_2rank_cas_n,    IO_IS=col_addr_select

 PORT CKE = ddr_1rank_cke_,  IO_IS=clk_enable
 PORT CSn  = ddr_1rank_cs_n, IO_IS=chip_select

 PORT RAS = ddr_1rank_2rank_ras_n,    IO_IS=row_addr_select
 PORT WE  = ddr_1rank_2rank_we_n,     IO_IS=write_enable
 PORT DM0 = ddr_1rank_2rank_dm_0_,  IO_IS = data_mask[7]
 PORT DM1 = ddr_1rank_2rank_dm_1_,  IO_IS = data_mask[6]
 PORT DM2 = ddr_1rank_2rank_dm_2_,  IO_IS = data_mask[5]
 PORT DM3 = ddr_1rank_2rank_dm_3_,  IO_IS = data_mask[4]
 PORT DM4 = ddr_1rank_2rank_dm_4_,  IO_IS = data_mask[3]
 PORT DM5 = ddr_1rank_2rank_dm_5_,  IO_IS = data_mask[2]
 PORT DM6 = ddr_1rank_2rank_dm_6_,  IO_IS = data_mask[1]
 PORT DM7 = ddr_1rank_2rank_dm_7_,  IO_IS = data_mask[0]

 PORT DQS0 = ddr_1rank_2rank_dqs_0_, IO_IS = data_strobe[7]
 PORT DQS1 = ddr_1rank_2rank_dqs_1_, IO_IS = data_strobe[6]
 PORT DQS2 = ddr_1rank_2rank_dqs_2_, IO_IS = data_strobe[5]
 PORT DQS3 = ddr_1rank_2rank_dqs_3_, IO_IS = data_strobe[4]
 PORT DQS4 = ddr_1rank_2rank_dqs_4_, IO_IS = data_strobe[3]
 PORT DQS5 = ddr_1rank_2rank_dqs_5_, IO_IS = data_strobe[2]
 PORT DQS6 = ddr_1rank_2rank_dqs_6_, IO_IS = data_strobe[1]
 PORT DQS7 = ddr_1rank_2rank_dqs_7_, IO_IS = data_strobe[0]

 PORT DQ0 = ddr_1rank_2rank_dq_0_,  IO_IS =  data[63]
 PORT DQ1 = ddr_1rank_2rank_dq_1_,  IO_IS =  data[62]
 PORT DQ2 = ddr_1rank_2rank_dq_2_,  IO_IS =  data[61]
 PORT DQ3 = ddr_1rank_2rank_dq_3_,  IO_IS =  data[60]
 PORT DQ4 = ddr_1rank_2rank_dq_4_,  IO_IS =  data[59]
 PORT DQ5 = ddr_1rank_2rank_dq_5_,  IO_IS =  data[58]
 PORT DQ6 = ddr_1rank_2rank_dq_6_,  IO_IS =  data[57]
 PORT DQ7 = ddr_1rank_2rank_dq_7_,  IO_IS =  data[56]
 PORT DQ8 = ddr_1rank_2rank_dq_8_,  IO_IS =  data[55]
 PORT DQ9 = ddr_1rank_2rank_dq_9_,  IO_IS =  data[54]
 PORT DQ10 = ddr_1rank_2rank_dq_10_, IO_IS = data[53]
 PORT DQ11 = ddr_1rank_2rank_dq_11_, IO_IS = data[52]
 PORT DQ12 = ddr_1rank_2rank_dq_12_, IO_IS = data[51]
 PORT DQ13 = ddr_1rank_2rank_dq_13_, IO_IS = data[50]
 PORT DQ14 = ddr_1rank_2rank_dq_14_, IO_IS = data[49]
 PORT DQ15 = ddr_1rank_2rank_dq_15_, IO_IS = data[48]
 PORT DQ16 = ddr_1rank_2rank_dq_16_, IO_IS = data[47]
 PORT DQ17 = ddr_1rank_2rank_dq_17_, IO_IS = data[46]
 PORT DQ18 = ddr_1rank_2rank_dq_18_, IO_IS = data[45]
 PORT DQ19 = ddr_1rank_2rank_dq_19_, IO_IS = data[44]
 PORT DQ20 = ddr_1rank_2rank_dq_20_, IO_IS = data[43]
 PORT DQ21 = ddr_1rank_2rank_dq_21_, IO_IS = data[42]
 PORT DQ22 = ddr_1rank_2rank_dq_22_, IO_IS = data[41]
 PORT DQ23 = ddr_1rank_2rank_dq_23_, IO_IS = data[40]
 PORT DQ24 = ddr_1rank_2rank_dq_24_, IO_IS = data[39]
 PORT DQ25 = ddr_1rank_2rank_dq_25_, IO_IS = data[38]
 PORT DQ26 = ddr_1rank_2rank_dq_26_, IO_IS = data[37]
 PORT DQ27 = ddr_1rank_2rank_dq_27_, IO_IS = data[36]
 PORT DQ28 = ddr_1rank_2rank_dq_28_, IO_IS = data[35]
 PORT DQ29 = ddr_1rank_2rank_dq_29_, IO_IS = data[34]
 PORT DQ30 = ddr_1rank_2rank_dq_30_, IO_IS = data[33]
 PORT DQ31 = ddr_1rank_2rank_dq_31_, IO_IS = data[32]
 PORT DQ32 = ddr_1rank_2rank_dq_32_, IO_IS = data[31]
 PORT DQ33 = ddr_1rank_2rank_dq_33_, IO_IS = data[30]
 PORT DQ34 = ddr_1rank_2rank_dq_34_, IO_IS = data[29]
 PORT DQ35 = ddr_1rank_2rank_dq_35_, IO_IS = data[28]
 PORT DQ36 = ddr_1rank_2rank_dq_36_, IO_IS = data[27]
 PORT DQ37 = ddr_1rank_2rank_dq_37_, IO_IS = data[26]
 PORT DQ38 = ddr_1rank_2rank_dq_38_, IO_IS = data[25]
 PORT DQ39 = ddr_1rank_2rank_dq_39_, IO_IS = data[24]
 PORT DQ40 = ddr_1rank_2rank_dq_40_, IO_IS = data[23]
 PORT DQ41 = ddr_1rank_2rank_dq_41_, IO_IS = data[22]
 PORT DQ42 = ddr_1rank_2rank_dq_42_, IO_IS = data[21]
 PORT DQ43 = ddr_1rank_2rank_dq_43_, IO_IS = data[20]
 PORT DQ44 = ddr_1rank_2rank_dq_44_, IO_IS = data[19]
 PORT DQ45 = ddr_1rank_2rank_dq_45_, IO_IS = data[18]
 PORT DQ46 = ddr_1rank_2rank_dq_46_, IO_IS = data[17]
 PORT DQ47 = ddr_1rank_2rank_dq_47_, IO_IS = data[16]
 PORT DQ48 = ddr_1rank_2rank_dq_48_, IO_IS = data[15]
 PORT DQ49 = ddr_1rank_2rank_dq_49_, IO_IS = data[14]
 PORT DQ50 = ddr_1rank_2rank_dq_50_, IO_IS = data[13]
 PORT DQ51 = ddr_1rank_2rank_dq_51_, IO_IS = data[12]
 PORT DQ52 = ddr_1rank_2rank_dq_52_, IO_IS = data[11]
 PORT DQ53 = ddr_1rank_2rank_dq_53_, IO_IS = data[10]
 PORT DQ54 = ddr_1rank_2rank_dq_54_, IO_IS = data[9]
 PORT DQ55 = ddr_1rank_2rank_dq_55_, IO_IS = data[8]