xilinx_xup_v2p_v2_2_0.xbd

Xilinx ISE&EDK 8.2平台的人脸检测系统设计

# -------------------------------------------------------------
#   Copyright(C) 2003 by Xilinx, Inc. All rights reserved.   --
#                                                            --
#   This copyright notice must be retained as part           --
#   of this text at all times.                               --
# -------------------------------------------------------------

ATTRIBUTE VENDOR = Xilinx
ATTRIBUTE SPEC_URL = www.xilinx.com
ATTRIBUTE CONTACT_INFO_URL=http://www.xilinx.com/univ/
ATTRIBUTE NAME = XUP Virtex-II Pro Development System
ATTRIBUTE REVISION = C

# Board Short Description
ATTRIBUTE DESC = XUP Virtex-II Pro Development System

# Board Long Description
ATTRIBUTE LONG_DESC = 'The XUP Virtex-II Pro Development System provides an advanced hardware platform that consists of a high performance Virtex-II Pro Platform FPGA surrounded by a comprehensive collection of peripherals that can be used to create a complex system and to demonstrate the capability of the Virtex-II Pro Platform FPGA.'

BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_CLOCK_V1
  ATTRIBUTE INSTANCE =clk_100
  PARAMETER CLK_FREQ =100000000, IO_IS=clk_freq, RANGE=(100000000) # 100 Mhz
  PORT CLK_100MHZ_OSC = CLK_100MHZ_OSC, IO_IS=ext_clk
END

BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_RESET_V1
  ATTRIBUTE INSTANCE = rst_0
  PARAMETER RST_POLARITY = 0, IO_IS=polarity, VALUE_NOTE=Active LOW
  PORT RESET = sys_rst_n, IO_IS=ext_rst
END

# OneWire Serial Number and Ethernet Address interface 
BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_ONEWIRE_V1
  ATTRIBUTE INSTANCE = onewire_0
  PORT SSN_DATA = SSN_DATA, IO_IS=onewire_dq
END

# CPU DEBUG Port
BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_CPUDEBUG_V1
  ATTRIBUTE INSTANCE = cpudbg_0
  PORT HALT_N = cpu_halt, IO_IS=cpu_halt
  PORT TDO    = cpu_tdo,  IO_IS=cpu_tdo
  PORT TDI    = cpu_tdi,  IO_IS=cpu_tdi
  PORT TCK    = cpu_tck,  IO_IS=cpu_tck
  PORT TMS    = cpu_tms,  IO_IS=cpu_tms
  PORT TRST   = cpu_trst, IO_IS=cpu_trst
END

# RS232
BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_UART_V1
  ATTRIBUTE INSTANCE = RS232_Uart_1
  PORT CTS = uart1_ctsn, IO_IS=clear_to_send
  PORT RTS = uart1_rtsn, IO_IS=req_to_send
  PORT RX  = uart1_sin,  IO_IS=serial_in
  PORT TX  = uart1_sout, IO_IS=serial_out
END

# LTX972A Ethernet MAC (10/100)
BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_ETHERNET_V1
  ATTRIBUTE INSTANCE = Ethernet_MAC
  PORT TXSLEW0  = phy_slew0, IO_IS=slew1,      INITIALVAL = VCC
  PORT TXSLEW1  = phy_slew1, IO_IS=slew2,      INITIALVAL = VCC
  PORT RESET    = phy_rst_n, IO_IS=PHY_RESETn, INITIALVAL = VCC
  PORT MDINT    = phy_mii_int_n, IO_IS = mii_int_n
  PORT CRS      = phy_crs,       IO_IS = ETH_CRS
  PORT COL      = phy_col,       IO_IS = ETH_COL
  PORT TXD3     = phy_tx_data_3, IO_IS = ETH_TXD[3]
  PORT TXD2     = phy_tx_data_2, IO_IS = ETH_TXD[2]
  PORT TXD1     = phy_tx_data_1, IO_IS = ETH_TXD[1]
  PORT TXD0     = phy_tx_data_0, IO_IS = ETH_TXD[0]
  PORT TX_EN    = phy_tx_en,     IO_IS = ETH_TXEN
  PORT TX_CLK   = phy_tx_clk,    IO_IS = ETH_TXC
  PORT TX_ER    = phy_tx_er,     IO_IS = ETH_TXER
  PORT RX_ER    = phy_rx_er,     IO_IS = ETH_RXER
  PORT RX_CLK   = phy_rx_clk,    IO_IS = ETH_RXC
  PORT RX_DV    = phy_dv,        IO_IS = ETH_RXDV
  PORT RXD0     = phy_rx_data_0, IO_IS = ETH_RXD[0]
  PORT RXD1     = phy_rx_data_1, IO_IS = ETH_RXD[1]
  PORT RXD2     = phy_rx_data_2, IO_IS = ETH_RXD[2]
  PORT RXD3     = phy_rx_data_3, IO_IS = ETH_RXD[3]
  PORT PHY_MDC  = phy_mii_clk,   IO_IS = ETH_MDC
  PORT PHY_MDIO = phy_mii_data,  IO_IS = ETH_MDIO
END

# System Advanced Configuration Environment 
BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_SYSACE_V1
  ATTRIBUTE INSTANCE = SysACE_CompactFlash
  PARAMETER C_MEM_WIDTH = 16, IO_IS=mem_data_bus_width  
  PORT sysace_clk = sysace_clk, IO_IS=clk_in
  PORT MPA00   = sysace_mpa_0_,  IO_IS = address[0]
  PORT MPA01   = sysace_mpa_1_,  IO_IS = address[1]
  PORT MPA02   = sysace_mpa_2_,  IO_IS = address[2]
  PORT MPA03   = sysace_mpa_3_,  IO_IS = address[3]
  PORT MPA04   = sysace_mpa_4_,  IO_IS = address[4]
  PORT MPA05   = sysace_mpa_5_,  IO_IS = address[5]
  PORT MPA06   = sysace_mpa_6_,  IO_IS = address[6]
  PORT MPD00   = sysace_mpd_0_,  IO_IS = data[0]
  PORT MPD01   = sysace_mpd_1_,  IO_IS = data[1]
  PORT MPD02   = sysace_mpd_2_,  IO_IS = data[2]
  PORT MPD03   = sysace_mpd_3_,  IO_IS = data[3]
  PORT MPD04   = sysace_mpd_4_,  IO_IS = data[4]
  PORT MPD05   = sysace_mpd_5_,  IO_IS = data[5]
  PORT MPD06   = sysace_mpd_6_,  IO_IS = data[6]
  PORT MPD07   = sysace_mpd_7_,  IO_IS = data[7]
  PORT MPD08   = sysace_mpd_8_,  IO_IS = data[8]
  PORT MPD09   = sysace_mpd_9_,  IO_IS = data[9]
  PORT MPD10   = sysace_mpd_10_, IO_IS = data[10]
  PORT MPD11   = sysace_mpd_11_, IO_IS = data[11]
  PORT MPD12   = sysace_mpd_12_, IO_IS = data[12]
  PORT MPD13   = sysace_mpd_13_, IO_IS = data[13]
  PORT MPD14   = sysace_mpd_14_, IO_IS = data[14]
  PORT MPD15   = sysace_mpd_15_, IO_IS = data[15]
  PORT MPCE    = sysace_mpce,    IO_IS=chip_enable
  PORT MPOE    = sysace_mpoe,    IO_IS=output_enable
  PORT MPWE    = sysace_mpwe,    IO_IS=write_enable
  PORT MPIRQ   = sysace_mpirq,   IO_IS=intr_out
END

# 4 LEDS and 4 Dip Switchs
BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_GPIO_V1
  ATTRIBUTE INSTANCE = LEDs_4Bit
  PARAMETER num_bits = 4, IO_IS=num_bits
  PARAMETER is_dual = 0, IO_IS=is_dual 
  PARAMETER bidir_data = 0, IO_IS=is_bidir        # Non-Bidir data pins
  PARAMETER all_inputs = 0, IO_IS=all_inputs

  PORT LED_0 = LED_0, IO_IS = gpio_io[0]
  PORT LED_1 = LED_1, IO_IS = gpio_io[1]
  PORT LED_2 = LED_2, IO_IS = gpio_io[2]
  PORT LED_3 = LED_3, IO_IS = gpio_io[3]
END

# 4 Dip Switchs
BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_GPIO_V1
  ATTRIBUTE INSTANCE = DIPSWs_4Bit
  PARAMETER num_bits = 4, IO_IS=num_bits
  PARAMETER is_dual = 0, IO_IS=is_dual 
  PARAMETER bidir_data = 1, IO_IS=is_bidir        # Non-Bidir data pins
  PARAMETER all_inputs = 1, IO_IS=all_inputs

  PORT SW_0 = SW_0, IO_IS = gpio_io[0]
  PORT SW_1 = SW_1, IO_IS = gpio_io[1]
  PORT SW_2 = SW_2, IO_IS = gpio_io[2]
  PORT SW_3 = SW_3, IO_IS = gpio_io[3]
END

# 5 Push Buttons
BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_GPIO_V1
  ATTRIBUTE INSTANCE = PushButtons_5Bit
  PARAMETER num_bits = 5, IO_IS=num_bits
  PARAMETER is_dual = 0, IO_IS=is_dual 
  PARAMETER bidir_data = 1, IO_IS=is_bidir        # Non-Bidir data pins
  PARAMETER all_inputs = 1, IO_IS=all_inputs

  PORT PB_ENTER = PB_ENTER, IO_IS = gpio_io[0]
  PORT PB_UP    = PB_UP,    IO_IS = gpio_io[1]
  PORT PB_DOWN  = PB_DOWN,  IO_IS = gpio_io[2]
  PORT PB_LEFT  = PB_LEFT,  IO_IS = gpio_io[3]
  PORT PB_RIGHT = PB_RIGHT, IO_IS = gpio_io[4]
END

# Total 512 MB arranged as 64Mx64
# Uses  Micron Tech MT8VDDT6464A  512MB unbufferd DIMM CL = 2.5 (512 MB dual rank) 
# OR uses Kingston KVR266X64C25/512 512 MB 266 Mhz DDR PC2100 DIMM CL2.5 (512 MB dual rank) 
BEGIN IO_INTERFACE
 ATTRIBUTE IOTYPE = XIL_DDR_V1
 ATTRIBUTE INSTANCE = DDR_512MB_64Mx64_rank2_row13_col10_cl2_5
 ATTRIBUTE EXCLUSIVE = ddr_1rank_2rank
 ATTRIBUTE ALERT = 'Micron Tech MT8VDDT6464A or Kingston KVR266X64C25/512 512MB unbufferd duak rank DIMM module minimum clock frequency of 75Mhz to operate properly.'
 PARAMETER C_NUM_BANKS_MEM = 2, IO_IS=C_NUM_BANKS_MEM
 PARAMETER C_MEM0_BASEADDR = 0x00000000, IO_IS=C_BASEADDR, SHORT_DESC=DDR_SDRAM_64Mx64 Dual Rank
 PARAMETER C_MEM0_HIGHADDR = 0x0fffffff, IO_IS=C_HIGHADDR
 PARAMETER C_MEM1_BASEADDR = 0x10000000, IO_IS=C_MEM1_BASEADDR
 PARAMETER C_MEM1_HIGHADDR = 0x1fffffff, IO_IS=C_MEM1_HIGHADDR
 PARAMETER C_NUM_CLK_PAIRS = 3, IO_IS=C_NUM_CLK_PAIRS
 PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 1, IO_IS=C_INCLUDE_BURST_CACHELN_SUPPORT
 PARAMETER C_REG_DIMM = 0, IO_IS=C_REG_DIMM
 PARAMETER C_DDR_TMRD = 20000, IO_IS=C_DDR_TMRD
 PARAMETER C_DDR_TWR = 20000, IO_IS=C_DDR_TWR
 PARAMETER C_DDR_TRAS = 60000, IO_IS=C_DDR_TRAS
 PARAMETER C_DDR_TRC = 90000, IO_IS=C_DDR_TRC
 PARAMETER C_DDR_TRFC = 100000, IO_IS=C_DDR_TRFC
 PARAMETER C_DDR_TRCD = 30000, IO_IS=C_DDR_TRCD
 PARAMETER C_DDR_TRRD = 20000, IO_IS=C_DDR_TRRD
 PARAMETER C_DDR_TRP = 30000, IO_IS=C_DDR_TRP
 PARAMETER C_DDR_TREFC = 70300000, IO_IS=C_DDR_TREFC
 PARAMETER C_DDR_AWIDTH = 13, IO_IS=C_DDR_AWIDTH
 PARAMETER C_DDR_COL_AWIDTH = 10, IO_IS=C_DDR_COL_AWIDTH
 PARAMETER C_DDR_BANK_AWIDTH = 2, IO_IS=C_DDR_BANK_AWIDTH
 PARAMETER C_DDR_DWIDTH = 64, IO_IS=C_DDR_DWIDTH
# Support for 64bit opb_ddr controller starts in EDK 7.1.2
 PORT A0  = ddr_1rank_2rank_addr_0_,  IO_IS=address[12]
 PORT A1  = ddr_1rank_2rank_addr_1_,  IO_IS=address[11]
 PORT A2  = ddr_1rank_2rank_addr_2_,  IO_IS=address[10]
 PORT A3  = ddr_1rank_2rank_addr_3_,  IO_IS=address[9]
 PORT A4  = ddr_1rank_2rank_addr_4_,  IO_IS=address[8]
 PORT A5  = ddr_1rank_2rank_addr_5_,  IO_IS=address[7]
 PORT A6  = ddr_1rank_2rank_addr_6_,  IO_IS=address[6]
 PORT A7  = ddr_1rank_2rank_addr_7_,  IO_IS=address[5]
 PORT A8  = ddr_1rank_2rank_addr_8_,  IO_IS=address[4]
 PORT A9  = ddr_1rank_2rank_addr_9_,  IO_IS=address[3]
 PORT A10 = ddr_1rank_2rank_addr_10_, IO_IS=address[2]
 PORT A11 = ddr_1rank_2rank_addr_11_, IO_IS=address[1]
 PORT A12 = ddr_1rank_2rank_addr_12_, IO_IS=address[0]
 PORT BA0 = ddr_1rank_2rank_ba_0_,    IO_IS=bank_addr[1]
 PORT BA1 = ddr_1rank_2rank_ba_1_,    IO_IS=bank_addr[0]
 PORT CAS = ddr_1rank_2rank_cas_n,    IO_IS=col_addr_select

 PORT CKE0 = ddr_2rank_cke_0_,  IO_IS=clk_enable[1]
 PORT CKE1 = ddr_2rank_cke_1_,  IO_IS=clk_enable[0]
 PORT CS0  = ddr_2rank_cs_n_0_, IO_IS=chip_select[1]