📄 initfuncs.c
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*(volatile unsigned long*) STI7710_LMI_SCR = 0x4;
*(volatile unsigned long*) STI7710_LMI_SCR = 0x4;
/*## Mode Register Set - Burst 8, Sequential, CAS 3, Test off, DLL running*/
*(volatile unsigned long*) STI7710_LMI_SDMR0 = 0x0033;
*(volatile unsigned long*) STI7710_LMI_SDMR1 = 0x0033;
/*## Set CPU back to Normal SDRAM operation*/
*(volatile unsigned long*) STI7710_LMI_SCR = 0x0;
/*## Config Complete*/
}
/*
###########################################################################
## Set up the EMI for five banks ##
## bank0 8MB x 16bits ##
## bank1 32MB x 16bits ##
## bank2 32MB x 16bits ##
## bank3 32MB x 16bits ##
## bank4 32MB x 16bits ##
###########################################################################
*/
static void MB391_ConfigureEmi(void)
{
/*## Ensure all EMI control registers are unlocked
## at reset the state of these regs is 'undefined'*/
*(volatile unsigned long*) STI7710_EMI_LOCK = 0x00000000;
*(volatile unsigned long*) STI7710_EMI_STATUS_LOCK =0x00000000;
/* ## Number of EMI Banks : Enable all banks*/
*(volatile unsigned long*) STI7710_EMI_BANK_ENABLE =0x00000006;
/*
## EMI Bank base addresses
## NOTE: bits [0,7] define top address bits [22,29] of bank
*/
/*## Bank 0 - 16MBytes ST M58LW064D Flash */
*(volatile unsigned long*)STI7710_EMI_BANK0_BASE =0x00000003; /*## 0x40000000 - 0x40FFFFFF*/
/*## Bank 1 - 16MBytes EPLD Configured as 16-bit peripheral*/
*(volatile unsigned long*)STI7710_EMI_BANK1_BASE =0x00000007; /*## 0x41000000 - 0x41FFFFFF*/
/*## Bank 2 - 16MBytes Stem0/1 Configured as 16-bit peripheral*/
*(volatile unsigned long*)STI7710_EMI_BANK2_BASE =0x0000000B; /*## 0x42000000 - 0x42FFFFFF*/
/*## Bank 3 - 16MBytes ATAPI configured as 16-bit peripheral*/
*(volatile unsigned long*)STI7710_EMI_BANK3_BASE =0x0000000F; /*## 0x43000000 - 0x43FFFFFF*/
/* ## Bank 4 - 16MBytes DVBCI configured as 16-bit peripheral*/
*(volatile unsigned long*)STI7710_EMI_BANK4_BASE =0x00000013; /*## 0x44000000 - 0x44FFFFFF*/
/*
##------------------------------------------------------------------------------
## Program bank functions
##------------------------------------------------------------------------------
##------------------------------------------------------------------------------
## Bank 0 - 8MBytes ST M58LW064D Flash
##------------------------------------------------------------------------------
## Parameters: -weuseoeconfig 0 -waitpolarity 0 -latchpoint 1 -datadrivedelay 0
## -busreleasetime 2 -csactive 3 -oeactive 1 -beactive 2 -portsize 16
## -devicetype 1
## -cyclenotphaseread 1 -accesstimeread 1d -cse1timeread 2
## -cse2timeread 0 -oee1timeread 0 -oee2timeread 0 -bee1timeread 0
## -bee2timeread 0
## -cyclenotphasewrite 1 -accesstimewrite 1d -cse1timewrite 2
## -cse2timewrite 2 -oee1timewrite 0 -oee2timewrite 0 -bee1timewrite 0
## -bee2timewrite 0
## -strobeonfalling 0 -burstsize 0 -datalatency 0 -dataholddelay 0
## -burstmode 0
*/
*(volatile unsigned long*)STI7710_EMI_BANK0_DATA0 =0x001016D1;
*(volatile unsigned long*)STI7710_EMI_BANK0_DATA1 =0x8B200000; /* 110ns */
*(volatile unsigned long*)STI7710_EMI_BANK0_DATA2 =0x8B220000; /* 110ns */
*(volatile unsigned long*)STI7710_EMI_BANK0_DATA3 =0x00000000;
/*
##------------------------------------------------------------------------------
## Bank 1 - 16MBytes EPLD Configured as 16-bit peripheral
##------------------------------------------------------------------------------
## Parameters: -weuseoeconfig 0 -waitpolarity 0 -latchpoint 1 -datadrivedelay 0
## -busreleasetime 2 -csactive 3 -oeactive 1 -beactive 2 -portsize 16
## -devicetype 1
## -cyclenotphaseread 1 -accesstimeread 1d -cse1timeread 2
## -cse2timeread 0 -oee1timeread 0 -oee2timeread 0 -bee1timeread 0
## -bee2timeread 0
## -cyclenotphasewrite 1 -accesstimewrite 1d -cse1timewrite 2
## -cse2timewrite 2 -oee1timewrite 0 -oee2timewrite 0 -bee1timewrite 0
## -bee2timewrite 0
## -strobeonfalling 0 -burstsize 0 -datalatency 0 -dataholddelay 0
## -burstmode 0
*/
*(volatile unsigned long*)STI7710_EMI_BANK1_DATA0= 0x001016D1; /*##BE not active during rd*/
*(volatile unsigned long*)STI7710_EMI_BANK1_DATA1= 0x9d200000;
*(volatile unsigned long*)STI7710_EMI_BANK1_DATA2= 0x9d220000;
*(volatile unsigned long*)STI7710_EMI_BANK1_DATA3= 0x00000000;
/*
##------------------------------------------------------------------------------
## Bank 2 - 16MBytes STEM0/1 Configured as 16-bit peripheral
##------------------------------------------------------------------------------
## Parameters: -weuseoeconfig 0 -waitpolarity 0 -latchpoint 1 -datadrivedelay 0
## -busreleasetime 2 -csactive 3 -oeactive 1 -beactive 2 -portsize 16
## -devicetype 1
## -cyclenotphaseread 1 -accesstimeread 1d -cse1timeread 2
## -cse2timeread 0 -oee1timeread 0 -oee2timeread 0 -bee1timeread 0
## -bee2timeread 0
## -cyclenotphasewrite 1 -accesstimewrite 1d -cse1timewrite 2
## -cse2timewrite 2 -oee1timewrite 0 -oee2timewrite 0 -bee1timewrite 0
## -bee2timewrite 0
## -strobeonfalling 0 -burstsize 0 -datalatency 0 -dataholddelay 0
## -burstmode 0
*/
*(volatile unsigned long*)STI7710_EMI_BANK2_DATA0 =0x001016D1; /*##BE not active during rd*/
*(volatile unsigned long*)STI7710_EMI_BANK2_DATA1 =0x9d200000;
*(volatile unsigned long*)STI7710_EMI_BANK2_DATA2 =0x9d220000;
/* ## poke -d (STI7710_EMI_BANK2_DATA2) 0x9d200022 ##<-- Value optimized for DB511 */
*(volatile unsigned long*)STI7710_EMI_BANK2_DATA3 =0x00000000;
/*
##------------------------------------------------------------------------------
## Bank 3 - 16MBytes Atapi Configured as 16-bit peripheral
##------------------------------------------------------------------------------
##
## Parameters: -weuseoeconfig 0 -waitpolarity 0 -latchpoint 16 -datadrivedelay 31
## -busreleasetime 0 -csactive 3 -oeactive 3 -beactive 0 -portsize 16
## -devicetype 1
## -cyclenotphaseread 1 -accesstimeread 62 -cse1timeread 0
## -cse2timeread 2 -oee1timeread 8 -oee2timeread 15 -bee1timeread 2
## -bee2timeread 1
## -cyclenotphasewrite 1 -accesstimewrite 62 -cse1timewrite 0
## -cse2timewrite 2 -oee1timewrite 8 -oee2timewrite 15 -bee1timewrite 2
## -bee2timewrite 2
## -strobeonfalling 0 -burstsize 2 -datalatency 2 -dataholddelay 2
## -burstmode 0
*/
*(volatile unsigned long*)STI7710_EMI_BANK3_DATA0= 0x010f8791;
*(volatile unsigned long*)STI7710_EMI_BANK3_DATA1= 0xbe028f21;
*(volatile unsigned long*)STI7710_EMI_BANK3_DATA2= 0xbe028f21;
*(volatile unsigned long*)STI7710_EMI_BANK3_DATA3= 0x0000000a;
/*
##------------------------------------------------------------------------------
## Bank 4 - 16MBytes DVBCI Configured as 16-bit peripheral
##------------------------------------------------------------------------------
## Parameters: -weuseoeconfig 0 -waitpolarity 0 -latchpoint 1 -datadrivedelay 0
## -busreleasetime 2 -csactive 3 -oeactive 1 -beactive 2 -portsize 16
## -devicetype 1
## -cyclenotphaseread 1 -accesstimeread 1d -cse1timeread 2
## -cse2timeread 0 -oee1timeread 0 -oee2timeread 0 -bee1timeread 0
## -bee2timeread 0
## -cyclenotphasewrite 1 -accesstimewrite 1d -cse1timewrite 2
## -cse2timewrite 2 -oee1timewrite 0 -oee2timewrite 0 -bee1timewrite 0
## -bee2timewrite 0
## -strobeonfalling 0 -burstsize 0 -datalatency 0 -dataholddelay 0
## -burstmode 0
*/
*(volatile unsigned long*)STI7710_EMI_BANK4_DATA0= 0x001016D1; /*##BE not active during rd*/
*(volatile unsigned long*)STI7710_EMI_BANK4_DATA1= 0x9d200000;
*(volatile unsigned long*)STI7710_EMI_BANK4_DATA2= 0x9d220000;
*(volatile unsigned long*)STI7710_EMI_BANK4_DATA3= 0x00000000;
/*
## ------- Program Other EMI Registers -------- ##
## flash runs @ 1/3 bus clk
## Enable PCMCIA support in bank 3 & 4
*/
*(volatile unsigned long*)STI7710_EMI_GEN_CFG =0x0000000c;
*(volatile unsigned long*)STI7710_EMI_FLASH_CLK_SEL = 0x00000002;
*(volatile unsigned long*)STI7710_EMI_CLK_ENABLE =0x00000001;
}
/*
##############################################################################
## Name : sti77100_init_clocks
## Purpose : Initialise the 7710 PLL's and synthesizers
## In : -
## Note : -
##############################################################################
*/
static void STi7710InitPLL(int targetfrequency)
{
volatile unsigned long temp;
/*
#####################################################
## Configure the PLL ##
#####################################################
*/
/*## Slow the clocks (lmi_async_mode = 0 ) */
temp = *(volatile unsigned long*)STI7710_PLL_CLOCKGEN_CTRL_0;
temp &= 0x0000FFFF;
temp |= 0x5aa50000;
temp &= 0xffffffef;
*(volatile unsigned long*)STI7710_PLL_CLOCKGEN_CTRL_0 = temp;
Delay(5);
/*## Reset LMI Pad Logic and TMDS macrocell*/
*(volatile unsigned long*)STI7710_RESET_CTRL_1 = 0x5AA50003;
Delay(5);
/*## Releasing the LMI pad reset*/
*(volatile unsigned long*)STI7710_RESET_CTRL_1 = 0x5AA50000;
Delay(5);
/*## Stop PLL1 ( poff =1 ) */
temp = *(volatile unsigned long*)STI7710_PLL_CONFIG_2;
temp &= 0x0000FFFF;
temp |= 0x5aa50000;
temp |= 0x2;
*(volatile unsigned long*)STI7710_PLL_CONFIG_2 = temp;
/*
## Set Mdiv/Ndiv and PDiv, (CPU and RAM clock speeds)
##
## ClockSpeed = (27 * (Ndiv+1) * 2)/((Mdiv+1) * 2pow(Pdiv+1))
##
## Mdiv = (27-1), Ndiv = (target_frequency-1), Pdiv = 0
*/
temp = 0x5aa5001a |(( (volatile unsigned long)targetfrequency-1)<<8);
*(volatile unsigned long*) STI7710_PLL_CONFIG_0 = temp;
/*
write CPU/DDR Frequency = (target_frequency) MHz
*/
/* ## restart pll and wait for lock ( poff=0 )*/
temp = *(volatile unsigned long*)STI7710_PLL_CONFIG_2;
temp &= 0x0000FFFF;
temp |= 0x5aa50000;
temp &= 0xfffffffd;
*(volatile unsigned long*) STI7710_PLL_CONFIG_2 = temp;
/*## And Wait for PLL to Lock, this is always successful.*/
temp = 0;
while(temp != 1){
temp = *(volatile unsigned long*)STI7710_PLL_CONFIG_2;
temp = temp >> 8;
temp &= 0x1;
}
/*
## Full speed for LMI config
## (200Mhz with dll3_nrst = 0 or dll3_bypass = 1)
*/
temp = *(volatile unsigned long*)STI7710_PLL_CLOCKGEN_CTRL_0;
temp &= 0x0000FFFF;
temp |= 0x5aa50000;
temp |= 0x00000018;
*(volatile unsigned long*)STI7710_PLL_CLOCKGEN_CTRL_0 = temp;
/*$$ = 0*/
/*return(0);*/
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