initfuncs.c

ST5100 driver files for ST chipset

/****************************************************************************

File Name   : initfuncs.c

Description : Initialization functions, used incase of Boot from Flash.

Copyright (C) 2004, ST Microelectronics


****************************************************************************/


#include <initfuncs.h>	/*PrePokeLoopCallback & PostPokeLoopCallback*/
#include "stsys.h"	/*if you wanna use reg. write & read procedures instead of direct write&read*/
#include "reg7710.h"	/*sti7710 reg. offsets and base addresses*/


static void Delay(int time);
#pragma ST_nolink(Delay)

static void MB391_ConfigureLmiDDR200(void);
#pragma ST_nolink(MB391_ConfigureLmiDDR200)

static void STi7710InitDLL(int mode);
#pragma ST_nolink(STi7710InitDLL)

static void STi7710InitPLL(int target_frequency);
#pragma ST_nolink(STi7710InitPLL)

static void MB391_ConfigureEmi(void);
#pragma ST_nolink(MB391_ConfigureEmi)

static void STi7710InitFrequencySynths(void);
#pragma ST_nolink(STi7710InitFrequencySynths)

static void STi7710_InterconnectConfig(void);
#pragma ST_nolink(STi7710_InterconnectConfig)


/*-------------------------------------------------------------------------
 * Function : PostPokeLoopCallback
 * Input    : None
 * Output   :
 * Return   : None
 * ----------------------------------------------------------------------*/
void PostPokeLoopCallback(void)
{
	/*tbd /  AC why do these here opposed to the others*/
  
  
  MB391_ConfigureEmi();
  
  STi7710InitFrequencySynths();

  
}

/*-------------------------------------------------------------------------
 * Function : PrePokeLoopCallback
 * Input    : None
 * Output   :
 * Return   : None
 * Comment  : Function automatically called after the poke loop
 * ----------------------------------------------------------------------*/
void PrePokeLoopCallback(void)
{
    /*U8 failure = 1;*/
 
    /*## Configure Register Addresses*/
    /*Sti7710Registers*/
/*
    ## Set up the PLL's
    ## Target speed can be configured, 
    ## The parameter passed in to STi7710InitPLL is your target speed in MHz
    ## Note the Default value is 175MHz for cut1x & 2x, 200 MHz for cut3x
*/    
   
#ifdef STI7710_CUT2x
	STi7710InitPLL(175);
#else
	STi7710InitPLL(200);
#endif

	/* optimum interconnect settings */
	STi7710_InterconnectConfig();

    /*## Configure the LMI*/
    MB391_ConfigureLmiDDR200();

    /*## Configure the EMI */
    
    STi7710InitDLL(1);		/*synchronous*/

/*    MB391_ConfigureEmi();*/

    
/*  STi7710InitFrequencySynths();*/

/*    
    ## Configure DLLS 
    ## 1 = Synchronous Mode 
    ## 2 = Asynchronous Mode 
*/

/*WILL BE USED LATER for step/mode = 2/ AC */
    /*failure = STi7710InitDLL(1);*/
/*    if (failure == ){
        write Clocks in Async Mode
        ##Attempt clock init with Async Mode
        STi7710InitDLL(2);
    }*/

}

/* optimum interconnect settings */
void STi7710_InterconnectConfig(void)	
{
	*(volatile unsigned long*)(0x20104000) = 8;
	*(volatile unsigned long*)(0x20104004) = 8;
	*(volatile unsigned long*)(0x20104200) = 10;
	*(volatile unsigned long*)(0x20104204) = 8;
	*(volatile unsigned long*)(0x20104208) = 4;
	*(volatile unsigned long*)(0x2010420C) = 4;
	*(volatile unsigned long*)(0x20104210) = 2;
	*(volatile unsigned long*)(0x20104214) = 2;
	*(volatile unsigned long*)(0x20104400) = 4;
	*(volatile unsigned long*)(0x20104408) = 2;
	*(volatile unsigned long*)(0x20104600) = 6;
	*(volatile unsigned long*)(0x20104800) = 14;
	*(volatile unsigned long*)(0x20104804) = 8;
	*(volatile unsigned long*)(0x20104808) = 6;
	*(volatile unsigned long*)(0x2010480C) = 4;
	*(volatile unsigned long*)(0x20104810) = 2;
	*(volatile unsigned long*)(0x20104818) = 12;
	*(volatile unsigned long*)(0x20104870) = 3;
	*(volatile unsigned long*)(0x20104A04) = 4;
	*(volatile unsigned long*)(0x20104A08) = 2;
}

static void Delay(int waitfor)
{
  volatile int m=0;
    for ( ;waitfor>0; waitfor--)
    {       
        for (m=0;m<1000;m++)
        {
		}  
    }

}

/*
##----------------------------------------------------------------------------
## Procedure Name : MB391_ConfigureLmiDDR200
## Purpose : Initialisation of LMI for MB391 board (CAS = 3.0 ns)
## Note : Set up the LMI for 256Mbit DDR-SDRAM using 2 off
## 4Mbit x 16 x 4 bank devices (Samsung K4H561638D-TCCC)
## DDR Clock = 133 MHz @ CAS 2.0 (LMI Spec: ADCS 7483542)
##----------------------------------------------------------------------------
*/
static void MB391_ConfigureLmiDDR200(void)
{
	volatile unsigned long data;
/*    ## Init for Samsung K4H561638F-TCCC DDR SDRAM*/
/*    ## See http://www.samsung.com/Products/Semiconductor/DRAM/TechnicalInfo/ddr-device_operation_timing_2003_04_17.pdf */

/*    write Setup 2 * Samsung K4H561638F-TCCC DDR RAM*/
  
/*    ## Set LMI_COC_UPPER Register, bits [63:32]   (LMI Pad logic)
    ## poke -d (LMI_COC_UPPER) 		0x002C6710
    ## poke -d (LMI_COC_UPPER)   	0x000C6720
*/    
    *(volatile unsigned long*) STI7710_LMI_COC_UPPER = 0x000C6750;
/*
    ## Set LMI_COC_LOWER Register, bits [31:0]  (LMI Pad logic)
    ## Bits [19:18] Compensation mode DDR
    ## Bits [17:16] Pad strenght 		 (0x0:5pF, 0x1:15pF, 0x2:25pF, Ox3:35pF)
    ## Bits [15:14] output Impedance (0x0:25Ohm, 0x1:40Ohm, 0x2:55Ohm, Ox3:70Ohm)
    ## Bit  [13]    DLL preset reset value enable
*/
    *(volatile unsigned long*) STI7710_LMI_COC_LOWER = 0x00002000;
    data = *(volatile unsigned long*) (STI7710_LMI_COC_LOWER);
    data = (data | 0x00<<16 | 0x00<<14);
    *(volatile unsigned long*) STI7710_LMI_COC_LOWER = data;
/*
    ## SDRAM Mode Register
    ## Set Refresh Interval, Enable Refresh, 32-bit bus,
    ## Grouping Disabled, DDR-SDRAM, Enable.
    ## Bits[27:16]: Refresh Interval = 7.8 microseconds (8K/64ms)
    ## @  50MHz =  391 clk cycles -> 0x186
    ## @  75MHz =  585 clk cycles -> 0x249
    ## @ 100MHz =  780 clk cycles -> 0x30C
    ## @ 125MHz =  975 clk cycles -> 0x3CF
    ## @ 133MHz = 1040 clk cycles -> 0x410
    ## @ 166MHz = 1300 clk cycles -> 0x514
    ## @ 200MHz = 1500 clk cycles -> 0x5DC  <--
*/    
    *(volatile unsigned long*) STI7710_LMI_MIM = 0x05DC0343;
/*
    ##  SDRAM Device Samsung K4H561638F-TCCC
    ##  For 200MHz (5ns) operation:
    ##  3 clks RAS_precharge, Trp;
    ##  3 clks RAS_to_CAS_delay, Trcd-r;
    ##  11 clks RAS cycle time, Trc;
    ##  8 clks RAS Active time, Tras;
    ##  2 clks RAS_to_RAS_Active_delay, Trrd;
    ##  3 clks Last write to PRE/PALL period SDRAM, Twr;
    ##  3 clks CAS Latency;
    ##  14 clks Auto Refresh RAS cycle time, Trfc;
    ##  Enable Write to Read interruption;
    ##  2 clk  Write to Read interruption, Twtr;
    ##  Next 2 params not in Datasheeet, but see ADCS 7483542_A
    ##  3 clks RAS_to_CAS_delay, Trcd-w;
    ## (200/16)=13 clks Exit self-refresh to next command, Tsxsr;
*/    
    *(volatile unsigned long*) STI7710_LMI_STR = 0x35b06455;
/*  
    ## SDRAM Row Attribute 0 & 1 Registers
    ## UBA = 32MB + Base Adr, Quad-bank, Shape 13x9,
    ## Bank Remapping Disabled
    ##
    ##  LMI base address 	0xC0000000
    ##  Memory size 32MB * 2 	0x04000000
    ##  Row UBA value    	0xC400
    ##
*/
    *(volatile unsigned long*) STI7710_LMI_SDRA0 = 0xC4001900;
/*
    ##  We just have one Row connected to cs0, so we must program UBA0 = UBA1,
    ##  following LMI specification
*/
    *(volatile unsigned long*) STI7710_LMI_SDRA1 = 0xC4001900;
/*
    ##------------------------------------------------------------------------
    ## Initialisation Sequence for K4H561638F-TCCC DDR-SDRAM Device
    ##------------------------------------------------------------------------
*/    
    /*## 200 microseconds to settle clocks*/
    Delay (200);
/*
    ## SDRAM Control Register
    ## Clock enable
*/
    *(volatile unsigned long*) STI7710_LMI_SCR = 0x3;

    /*## 200us required of stable power and stable clock signal*/
    Delay (200);

    /*## NOP enable*/
    *(volatile unsigned long*) STI7710_LMI_SCR = 0x1;

    /*## Precharge all banks*/
    *(volatile unsigned long*) STI7710_LMI_SCR = 0x2;
/*
    ## According to the Specs, the mode register is mapped thus...
    ## RAM - BA1 Ba0 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00
    ## CPU - A14 A13 A17 A16 A15 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03

    ## Extended Mode Register Set - Enable DLL - Weak output Driver
*/    
    *(volatile unsigned long*) STI7710_LMI_SDMR0 = 0x0402;
    *(volatile unsigned long*) STI7710_LMI_SDMR1 = 0x0402;
/*
    ## Or for Normal Drive strengh (comment out above 2 lines) use these..
    ## Extended Mode Register Set - Enable DLL - Normal Output Driver
    ## poke -d (LMI_SDMR0)    0x0400
    ## poke -d (LMI_SDMR1)    0x0400
*/
    /*## Mode Register Set - Reset DLL, Burst 8, Sequential, CAS 3, Test off, DLL reset */
    *(volatile unsigned long*) STI7710_LMI_SDMR0 = 0x0133;
    *(volatile unsigned long*) STI7710_LMI_SDMR1 = 0x0133;
 
    /*## 200 clock cycles required to lock DLL*/
    Delay (100);

    /*## Precharge all banks*/
    *(volatile unsigned long*) STI7710_LMI_SCR =   0x2;

    /*## 2 Auto Refresh Cycles */