📄 drv_channel.c
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if(!g_ChannelFlag[unitId].fgLOCK) g_ChInfoWork[unitId].ucAGCLevel = 0; // unlock state
#if defined(SUPPORT_UNLOCK_SIGNAL_SHOW)
if(ucVAGCA > (unsigned char)45)
{
if(ucVAGCA >(unsigned char)90)
{
ucVAGCA = 90;
}
ucVAGCA = ucVAGCA - 45;
ucVAGCA = (unsigned char)((ucVAGCA * 100)/45);
}
else
{
ucVAGCA = 0;
}
#endif
ucVAGCA = ucVAGCA*255/100;
g_ChInfoWork[unitId].ucAGCLevel = ucVAGCA;
return g_ChInfoWork[unitId].ucAGCLevel;
} // end of drv_channel_GetAGCLevel
/////////////////////////////////////////////////////////////////////////////////
// Function : drv_channel_GetVBER
// Description :
// Input :
// Output :
// Return :
/////////////////////////////////////////////////////////////////////////////////
void drv_channel_GetVBER(unsigned char unitId,unsigned long *VBER)
{
#ifdef THOMSON_MM
#else
unsigned long VBER_LSB, VBER_MID, VBER_MSB;
// read the VBER_LSB[7:0], VBER_MID[15:8], VBER_MSB[19:16]
drv_ch_i2c_DEMODRead(unitId, DEMOD_REG_VBER_LSB, &DEMOD_REG[unitId][DEMOD_REG_VBER_LSB], 1);
drv_ch_i2c_DEMODRead(unitId, DEMOD_REG_VBER_MID, &DEMOD_REG[unitId][DEMOD_REG_VBER_MID], 1);
drv_ch_i2c_DEMODRead(unitId, DEMOD_REG_VBER_MSB, &DEMOD_REG[unitId][DEMOD_REG_VBER_MSB], 1);
VBER_LSB = DEMOD_REG[unitId][DEMOD_REG_VBER_LSB];
VBER_MID = DEMOD_REG[unitId][DEMOD_REG_VBER_MID];
VBER_MSB = DEMOD_REG[unitId][DEMOD_REG_VBER_MSB];
*VBER = VBER_LSB + (VBER_MID << 8) + ((VBER_MSB & 0x0000000F) << 16);
// read the BER depth to apply the correction
switch(g_ucPVBERDepth[unitId] & PVBER_MASKING)
{
case PVBER_10E5:
*VBER *= 85;
*VBER /= 100;
break;
case PVBER_10E6:
*VBER *= 98;
*VBER /= 100;
break;
case PVBER_10E7:
*VBER *= 99;
*VBER /= 100;
break;
case PVBER_10E8:
break;
}
#endif
} // end of drv_channel_GetVBER
/////////////////////////////////////////////////////////////////////////////////
// Function : drv_channel_GetFEC
// Description :
// Input :
// Output :
// Return :
/////////////////////////////////////////////////////////////////////////////////
void drv_channel_GetFEC(unsigned char unitId)
{
#ifdef THOMSON_MM
#else
unsigned char ucFEC;
// drv_ch_i2c_DEMODRead(unitId, DEMOD_REG_RATE, &ucFEC, 1);
// ucFEC = (ucFEC & 0x70) >> 4;
ucFEC = PN1010_Get_Register(unitId,0x32)&0x07;
switch(ucFEC)
{
case 0x00: // 1/2
g_ChInfoWork[unitId].Tuner.Sat.ucConvolutionCode = 0x00;
break;
case 0x01: // 2/3
g_ChInfoWork[unitId].Tuner.Sat.ucConvolutionCode = 0x01;
break;
case 0x02: // 3/4
g_ChInfoWork[unitId].Tuner.Sat.ucConvolutionCode = 0x02;
break;
case 0x04: // 5/6
g_ChInfoWork[unitId].Tuner.Sat.ucConvolutionCode = 0x03;
break;
case 0x06: // 7/8
g_ChInfoWork[unitId].Tuner.Sat.ucConvolutionCode = 0x04;
break;
}
#endif
} // end of drv_channel_GetFEC
/////////////////////////////////////////////////////////////////////////////////
// Function : drv_channel_GetNEST
// Description : NEST[7:0] 0x1C
// - the current value of the noise power estimation
// - give a estimation of signal quality
// - value 0 is good signal (0 ~ 255)
// Input :
// Output :
// Return :
/////////////////////////////////////////////////////////////////////////////////
void drv_channel_GetNEST(unsigned char unitId, unsigned char *NEST)
{
#ifdef THOMSON_MM
#else
unsigned char ucNEST_1st, ucNEST_2nd;
int i;
for(i=0; i<5; i++)
{
drv_ch_i2c_DEMODRead(unitId, DEMOD_REG_NEST, &ucNEST_1st, 1);
drv_ch_i2c_DEMODRead(unitId, DEMOD_REG_NEST, &ucNEST_2nd, 1);
if (ucNEST_1st == ucNEST_2nd)
{
*NEST = ucNEST_2nd;
return;
}
}
/* last read value */
*NEST = ucNEST_2nd;
#endif
} // end of drv_channel_GetNEST
/////////////////////////////////////////////////////////////////////////////////
// Function : drv_channel_SetPVBER
// Description : program the number of bits of the sequence length
// where the Viterbi output Bit Error Rate is computed.
// The number of bits varies from 10^5 to 10^8 bits.
// Input :
// Output :
// Return :
/////////////////////////////////////////////////////////////////////////////////
void drv_channel_SetPVBER(unsigned char unitId)
{
if (g_ChInfoWork[unitId].Tuner.Sat.wSymbolRate < 12000) // < 5Ms/s
{
// for 1~12Ms/s BER display
g_ulBER_DISP[unitId][10] = BER_DISP2_100;
g_ulBER_DISP[unitId][9] = BER_DISP2_90;
g_ulBER_DISP[unitId][8] = BER_DISP2_80;
g_ulBER_DISP[unitId][7] = BER_DISP2_70;
g_ulBER_DISP[unitId][6] = BER_DISP2_60;
g_ulBER_DISP[unitId][5] = BER_DISP2_50;
g_ulBER_DISP[unitId][4] = BER_DISP2_40;
g_ulBER_DISP[unitId][3] = BER_DISP2_30;
g_ulBER_DISP[unitId][2] = BER_DISP2_20;
g_ulBER_DISP[unitId][1] = BER_DISP2_10;
g_ulBER_DISP[unitId][0] = BER_DISP2_0;
}
else
{
// for 12~45Ms/sBER display
g_ulBER_DISP[unitId][10] = BER_DISP1_100;
g_ulBER_DISP[unitId][9] = BER_DISP1_90;
g_ulBER_DISP[unitId][8] = BER_DISP1_80;
g_ulBER_DISP[unitId][7] = BER_DISP1_70;
g_ulBER_DISP[unitId][6] = BER_DISP1_60;
g_ulBER_DISP[unitId][5] = BER_DISP1_50;
g_ulBER_DISP[unitId][4] = BER_DISP1_40;
g_ulBER_DISP[unitId][3] = BER_DISP1_30;
g_ulBER_DISP[unitId][2] = BER_DISP1_20;
g_ulBER_DISP[unitId][1] = BER_DISP1_10;
g_ulBER_DISP[unitId][0] = BER_DISP1_0;
}
} // end of drv_channel_SetPVBER
/////////////////////////////////////////////////////////////////////////////////
// Function : drv_channel_ResetUncorrectablePacketCounter
// Description : clear counter which memorize the number of uncorrectable packets
// found after a master reset(hard or soft) or between two CLBUNC writing
// CPT_UNCOR[0x18] : bit7 : CLBUNC = 0 => reset counter
// Input :
// Output :
// Return :
/////////////////////////////////////////////////////////////////////////////////
void drv_channel_ResetUncorrectablePacketCounter(unsigned char unitId)
{
#ifdef THOMSON_MM
#else
// reset counter
DEMOD_REG[unitId][DEMOD_REG_CPT_UNCOR] &= ~(DEMOD_REG_BIT_CLBUNC);
drv_ch_i2c_DEMODWrite(unitId, DEMOD_REG_CPT_UNCOR, &DEMOD_REG[unitId][DEMOD_REG_CPT_UNCOR], 1);
// active counter
DEMOD_REG[unitId][DEMOD_REG_CPT_UNCOR] |= DEMOD_REG_BIT_CLBUNC;
drv_ch_i2c_DEMODWrite(unitId, DEMOD_REG_CPT_UNCOR, &DEMOD_REG[unitId][DEMOD_REG_CPT_UNCOR], 1);
#endif
} // end of drv_channel_ResetUncorrectablePacketCounter
/////////////////////////////////////////////////////////////////////////////////
// Function : AS_ReadUncor
// Description : get the number of uncorrectable packets
// Input :
// Output :
// Return :
/////////////////////////////////////////////////////////////////////////////////
unsigned char AS_ReadUncor(unsigned char unitId)
{
#ifdef THOMSON_MM
#else
unsigned char ucCnt;
drv_ch_i2c_DEMODRead(unitId, DEMOD_REG_CPT_UNCOR, &DEMOD_REG[unitId][DEMOD_REG_CPT_UNCOR], 1);
ucCnt = DEMOD_REG[unitId][DEMOD_REG_CPT_UNCOR] & DEMOD_REG_BIT_CPTU;
if(ucCnt > 0) drv_channel_ResetUncorrectablePacketCounter(unitId); // reset counter
return (ucCnt);
#endif
} // end of drv_channel_InitChannelInfo
/////////////////////////////////////////////////////////////////////////////////
// Function : drv_channel_GetBER
// Description :
// Input :
// Output :
// Return :
/////////////////////////////////////////////////////////////////////////////////
unsigned char drv_channel_GetBER(unsigned char unitId)
{
unsigned char ucNEST;
unsigned char ucUncorr;
unsigned long ulBitErr;
int iBer;
#if !defined(SUPPORT_UNLOCK_SIGNAL_SHOW)
if (!g_ChannelFlag[unitId].fgLOCK)
{
g_ChInfoWork[unitId].ucBER = 0; // Unlock
return g_ChInfoWork[unitId].ucBER;
}
#endif
iBer = Snim_Drv_Get_Quality();
iBer = ((iBer * 100)/160);
if((iBer > 10) && (iBer < 50))
iBer += 10;
if(iBer >= 100)
iBer = 99;
g_ChInfoWork[unitId].ucBER = iBer;
//printf("g_ChInfoWork[unitId].ucBER : %x \n",g_ChInfoWork[unitId].ucBER);
return g_ChInfoWork[unitId].ucBER;
} // end of drv_channel_GetBER
/////////////////////////////////////////////////////////////////////////////////
// Function : drv_channel_GetOverLoadStatus
// Description :
// Input :
// Output :
// Return : if Over Load : TRUE, else FALSE
/////////////////////////////////////////////////////////////////////////////////
unsigned char drv_channel_GetOverLoadStatus(unsigned char unitId)
{
#ifdef THOMSON_MM
#else
unsigned char ucCTRL3;
drv_ch_i2c_DEMODRead(unitId, DEMOD_REG_ADCONF, &ucCTRL3, 1);
ucCTRL3 &= DEMOD_REG_BIT_CTRL3;
return ucCTRL3;
#endif
}
/////////////////////////////////////////////////////////////////////////////////
// Function : drv_channel_GetSYNC
// Description :
// Input :
// Output :
// Return :
/////////////////////////////////////////////////////////////////////////////////
void drv_channel_GetSYNC(unsigned char unitId)
{
#ifdef THOMSON_MM
#else
g_ucSYNC[unitId] = PN1010_CheckByteSync(unitId);
printDrvCh(("drv_channel_GetSYNC : g_ucSYNC = 0x%02X \n\r", g_ucSYNC[unitId]));
#endif
} // end of drv_channel_GetSYNC
void drv_channel_SoftresetRegister(unsigned char unitId)
{
#ifdef THOMSON_MM
#else
PN1010_Set_Register(unitId, 0x01, 0x08 ); // Software Reset Enable
PN1010_Set_Register( unitId,0x01, 0x00 ); // Software Reset Disable
#endif
}
void drv_channel_Stream_Disable(unsigned char unitId)
{
#ifdef THOMSON_MM
Snim_Drv_Stream_Disable();
#else
#endif
}
void drv_channel_Stream_Enable(unsigned char unitId)
{
#ifdef THOMSON_MM
Snim_Drv_Stream_Enable();
#else
#endif
}
/////////////////////////////////////////////////////////////////////////////////
// Function : AS_ResetAll
// Description : reset the chip and clear algo. Register not modified
// Input :
// Output :
// Return :
/////////////////////////////////////////////////////////////////////////////////
void AS_ResetAll(unsigned char unitId)
{
#ifdef THOMSON_MM
#else
DEMOD_REG[unitId][DEMOD_REG_CLEAR] &= ~(DEMOD_REG_BIT_CLB);
drv_ch_i2c_DEMODWrite(unitId, DEMOD_REG_CLEAR, &DEMOD_REG[unitId][DEMOD_REG_CLEAR], 1);
VK_TASK_Sleep(2);
DEMOD_REG[unitId][DEMOD_REG_CLEAR] |= DEMOD_REG_BIT_CLB;
drv_ch_i2c_DEMODWrite(unitId, DEMOD_REG_CLEAR, &DEMOD_REG[unitId][DEMOD_REG_CLEAR], 1);
#endif
} // end of AS_ResetAll
/////////////////////////////////////////////////////////////////////////////////
// Function : AS_WriteInitAGCRA
// Description : AGC Offset Ref. Register Default Setting. (value :0x8a)
// Input :
// Output :
// Return : TRUE if error, FALSE if success
/////////////////////////////////////////////////////////////////////////////////
void AS_WriteInitAGCRA(unsigned char unitId)
{
#ifdef THOMSON_MM
#else
DEMOD_REG[unitId][DEMOD_REG_AGCRA] = 0x0A;
#ifdef PHILIPS_TUNER
DEMOD_REG[unitId][DEMOD_REG_AGCRA] |= DEMOD_REG_BIT_PWMOD;
#else
DEMOD_REG[unitId][DEMOD_REG_AGCRA] &= ~(DEMOD_REG_BIT_PWMOD);
#endif
drv_ch_i2c_DEMODWrite(unitId, DEMOD_REG_AGCRA, &DEMOD_REG[unitId][DEMOD_REG_AGCRA], 1);
#endif
} // end of AS_WriteInitAGCRA
/////////////////////////////////////////////////////////////////////////////////
// Function : AS_IQinversion
// Description : search for spectral inversion is deactivated
// Spectruam (I,Q) Change.
// Normal case I,Q , Inversion case Q,I
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