362_init.h

STV0299 Minituner driver, for ST chipset

#define LOCK_DETECT_MSB		240

/*	AGCTAR_LOCK_LSBS	*/
#define R_AGCTAR_LOCK_LSBS		110
#define AUT_AGC_TARGET_LSB		241
#define LOCK_DETECT_LSB		242

/*	AUT_GAIN_EN	*/
#define R_AUT_GAIN_EN		111
#define AUT_ENMODE		243
#define AUT_GAIN2		244

/*	AUT_CFG	*/
#define R_AUT_CFG		112
#define AUT_N		245
#define INT_CHOICE		246
#define INT_LOAD		247

/*	LOCKN	*/
#define R_LOCKN		113
#define LOCKN		248
#define SEL_IQNTAR		249
#define LOCK_DETECT_CHOICE		250

/*	INT_X_3	*/
#define R_INT_X_3		114
#define INT_X3		251

/*	INT_X_2	*/
#define R_INT_X_2		115
#define INT_X2		252

/*	INT_X_1	*/
#define R_INT_X_1		116
#define INT_X1		253

/*	INT_X_0	*/
#define R_INT_X_0		117
#define INT_X0		254

/*	MIN_ERR_X_MSB	*/
#define R_MIN_ERR_X_MSB		118
#define MIN_ERR_X_MSB		255

/*	STATUS_ERR_DA	*/
#define R_STATUS_ERR_DA		119
#define COM_USEGAINTRK		256
#define COM_AGCLOCK		257
#define AUT_AGCLOCK		258
#define MIN_ERR_X_LSB		259

/*	COR_CTL	*/
#define R_COR_CTL		120
#define CORE_ACTIVE		260
#define HOLD		261
#define CORE_STATE_CTL		262

/*	COR_STAT	*/
#define R_COR_STAT		121
#define SCATT_LOCKED		263
#define TPS_LOCKED		264
#define SYR_LOCKED_COR		265
#define AGC_LOCKED_STAT		266
#define CORE_STATE_STAT		267

/*	COR_INTEN	*/
#define R_COR_INTEN		122
#define INTEN		268
#define INTEN_SYR		269
#define INTEN_FFT		270
#define INTEN_AGC		271
#define INTEN_TPS1		272
#define INTEN_TPS2		273
#define INTEN_TPS3		274

/*	COR_INTSTAT	*/
#define R_COR_INTSTAT		123
#define INTSTAT_SYR		275
#define INTSTAT_FFT		276
#define INTSAT_AGC		277
#define INTSTAT_TPS1		278
#define INTSTAT_TPS2		279
#define INTSTAT_TPS3		280

/*	COR_MODEGUARD	*/
#define R_COR_MODEGUARD		124
#define FORCE		281
#define MODE		282
#define GUARD		283

/*	AGC_CTL	*/
#define R_AGC_CTL		125
#define AGC_TIMING_FACTOR		284
#define AGC_LAST		285
#define AGC_GAIN		286
#define AGC_NEG		287
#define AGC_SET		288

/*	AGC_MANUAL1	*/
#define R_AGC_MANUAL1		126
#define AGC_VAL_LO		289

/*	AGC_MANUAL2	*/
#define R_AGC_MANUAL2		127
#define AGC_VAL_HI		290

/*	AGC_TARGET	*/
#define R_AGC_TARGET		128
#define AGC_TARGET		291

/*	AGC_GAIN1	*/
#define R_AGC_GAIN1		129
#define AGC_GAIN_LO		292

/*	AGC_GAIN2	*/
#define R_AGC_GAIN2		130
#define AGC_LOCKED_GAIN2		293
#define AGC_GAIN_HI		294

/*	RESERVED_1	*/
#define R_RESERVED_1		131
#define RESERVED_1		295

/*	RESERVED_2	*/
#define R_RESERVED_2		132
#define RESERVED_2		296

/*	RESERVED_3	*/
#define R_RESERVED_3		133
#define RESERVED_3		297

/*	CAS_CTL	*/
#define R_CAS_CTL		134
#define CCS_ENABLE		298
#define ACS_DISABLE		299
#define DAGC_DIS		300
#define DAGC_GAIN		301
#define CCSMU		302

/*	CAS_FREQ	*/
#define R_CAS_FREQ		135
#define CCS_FREQ		303

/*	CAS_DAGCGAIN	*/
#define R_CAS_DAGCGAIN		136
#define CAS_DAGC_GAIN		304

/*	SYR_CTL	*/
#define R_SYR_CTL		137
#define SICTH_ENABLE		305
#define LONG_ECHO		306
#define AUTO_LE_EN		307
#define SYR_BYPASS		308
#define SYR_TR_DIS		309

/*	SYR_STAT	*/
#define R_SYR_STAT		138
#define SYR_LOCKED_STAT		310
#define SYR_MODE		311
#define SYR_GUARD		312

/*	SYR_NCO1	*/
#define R_SYR_NCO1		139
#define SYR_NCO_LO		313

/*	SYR_NCO2	*/
#define R_SYR_NCO2		140
#define SYR_NCO_HI		314

/*	SYR_OFFSET1	*/
#define R_SYR_OFFSET1		141
#define SYR_OFFSET_LO		315

/*	SYR_OFFSET2	*/
#define R_SYR_OFFSET2		142
#define SYR_OFFSET_HI		316

/*	FFT_CTL	*/
#define R_FFT_CTL		143
#define SHIFT_FFT_TRIG		317
#define FFT_TRIGGER		318
#define FFT_MANUAL		319
#define IFFT_MODE		320

/*	SCR_CTL	*/
#define R_SCR_CTL		144
#define SYRADJDECAY		321
#define SCR_CPEDIS		322
#define SCR_DIS		323

/*	PPM_CTL1	*/
#define R_PPM_CTL1		145
#define MEAN_OFF		324
#define GRAD_OFF		325
#define PPM_MAXFREQ		326
#define PPM_MAXTIM		327
#define PPM_INVSEL		328
#define PPM_SCATDIS		329
#define PPM_BYP		330

/*	TRL_CTL	*/
#define R_TRL_CTL		146
#define TRL_NOMRATE_LSB		331
#define TRL_GAIN_FACTOR		332
#define TRL_LOOPGAIN		333

/*	TRL_NOMRATE1	*/
#define R_TRL_NOMRATE1		147
#define TRL_NOMRATE_LO		334

/*	TRL_NOMRATE2	*/
#define R_TRL_NOMRATE2		148
#define TRL_NOMRATE_HI		335

/*	TRL_TIME1	*/
#define R_TRL_TIME1		149
#define TRL_TOFFSET_LO		336

/*	TRL_TIME2	*/
#define R_TRL_TIME2		150
#define TRL_TOFFSET_HI		337

/*	CRL_CTL	*/
#define R_CRL_CTL		151
#define CRL_DIS		338
#define CRL_GAIN_FACTOR		339
#define CRL_LOOPGAIN		340

/*	CRL_FREQ1	*/
#define R_CRL_FREQ1		152
#define CRL_FOFFSET_LO		341

/*	CRL_FREQ2	*/
#define R_CRL_FREQ2		153
#define CRL_FOFFSET_HI		342

/*	CRL_FREQ3	*/
#define R_CRL_FREQ3		154
#define CRL_FOFFSET_VHI		343

/*	CHC_CTL1	*/
#define R_CHC_CTL1		155
#define MEAN_PILOT_GAIN		344
#define MANMEANP		345
#define DBADP		346
#define DNOISEN		347
#define DCHCPRED		348
#define CHC_INT		349

/*	CHC_SNR	*/
#define R_CHC_SNR		156
#define CHC_SNR		350

/*	BDI_CTL	*/
#define R_BDI_CTL		157
#define BDI_LPSEL		351
#define BDI_SERIAL		352

/*	DMP_CTL	*/
#define R_DMP_CTL		158
#define DMP_SCALING_FACTOR		353
#define DMP_SDDIS		354

/*	TPS_RCVD1	*/
#define R_TPS_RCVD1		159
#define TPS_CHANGE		355
#define BCH_OK		356
#define TPS_SYNC		357
#define TPS_FRAME		358

/*	TPS_RCVD2	*/
#define R_TPS_RCVD2		160
#define TPS_HIERMODE		359
#define TPS_CONST		360

/*	TPS_RCVD3	*/
#define R_TPS_RCVD3		161
#define TPS_LPCODE		361
#define TPS_HPCODE		362

/*	TPS_RCVD4	*/
#define R_TPS_RCVD4		162
#define TPS_GUARD		363
#define TPS_MODE		364

/*	TPS_ID_CELL1	*/
#define R_TPS_ID_CELL1		163
#define TPS_ID_CELL_LO		365

/*	TPS_ID_CELL2	*/
#define R_TPS_ID_CELL2		164
#define TPS_ID_CELL_HI		366

/*	TPS_RCVD5_SET1	*/
#define R_TPS_RCVD5_SET1		165
#define TPS_NA		367
#define TPS_SETFRAME		368

/*	TPS_SET2	*/
#define R_TPS_SET2		166
#define TPS_SETHIERMODE		369
#define TPS_SETCONST		370

/*	TPS_SET3	*/
#define R_TPS_SET3		167
#define TPS_SETLPCODE		371
#define TPS_SETHPCODE		372

/*	TPS_CTL	*/
#define R_TPS_CTL		168
#define TPS_IMM		373
#define TPS_BCHDIS		374
#define TPS_UPDDIS		375

/*	CTL_FFTOSNUM	*/
#define R_CTL_FFTOSNUM		169
#define SYMBOL_NUMBER		376

/*	TESTSELECT	*/
#define R_TESTSELECT		170
#define TESTSELECT		377

/*	MSC_REV	*/
#define R_MSC_REV		171
#define REV_NUMBER		378

/*	PIR_CTL	*/
#define R_PIR_CTL		172
#define FREEZE		379

/*	SNR_CARRIER1	*/
#define R_SNR_CARRIER1		173
#define SNR_CARRIER_LO		380

/*	SNR_CARRIER2	*/
#define R_SNR_CARRIER2		174
#define MEAN		381
#define SNR_CARRIER_HI		382

/*	PPM_CPAMP	*/
#define R_PPM_CPAMP		175
#define PPM_CPC		383

/*	TSM_AP0	*/
#define R_TSM_AP0		176
#define ADDRESS_BYTE_0		384

/*	TSM_AP1	*/
#define R_TSM_AP1		177
#define ADDRESS_BYTE_1		385

/*	TSM_AP2	*/
#define R_TSM_AP2		178
#define DATA_BYTE_0		386

/*	TSM_AP3	*/
#define R_TSM_AP3		179
#define DATA_BYTE_1		387

/*	TSM_AP4	*/
#define R_TSM_AP4		180
#define DATA_BYTE_2		388

/*	TSM_AP5	*/
#define R_TSM_AP5		181
#define DATA_BYTE_3		389

/*	TSM_AP6	*/
#define R_TSM_AP6		182
#define TSM_AP6		390

/*	TSM_AP7	*/
#define R_TSM_AP7		183
#define MEM_SELECT_BYTE		391

/*	TSTRES	*/
#define R_TSTRES		184
#define FRES_DISPLAY		392
#define FRES_FIFO_AD		393
#define FRESRS		394
#define FRESACS		395
#define FRESFEC		396
#define FRES_PRIF		397
#define FRESCORE		398

/*	ANACTRL	*/
#define R_ANACTRL		185
#define BYPASS_XTAL		399
#define BYPASS_PLLXN		400
#define DIS_PAD_OSC		401
#define STDBY_PLLXN		402

/*	TSTBUS	*/
#define R_TSTBUS		186
#define FORCERATE1		403
#define TSTCKRS		404
#define TSTCKDIL		405
#define CFG_TST		406

/*	TSTRATE	*/
#define R_TSTRATE		187
#define FORCEPHA		407
#define FNEWPHA		408
#define FROT90		409
#define FR		410

/*	CONSTMODE	*/
#define R_CONSTMODE		188
#define TST_PRIF		411
#define CAR_TYPE		412
#define CONST_MODE		413

/*	CONSTCARR1	*/
#define R_CONSTCARR1		189
#define CONST_CARR_LO		414

/*	CONSTCARR2	*/
#define R_CONSTCARR2		190
#define CONST_CARR_HI		415

/*	ICONSTEL	*/
#define R_ICONSTEL		191
#define ICONSTEL		416

/*	QCONSTEL	*/
#define R_QCONSTEL		192
#define QCONSTEL		417

/*	TSTBISTRES0	*/
#define R_TSTBISTRES0		193
#define BEND_BDI		418
#define BBAD_BDI		419
#define BEND_PPM		420
#define BBAD_PPM		421
#define BEND_SDI		422
#define BBAD_SDI		423
#define BEND_INS		424
#define BBAD_INS		425

/*	TSTBISTRES1	*/
#define R_TSTBISTRES1		194
#define BEND_CHC2B		426
#define BBAD_CHC2B		427
#define BEND_CHC3		428
#define BBAD_CHC3		429
#define BEND_FFTI		430
#define BBAD_FFTI		431
#define BEND_FFTW		432
#define BBAD_FFTW		433

/*	TSTBISTRES2	*/
#define R_TSTBISTRES2		195
#define BEND_RS		434
#define BBAD_RS		435
#define BEND_SYR		436
#define BBAD_SYR		437
#define BEND_CHC1		438
#define BBAD_CHC1		439
#define BEND_CHC2		440
#define BBAD_CHC2		441

/*	TSTBISTRES3	*/
#define R_TSTBISTRES3		196
#define BEND_FIFO		442
#define BBAD_FIFO		443
#define BEND_VIT2		444
#define BBAD_VIT2		445
#define BEND_VIT1		446
#define BBAD_VIT1		447
#define BEND_DIL		448
#define BBAD_DIL		449

/*	RF_AGC1	*/
#define R_RF_AGC1		197
#define RF_AGC1_LEVEL_HI		450

/*	RF_AGC2	*/
#define R_RF_AGC2		198
#define REF_ADGP		451
#define STDBY_ADCGP		452
#define CHANNEL_SEL		453
#define RF_AGC1_LEVEL_LO		454

/*	ANADIGCTRL	*/
#define R_ANADIGCTRL		199
#define SEL_CLKDEM		455
#define ADC_RIS_EGDE		456
#define SGN_ADC		457
#define SEL_AD12_SYNC		458

/*	PLLMDIV	*/
#define R_PLLMDIV		200
#define PLL_MDIV		459

/*	PLLSETUP	*/
#define R_PLLSETUP		201
#define PLL_PDIV		460

/*	DUAL_AD12	*/
#define R_DUAL_AD12		202
#define FS20M		461
#define FS50M		462
#define INMODE		463
#define POFFQ		464
#define POFFI		465
#define POFFREF		466

/*	TSTBIST	*/
#define R_TSTBIST		203
#define TST_GCLKENA		467
#define TST_MEMBIST		468

/*	PAD_COMP_CTRL	*/
#define R_PAD_COMP_CTRL		204
#define COMPTQ		469
#define COMPEN		470
#define FREEZE2		471
#define SLEEP_INHBT		472
#define CHIP_SLEEP		473

/*	PAD_COMP_WR	*/
#define R_PAD_COMP_WR		205
#define WR_ASRC		474

/*	PAD_COMP_RD	*/
#define R_PAD_COMP_RD		206
#define COMPOK		475
#define RD_ASRC		476

/*	GHOSTREG	*/
#define R_GHOSTREG		207
#define GHOSTFIELD		477




#define		STV362_NBREGS 208
#define 	STV362_NBFIELDS 478




	

	/* Number of registers  */
	
	
	#ifdef __cplusplus
	 extern "C"
	 {
	#endif                  /* __cplusplus */

	/* structures -------------------------------------------------------------- */

	    typedef struct
	    {
	        STCHIP_Info_t *Chip;        /* pointer to parameters to pass to the CHIP API */
	        U32            NbDefVal;    /* number of default values (must match number of 362 registers) */
	        U8            *DefVal;      /* pointer to table of default values */
	    } 
	    STV0362_InitParams_t;   


	/* functions --------------------------------------------------------------- */

	/* create instance of 362 register mappings */
	STCHIP_Handle_t STV0362_Init(STV0362_InitParams_t *InitParams);     


	#ifdef __cplusplus
	 }
	#endif                  /* __cplusplus */
	
#endif