362_init.h

STV0299 Minituner driver, for ST chipset

#ifndef H_362_INIT
	#define H_362_INIT

	#include "chip.h"
/**************************/	
//Registers and Fields d閒initions

/*	PLLNDIV	*/
#define R_PLLNDIV		0
#define PLL_NDIV		0

/*	ID	*/
#define R_ID		1
#define IDENTIFICATIONREGISTER		1

/*	I2CRPT	*/
#define R_I2CRPT		2
#define I2CT_ON		2
#define ENARPT_LEVEL		3
#define SCLT_DELAY		4
#define SCLT_NOD		5
#define STOP_ENABLE		6
#define SDAT_NOD		7

/*	TOPCTRL	*/
#define R_TOPCTRL		3
#define STDBY		8
#define STDBY_FEC		9
#define STDBY_CORE		10
#define DIR_CLK_54		11
#define TS_DIS		12
#define DIR_CLK_108		13
#define TUNER_BB		14
#define DVBT_H		15

/*	IOCFG0	*/
#define R_IOCFG0		4
#define OP0_SD		16
#define OP0_VAL		17
#define OP0_OD		18
#define OP0_INV		19
#define OP0_DACVALUE_HI		20

/*	DAC0R	*/
#define R_DAC0R		5
#define OP0_DACVALUE_LO		21

/*	IOCFG1	*/
#define R_IOCFG1		6
#define IP0		22
#define OP1_OD		23
#define OP1_INV		24
#define OP1_DACVALUE_HI		25

/*	DAC1R	*/
#define R_DAC1R		7
#define OP1_DACVALUE_LO		26

/*	IOCFG2	*/
#define R_IOCFG2		8
#define OP2_LOCK_CONF		27
#define OP2_OD		28
#define OP2_VAL		29
#define OP1_LOCK_CONF		30

/*	SDFR	*/
#define R_SDFR		9
#define OP0_FREQ		31
#define OP1_FREQ		32

/*	STATUS	*/
#define R_STATUS		10
#define TPS_LOCK		33
#define SYR_LOCK		34
#define AGC_LOCK		35
#define PRF		36
#define LK		37
#define PR		38

/*	AUX_CLK	*/
#define R_AUX_CLK		11
#define AUXFEC_CTL		39
#define DIS_CKX4		40
#define CKSEL		41
#define CKDIV_PROG		42
#define AUXCLK_ENA		43

/*	FREESYS1	*/
#define R_FREESYS1		12
#define FREESYS1		44

/*	FREESYS2	*/
#define R_FREESYS2		13
#define FREESYS2		45

/*	FREESYS3	*/
#define R_FREESYS3		14
#define FREESYS3		46

/*	AGC2MAX	*/
#define R_AGC2MAX		15
#define AGC2MAX		47

/*	AGC2MIN	*/
#define R_AGC2MIN		16
#define AGC2MIN		48

/*	AGC1MAX	*/
#define R_AGC1MAX		17
#define AGC1MAX		49

/*	AGC1MIN	*/
#define R_AGC1MIN		18
#define AGC1MIN		50

/*	AGCR	*/
#define R_AGCR		19
#define RATIO_A		51
#define RATIO_B		52
#define RATIO_C		53

/*	AGC2TH	*/
#define R_AGC2TH		20
#define AGC2_THRES		54

/*	AGC12C	*/
#define R_AGC12C		21
#define AGC1_IV		55
#define AGC1_OD		56
#define AGC1_LOAD		57
#define AGC2_IV		58
#define AGC2_OD		59
#define AGC2_LOAD		60
#define AGC12_MODE		61

/*	AGCCTRL1	*/
#define R_AGCCTRL1		22
#define DAGC_ON		62
#define INVERT_AGC12		63
#define AGC1_MODE		64
#define AGC2_MODE		65

/*	AGCCTRL2	*/
#define R_AGCCTRL2		23
#define FRZ2_CTRL		66
#define FRZ1_CTRL		67
#define TIME_CST		68

/*	AGC1VAL1	*/
#define R_AGC1VAL1		24
#define AGC1_VAL_LO		69

/*	AGC1VAL2	*/
#define R_AGC1VAL2		25
#define AGC1_VAL_HI		70

/*	AGC2VAL1	*/
#define R_AGC2VAL1		26
#define AGC2_VAL_LO		71

/*	AGC2VAL2	*/
#define R_AGC2VAL2		27
#define AGC2_VAL_HI		72

/*	AGC2PGA	*/
#define R_AGC2PGA		28
#define AGC2PGA		73

/*	OVF_RATE1	*/
#define R_OVF_RATE1		29
#define OVF_RATE_HI		74

/*	OVF_RATE2	*/
#define R_OVF_RATE2		30
#define OVF_RATE_LO		75

/*	GAIN_SRC1	*/
#define R_GAIN_SRC1		31
#define INV_SPECTR		76
#define IQ_INVERT		77
#define INR_BYPASS		78
#define INS_BYPASS		79
#define GAIN_SRC_HI		80

/*	GAIN_SRC2	*/
#define R_GAIN_SRC2		32
#define GAIN_SRC_LO		81

/*	INC_DEROT1	*/
#define R_INC_DEROT1		33
#define INC_DEROT_HI		82

/*	INC_DEROT2	*/
#define R_INC_DEROT2		34
#define INC_DEROT_LO		83

/*	PPM_CPAMP_DIR	*/
#define R_PPM_CPAMP_DIR		35
#define PPM_CPAMP_DIRECT		84

/*	PPM_CPAMP_INV	*/
#define R_PPM_CPAMP_INV		36
#define PPM_CPAMP_INV		85

/*	FREESTFE_1	*/
#define R_FREESTFE_1		37
#define SYMBOL_NUMBER_INC		86
#define SEL_LSB		87
#define AVERAGE_ON		88
#define DC_ADJ		89

/*	FREESTFE_2	*/
#define R_FREESTFE_2		38
#define SEL_SRCOUT		90
#define SEL_SYRTHR		91

/*	DCOFFSET	*/
#define R_DCOFFSET		39
#define SELECT_I_Q		92
#define DC_OFFSET		93

/*	EN_PROCESS	*/
#define R_EN_PROCESS		40
#define INS_NIN_INDEX		94
#define ENAB_MANUAL		95

/*	SDI_SMOOTHER	*/
#define R_SDI_SMOOTHER		41
#define DIS_SMOOTH		96
#define SDI_INC_SMOOTHER		97

/*	FE_LOOP_OPEN	*/
#define R_FE_LOOP_OPEN		42
#define TRL_LOOP_OP		98
#define CRL_LOOP_OP		99

/*	FREQOFF1	*/
#define R_FREQOFF1		43
#define FREQ_OFFSET_LOOP_OPEN_VHI		100

/*	FREQOFF2	*/
#define R_FREQOFF2		44
#define FREQ_OFFSET_LOOP_OPEN_HI		101

/*	FREQOFF3	*/
#define R_FREQOFF3		45
#define FREQ_OFFSET_LOOP_OPEN_LO		102

/*	TIMOFF1	*/
#define R_TIMOFF1		46
#define TIM_OFFSET_LOOP_OPEN_HI		103

/*	TIMOFF2	*/
#define R_TIMOFF2		47
#define TIM_OFFSET_LOOP_OPEN_LO		104

/*	EPQ	*/
#define R_EPQ		48
#define EPQ		105

/*	EPQAUTO	*/
#define R_EPQAUTO		49
#define EPQ2		106

/*	CHP_TAPS	*/
#define R_CHP_TAPS		50
#define SCAT_FILT_EN		107
#define TAPS_EN		108

/*	CHP_DYN_COEFF	*/
#define R_CHP_DYN_COEFF		51
#define CHP_DYNAM_COEFFCIENT		109

/*	PPM_STATE_MAC	*/
#define R_PPM_STATE_MAC		52
#define PPM_STATE_MACHINE_DECODER		110

/*	INR_THRESHOLD	*/
#define R_INR_THRESHOLD		53
#define INR_THRESHOLD		111

/*	EPQ_TPS_ID_CELL	*/
#define R_EPQ_TPS_ID_CELL		54
#define DIS_TPS_RSVD		112
#define DIS_BCH		113
#define DIS_ID_CEL		114
#define HOLD_SLOPE		115
#define TPS_ADJUST_SYM		116

/*	EPQ_CFG	*/
#define R_EPQ_CFG		55
#define EPQ_RANGE		117
#define EPQ_SOFT		118

/*	EPQ_STATUS	*/
#define R_EPQ_STATUS		56
#define SLOPE_INC		119
#define TPS_FIELD		120

/*	FECM	*/
#define R_FECM		57
#define FEC_MODE		121
#define VIT_DIFF		122
#define SYNC		123
#define SYM		124

/*	VTH0	*/
#define R_VTH0		58
#define VTH0		125

/*	VTH1	*/
#define R_VTH1		59
#define VTH1		126

/*	VTH2	*/
#define R_VTH2		60
#define VTH2		127

/*	VTH3	*/
#define R_VTH3		61
#define VTH3		128

/*	VTH4	*/
#define R_VTH4		62
#define VTH4		129

/*	VTH5	*/
#define R_VTH5		63
#define VTH5		130

/*	FREEVIT	*/
#define R_FREEVIT		64
#define FREEVIT		131

/*	VITPROG	*/
#define R_VITPROG		65
#define FORCE_ROTA		132
#define AUTO_FREEZE		133
#define MDIVIDER		134

/*	PR	*/
#define R_PR		66
#define FRAPTCR		135
#define E7_8		136
#define E6_7		137
#define E5_6		138
#define E3_4		139
#define E2_3		140
#define E1_2		141

/*	VSEARCH	*/
#define R_VSEARCH		67
#define PR_AUTO		142
#define PR_FREEZE		143
#define SAMPNUM		144
#define TIMEOUT		145
#define HYSTER		146

/*	RS	*/
#define R_RS		68
#define DEINT_ENA		147
#define OUTRS_SP		148
#define RS_ENA		149
#define DESCR_ENA		150
#define ERRBIT_ENA		151
#define FORCE47		152
#define CLK_POL		153
#define CLK_CFG		154

/*	RSOUT	*/
#define R_RSOUT		69
#define ENA_STBACKEND		155
#define ENA8_LEVEL		156

/*	ERRCTRL1	*/
#define R_ERRCTRL1		70
#define ERRMODE1		157
#define TESTERS1		158
#define ERR_SOURCE1		159
#define RESET_CNTR1		160
#define NUM_EVENT1		161

/*	ERRCNTM1	*/
#define R_ERRCNTM1		71
#define ERROR_COUNT1_HI		162

/*	ERRCNTL1	*/
#define R_ERRCNTL1		72
#define ERROR_COUNT1_LO		163

/*	ERRCTRL2	*/
#define R_ERRCTRL2		73
#define ERRMODE2		164
#define TESTERS2		165
#define ERR_SOURCE2		166
#define RESET_CNTR2		167
#define NUM_EVENT2		168

/*	ERRCNTM2	*/
#define R_ERRCNTM2		74
#define ERROR_COUNT2_HI		169

/*	ERRCNTL2	*/
#define R_ERRCNTL2		75
#define ERROR_COUNT2_LO		170

/*	FREEDRS	*/
#define R_FREEDRS		76
#define FREEDRS		171

/*	VERROR	*/
#define R_VERROR		77
#define ERROR_VALUE		172

/*	ERRCTRL3	*/
#define R_ERRCTRL3		78
#define ERRMODE3		173
#define TESTERS3		174
#define ERR_SOURCE3		175
#define RESET_CNTR3		176
#define NUM_EVENT3		177

/*	ERRCNTM3	*/
#define R_ERRCNTM3		79
#define ERROR_COUNT3_HI		178

/*	ERRCNTL3	*/
#define R_ERRCNTL3		80
#define ERROR_COUNT3_LO		179

/*	DILSTK1	*/
#define R_DILSTK1		81
#define DILSTK_HI		180

/*	DILSTK0	*/
#define R_DILSTK0		82
#define DILSTK_LO		181

/*	DILBWSTK1	*/
#define R_DILBWSTK1		83
#define DILBWSTK1		182

/*	DILBWST0	*/
#define R_DILBWST0		84
#define DILBWST0		183

/*	LNBRX	*/
#define R_LNBRX		85
#define LINE_OK		184
#define OCCURRED_ERR		185
#define RSOV_DATAIN		186
#define LNBTX_CHIPADDR		187

/*	RSTC	*/
#define R_RSTC		86
#define DEINTTC		188
#define DIL64_ON		189
#define RSTC		190
#define DESCRAMTC		191
#define MODSYNCBYT		192
#define LOWP_DIS		193
#define HIGHP_DIS		194

/*	VIT_BIST	*/
#define R_VIT_BIST		87
#define RAND_RAMP		195
#define NOISE_LEVEL		196
#define PR_VIT_BIST		197

/*	IIR_CELL_NB	*/
#define R_IIR_CELL_NB		88
#define NRST_IIR		198
#define IIR_CELL_NB		199

/*	IIR_CX_COEFF1_MSB	*/
#define R_IIR_CX_COEFF1_MSB		89
#define IIR_CX_COEFF1_MSB		200

/*	IIR_CX_COEFF1_LSB	*/
#define R_IIR_CX_COEFF1_LSB		90
#define IIR_CX_COEFF1_LSB		201

/*	IIR_CX_COEFF2_MSB	*/
#define R_IIR_CX_COEFF2_MSB		91
#define IIR_CX_COEFF2_MSB		202

/*	IIR_CX_COEFF2_LSB	*/
#define R_IIR_CX_COEFF2_LSB		92
#define IIR_CX_COEFF2_LSB		203

/*	IIR_CX_COEFF3_MSB	*/
#define R_IIR_CX_COEFF3_MSB		93
#define IIR_CX_COEFF3_MSB		204

/*	IIR_CX_COEFF3_LSB	*/
#define R_IIR_CX_COEFF3_LSB		94
#define IIR_CX_COEFF3_LSB		205

/*	IIR_CX_COEFF4_MSB	*/
#define R_IIR_CX_COEFF4_MSB		95
#define IIR_CX_COEFF4_MSB		206

/*	IIR_CX_COEFF4_LSB	*/
#define R_IIR_CX_COEFF4_LSB		96
#define IIR_CX_COEFF4_LSB		207

/*	IIR_CX_COEFF5_MSB	*/
#define R_IIR_CX_COEFF5_MSB		97
#define IIR_CX_COEFF5_MSB		208

/*	IIR_CX_COEFF5_LSB	*/
#define R_IIR_CX_COEFF5_LSB		98
#define IIR_CX_COEFF5_LSB		209

/*	FEPATH_CFG	*/
#define R_FEPATH_CFG		99
#define DEMUX_SWAP		210
#define DIGAGC_SWAP		211
#define LONGPATH_IF		212

/*	PMC1_FUNC	*/
#define R_PMC1_FUNC		100
#define SOFT_RSTN		213
#define PMC1_AVERAGE_TIME		214
#define PMC1_WAIT_TIME		215
#define PMC1_2N_SEL		216

/*	PMC1_FORCE	*/
#define R_PMC1_FORCE		101
#define PMC1_FORCE		217
#define PMC1_FORCE_VALUE		218

/*	PMC2_FUNC	*/
#define R_PMC2_FUNC		102
#define PMC2_SOFT_STN		219
#define PMC2_ACCU_TIME		220
#define PMC2_CMDP_MN		221
#define PMC2_SWAP		222

/*	DIG_AGC_R	*/
#define R_DIG_AGC_R		103
#define COM_SOFT_RSTN		223
#define COM_AGC_ON		224
#define COM_EARLY		225
#define AUT_SOFT_RESETN		226
#define AUT_AGC_ON		227
#define AUT_EARLY		228
#define AUT_ROT_EN		229
#define LOCK_SOFT_RESETN		230

/*	COMAGC_TARMSB	*/
#define R_COMAGC_TARMSB		104
#define COM_AGC_TARGET_MSB		231

/*	COM_AGC_TAR_ENMODE	*/
#define R_COM_AGC_TAR_ENMODE		105
#define COM_AGC_TARGET_LSB		232
#define COM_ENMODE		233

/*	COM_AGC_CFG	*/
#define R_COM_AGC_CFG		106
#define COM_N		234
#define COM_STABMODE		235
#define ERR_SEL		236

/*	COM_AGC_GAIN1	*/
#define R_COM_AGC_GAIN1		107
#define COM_GAIN1ACK		237
#define COM_GAIN1TRK		238

/*	AUT_AGC_TARGET_MSB	*/
#define R_AUT_AGC_TARGET_MSB		108
#define AUT_AGC_TARGET_MSB		239

/*	LOCK_DETECT_MSB	*/
#define R_LOCK_DETECT_MSB		109