tmbslhdmitx.h

HDMI NXP9983 chipset controller driver

/** size descriptor block of monitor descriptor */
#define EDID_MONITOR_DESCRIPTOR_SIZE   13

#define NUMBER_DTD_STORED       10



/*============================================================================*/
/*                       ENUM OR TYPE DEFINITIONS                             */
/*============================================================================*/


/*============================================================================*/
/**
 * basic display parameters structure
 */
typedef struct _tmbslHdmiTxEdidBDParam_t
{
    UInt8   uVideoInputDef;      /**< Video Input Definition                       */
    UInt8   uMaxHorizontalSize;  /**< Max. Horizontal Image Size in cm             */
    UInt8   uMaxVerticalSize;    /**< Max. Vertical Image Size in cm               */
    UInt8   uGamma;              /**< Gamma                                        */
    UInt8   uFeatureSupport;     /**< Feature support                              */
} tmbslHdmiTxEdidBDParam_t;


/*============================================================================*/
/**
 * First monitor descriptor structure
 */
typedef struct _tmbslHdmiTxEdidFirstMD_t
{   
    Bool    bDescRecord;                                    /**< True when parameters of struct are available   */
    UInt8   uMonitorName[EDID_MONITOR_DESCRIPTOR_SIZE];     /**< Monitor Name                                   */
} tmbslHdmiTxEdidFirstMD_t;

/*============================================================================*/
/**
 * Second monitor descriptor structure
 */
typedef struct _tmbslHdmiTxEdidSecondMD_t
{
    Bool    bDescRecord;                                    /**< True when parameters of struct are available   */
    UInt8   uMinVerticalRate;                               /**< Min vertical rate in Hz                        */
    UInt8   uMaxVerticalRate;                               /**< Max vertical rate in Hz                        */
    UInt8   uMinHorizontalRate;                             /**< Min horizontal rate in Hz                      */
    UInt8   uMaxHorizontalRate;                             /**< Max horizontal rate in Hz                      */
    UInt8   uMaxSupportedPixelClk;                          /**< Max suuported pixel clock rate in MHz          */
} tmbslHdmiTxEdidSecondMD_t;


/*============================================================================*/
/**
 * Other monitor descriptor structure
 */
typedef struct _tmbslHdmiTxEdidOtherMD_t
{
    Bool    bDescRecord;                                    /**< True when parameters of struct are available   */
    UInt8   uOtherDescriptor[EDID_MONITOR_DESCRIPTOR_SIZE]; /**< Other monitor Descriptor                       */
} tmbslHdmiTxEdidOtherMD_t;














/**
 * \brief System function pointer type, to call user I2C read/write functions
 * \param slaveAddr     The I2C slave address
 * \param firstRegister The first device register address to read or write 
 * \param lenData       Length of data to read or write (i.e. no. of registers)
 * \param pData         Pointer to data to write, or to buffer to receive data
 * \return              The call result:
 *                      - TM_OK: the call was successful
 *                      - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing
 *                      - TMBSL_ERR_HDMI_I2C_READ:  failed when reading
 */
typedef struct _tmbslHdmiTxSysArgs_t
{
    UInt8 slaveAddr;
    UInt8 firstRegister;
    UInt8 lenData;
    UInt8 *pData;
} tmbslHdmiTxSysArgs_t;
typedef tmErrorCode_t (FUNC_PTR * ptmbslHdmiTxSysFunc_t)
                                 (tmbslHdmiTxSysArgs_t *pSysArgs);

/**
 * \brief System function pointer type, to call user I2C EDID read function
 * \param segPtrAddr    The EDID segment pointer address 0 to 7Fh
 * \param segPtr        The EDID segment pointer 0 to 7Fh
 * \param dataRegAddr   The EDID data register address 0 to 7Fh
 * \param wordOffset    The first word offset 0 to FFh to read
 * \param lenData       Length of data to read (i.e. number of registers),
                        1 to max starting at wordOffset
 * \param pData         Pointer to buffer to receive lenData data bytes
 * \return              The call result:
 *                      - TM_OK: the call was successful
 *                      - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing
 *                      - TMBSL_ERR_HDMI_I2C_READ:  failed when reading
 */
typedef struct _tmbslHdmiTxSysArgsEdid_t
{
    UInt8 segPtrAddr;
    UInt8 segPtr;
    UInt8 dataRegAddr;
    UInt8 wordOffset;
    UInt8 lenData;
    UInt8 *pData;
} tmbslHdmiTxSysArgsEdid_t;
typedef tmErrorCode_t (FUNC_PTR * ptmbslHdmiTxSysFuncEdid_t)
                                 (tmbslHdmiTxSysArgsEdid_t *pSysArgs);

/*============================================================================*/
/*
 * Timer function pointer type, to call an application timer
 * Parameter ms: Delay in milliseconds required
 */
typedef Void (FUNC_PTR * ptmbslHdmiTxSysFuncTimer_t) (UInt16 ms);

/*============================================================================*/
/*
 * Callback function pointer type, to call a user interrupt handler
 * Parameter txUnit: The transmitter unit that interrupted, 0 to max
 */
typedef Void (FUNC_PTR * ptmbslHdmiTxCallback_t) (tmUnitSelect_t txUnit);

/*============================================================================*/
/**
 * EIA/CEA-861B video format type
 */
typedef enum
{
    HDMITX_VFMT_NULL               = 0,     /**< Not a valid format...        */
    HDMITX_VFMT_NO_CHANGE          = 0,     /**< ...or no change required     */
    HDMITX_VFMT_MIN                = 1,     /**< Lowest valid format          */
    HDMITX_VFMT_TV_MIN             = 1,     /**< Lowest valid TV format       */
    HDMITX_VFMT_01_640x480p_60Hz   = 1,     /**< Format 01 640  x 480p  60Hz  */
    HDMITX_VFMT_02_720x480p_60Hz   = 2,     /**< Format 02 720  x 480p  60Hz  */
    HDMITX_VFMT_03_720x480p_60Hz   = 3,     /**< Format 03 720  x 480p  60Hz  */
    HDMITX_VFMT_04_1280x720p_60Hz  = 4,     /**< Format 04 1280 x 720p  60Hz  */
    HDMITX_VFMT_05_1920x1080i_60Hz = 5,     /**< Format 05 1920 x 1080i 60Hz  */
    HDMITX_VFMT_06_720x480i_60Hz   = 6,     /**< Format 06 720  x 480i  60Hz  */
    HDMITX_VFMT_07_720x480i_60Hz   = 7,     /**< Format 07 720  x 480i  60Hz  */
    HDMITX_VFMT_08_720x240p_60Hz   = 8,     /**< Format 08 720  x 240p  60Hz  */
    HDMITX_VFMT_09_720x240p_60Hz   = 9,     /**< Format 09 720  x 240p  60Hz  */
    HDMITX_VFMT_10_720x480i_60Hz   = 10,    /**< Format 10 720  x 480i  60Hz  */
    HDMITX_VFMT_11_720x480i_60Hz   = 11,    /**< Format 11 720  x 480i  60Hz  */
    HDMITX_VFMT_12_720x240p_60Hz   = 12,    /**< Format 12 720  x 240p  60Hz  */
    HDMITX_VFMT_13_720x240p_60Hz   = 13,    /**< Format 13 720  x 240p  60Hz  */
    HDMITX_VFMT_14_1440x480p_60Hz  = 14,    /**< Format 14 1440 x 480p  60Hz  */
    HDMITX_VFMT_15_1440x480p_60Hz  = 15,    /**< Format 15 1440 x 480p  60Hz  */
    HDMITX_VFMT_16_1920x1080p_60Hz = 16,    /**< Format 16 1920 x 1080p 60Hz  */
    HDMITX_VFMT_17_720x576p_50Hz   = 17,    /**< Format 17 720  x 576p  50Hz  */
    HDMITX_VFMT_18_720x576p_50Hz   = 18,    /**< Format 18 720  x 576p  50Hz  */
    HDMITX_VFMT_19_1280x720p_50Hz  = 19,    /**< Format 19 1280 x 720p  50Hz  */
    HDMITX_VFMT_20_1920x1080i_50Hz = 20,    /**< Format 20 1920 x 1080i 50Hz  */
    HDMITX_VFMT_21_720x576i_50Hz   = 21,    /**< Format 21 720  x 576i  50Hz  */
    HDMITX_VFMT_22_720x576i_50Hz   = 22,    /**< Format 22 720  x 576i  50Hz  */
    HDMITX_VFMT_23_720x288p_50Hz   = 23,    /**< Format 23 720  x 288p  50Hz  */
    HDMITX_VFMT_24_720x288p_50Hz   = 24,    /**< Format 24 720  x 288p  50Hz  */
    HDMITX_VFMT_25_720x576i_50Hz   = 25,    /**< Format 25 720  x 576i  50Hz  */
    HDMITX_VFMT_26_720x576i_50Hz   = 26,    /**< Format 26 720  x 576i  50Hz  */
    HDMITX_VFMT_27_720x288p_50Hz   = 27,    /**< Format 27 720  x 288p  50Hz  */
    HDMITX_VFMT_28_720x288p_50Hz   = 28,    /**< Format 28 720  x 288p  50Hz  */
    HDMITX_VFMT_29_1440x576p_50Hz  = 29,    /**< Format 29 1440 x 576p  50Hz  */
    HDMITX_VFMT_30_1440x576p_50Hz  = 30,    /**< Format 30 1440 x 576p  50Hz  */
    HDMITX_VFMT_31_1920x1080p_50Hz = 31,    /**< Format 31 1920 x 1080p 50Hz  */
	HDMITX_VFMT_32_1920x1080p_24Hz = 32,    /**< Format 32 1920 x 1080p 24Hz  */
	HDMITX_VFMT_33_1920x1080p_25Hz = 33,    /**< Format 33 1920 x 1080p 25Hz  */
	HDMITX_VFMT_34_1920x1080p_30Hz = 34,    /**< Format 34 1920 x 1080p 30Hz  */
    HDMITX_VFMT_TV_MAX             = 34,    /**< Highest valid TV format      */
	HDMITX_VFMT_TV_NO_REG_MIN	   = 32,	/**< Lowest TV format without prefetched table */
    HDMITX_VFMT_TV_NUM             = 35,    /**< Number of TV formats & null  */
    HDMITX_VFMT_PC_MIN             = 128,   /**< Lowest valid PC format       */
    HDMITX_VFMT_PC_640x480p_60Hz   = 128,   /**< PC format 128                */
    HDMITX_VFMT_PC_800x600p_60Hz   = 129,   /**< PC format 129                */
    HDMITX_VFMT_PC_1152x960p_60Hz  = 130,   /**< PC format 130                */
    HDMITX_VFMT_PC_1024x768p_60Hz  = 131,   /**< PC format 131                */
    HDMITX_VFMT_PC_1280x768p_60Hz  = 132,   /**< PC format 132                */
    HDMITX_VFMT_PC_1280x1024p_60Hz = 133,   /**< PC format 133                */
    HDMITX_VFMT_PC_1360x768p_60Hz  = 134,   /**< PC format 134                */
    HDMITX_VFMT_PC_1400x1050p_60Hz  = 135,  /**< PC format 135                */
    HDMITX_VFMT_PC_1600x1200p_60Hz = 136,   /**< PC format 136                */
    HDMITX_VFMT_PC_1024x768p_70Hz  = 137,   /**< PC format 137                */
    HDMITX_VFMT_PC_640x480p_72Hz   = 138,   /**< PC format 138                */
    HDMITX_VFMT_PC_800x600p_72Hz   = 139,   /**< PC format 139                */
    HDMITX_VFMT_PC_640x480p_75Hz   = 140,   /**< PC format 140                */
    HDMITX_VFMT_PC_1024x768p_75Hz  = 141,   /**< PC format 141                */
    HDMITX_VFMT_PC_800x600p_75Hz   = 142,   /**< PC format 142                */
    HDMITX_VFMT_PC_1024x864p_75Hz  = 143,   /**< PC format 143                */
    HDMITX_VFMT_PC_1280x1024p_75Hz = 144,   /**< PC format 144                */
    HDMITX_VFMT_PC_640x350p_85Hz   = 145,   /**< PC format 145                */
    HDMITX_VFMT_PC_640x400p_85Hz   = 146,   /**< PC format 146                */
    HDMITX_VFMT_PC_720x400p_85Hz   = 147,   /**< PC format 147                */
    HDMITX_VFMT_PC_640x480p_85Hz   = 148,   /**< PC format 148                */
    HDMITX_VFMT_PC_800x600p_85Hz   = 149,   /**< PC format 149                */
    HDMITX_VFMT_PC_1024x768p_85Hz  = 150,   /**< PC format 150                */
    HDMITX_VFMT_PC_1152x864p_85Hz  = 151,   /**< PC format 151                */
    HDMITX_VFMT_PC_1280x960p_85Hz  = 152,   /**< PC format 152                */
    HDMITX_VFMT_PC_1280x1024p_85Hz = 153,   /**< PC format 153                */
    HDMITX_VFMT_PC_1024x768i_87Hz  = 154,   /**< PC format 154                */
    HDMITX_VFMT_PC_MAX             = 154,   /**< Highest valid PC format      */
    HDMITX_VFMT_PC_NUM     = (1+154-128)    /**< Number of PC formats         */
} tmbslHdmiTxVidFmt_t;

/*============================================================================*/
/*                       EXTERN DATA DEFINITIONS                              */
/*============================================================================*/

typedef enum
{
     BSLHDMITX_UNKNOWN = 0x00, /**< IC/IP is not recognized */
     BSLHDMITX_TDA9984,        /**< IC is a TDA9984         */
     BSLHDMITX_TDA9989,        /**< IC is a TDA9989         */
     BSLHDMITX_LIPP4200,       /**< IP is a LIPP4200        */
     BSLHDMITX_TDA9981,        /**< IC is a TDA9981         */
     BSLHDMITX_TDA9983         /**< IC is a TDA9983         */
} tmbslHdmiTxVersion_t;


/*============================================================================*/
/*                       EXTERN FUNCTION PROTOTYPES                           */
/*============================================================================*/

/*============================================================================*/
/**
    \brief      Reset the Clock Time Stamp generator in HDMI mode only

    \param[in]  txUnit      Transmitter unit number

    \return     The call result:
                - TM_OK: the call was successful
                - Else a problem has been detected:
                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing the I2C bus
                  - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: in DVI mode
 */
tmErrorCode_t
tmbslHdmiTxAudioInResetCts
(
    tmUnitSelect_t      txUnit
);


/*============================================================================*/
/**
 * tmbslHdmiTxAudioInSetConfig() parameter types
 */
/** Audio input formats */
typedef enum
{
    HDMITX_AFMT_SPDIF      = 0,         /**< SPDIF */
    HDMITX_AFMT_I2S        = 1,         /**< I2S   */
    HDMITX_AFMT_OBA        = 2,         /**< One bit audio */
    HDMITX_AFMT_DSD        = 3,         /**< DSD           */
    HDMITX_AFMT_INVALID    = 4          /**< Invalid format*/
} tmbslHdmiTxaFmt_t;

/** DSD clock polarities */
typedef enum
{
    HDMITX_CLKPOLDSD_ACLK       = 0,    /**< Same as ACLK */
    HDMITX_CLKPOLDSD_NACLK      = 1,    /**< Not ACLK, i.e. inverted */
    HDMITX_CLKPOLDSD_NO_CHANGE  = 2,    /**< No change    */
    HDMITX_CLKPOLDSD_INVALID    = 3     /**< Invalid      */
} tmbslHdmiTxClkPolDsd_t;

/** DSD data swap values */
typedef enum
{
    HDMITX_SWAPDSD_OFF          = 0,    /**< No swap   */
    HDMITX_SWAPDSD_ON           = 1,    /**< Swap      */
    HDMITX_SWAPDSD_NO_CHANGE    = 2,    /**< No change */
    HDMITX_SWAPDSD_INVALID      = 3     /**< Invalid   */
} tmbslHdmiTxSwapDsd_t;

/** I2S and DSD channel allocation values */
enum _tmbslHdmiTxChan
{
    HDMITX_CHAN_MIN        = 0,
    HDMITX_CHAN_MAX        = 31,
    HDMITX_CHAN_NO_CHANGE  = 32,
    HDMITX_CHAN_INVALID    = 33
};

/** Audio layout values */
enum _tmbslHdmiTxLayout
{
    HDMITX_LAYOUT_MIN       = 0,
    HDMITX_LAYOUT_MAX       = 1,
    HDMITX_LAYOUT_NO_CHANGE = 2,
    HDMITX_LAYOUT_INVALID   = 3
};

/** Audio FIFO read latency values */
enum _tmbslHdmiTxlatency_rd
{
    HDMITX_LATENCY_MIN         = 0x000,
    HDMITX_LATENCY_MAX         = 0x0FF,
    HDMITX_LATENCY_NO_CHANGE   = 0x100,
    HDMITX_LATENCY_INVALID     = 0x101