tmbslhdmitx_local.h

HDMI NXP9983 chipset controller driver

{
    EV_DEINIT               = 0,
    EV_UNPLUGGED            = 1,
    EV_PLUGGEDIN            = 2,
    EV_STANDBY              = 3,
    EV_RESUME_UNPLUGGED     = 4,
    EV_RESUME_PLUGGEDIN     = 5,
    EV_GETBLOCKDATA         = 6,
    EV_SETINOUT             = 7,
    EV_OUTDISABLE           = 8,
    EV_HDCP_RUN             = 9,
    EV_HDCP_BKSV_NREPEAT    = 10,
    EV_HDCP_BKSV_NSECURE    = 11,
    EV_HDCP_BKSV_REPEAT     = 12,
    EV_HDCP_BSTATUS_GOOD    = 13,
    EV_HDCP_KSV_SECURE      = 14,
    EV_HDCP_T0              = 15,
    EV_HDCP_STOP            = 16,
#if defined (TMFL_TDA9981_SUPPORT) && defined(TMFL_RX_SENSE_ON)
    EV_SINKON               = 17,
    EV_SINKOFF              = 18,
    EV_INVALID              = 19
#else /* TMFL_TDA9981_SUPPORT && TMFL_RX_SENSE_ON */
    EV_INVALID              = 17
#endif /* TMFL_TDA9981_SUPPORT && TMFL_RX_SENSE_ON */
} tmbslHdmiTxEvent_t;

typedef enum _tmbslHdmiTxState
{
    ST_UNINITIALIZED        = 0,
    ST_DISCONNECTED         = 1,
    ST_AWAIT_EDID           = 2,
    ST_SINK_CONNECTED       = 3,
    ST_VIDEO_NO_HDCP        = 4,
    ST_STANDBY              = 5,
    ST_HDCP_WAIT_RX         = 6,
    ST_HDCP_WAIT_BSTATUS    = 7,
    ST_HDCP_WAIT_SHA_1      = 8,
    ST_HDCP_AUTHENTICATED   = 9,
#if defined (TMFL_TDA9981_SUPPORT) && defined(TMFL_RX_SENSE_ON)
    ST_AWAIT_RX_SENSE       = 10,
    ST_INVALID              = 11,
    ST_NUM                  = 11
#else /* TMFL_TDA9981_SUPPORT && TMFL_RX_SENSE_ON */
    ST_INVALID              = 10,
    ST_NUM                  = 10
#endif /* TMFL_TDA9981_SUPPORT && TMFL_RX_SENSE_ON */
} tmbslHdmiTxState_t;

/**
 * An enum to index into the Device Instance Data shadowReg array
 */
enum _eShad
{
#ifdef TMFL_TDA9981_SUPPORT
    E_SP00_MAIN_CNTRL0  = 0,
    E_SP00_INT_FLAGS_0  = 1,
    E_SP00_INT_FLAGS_1  = 2,
    E_SP00_INT_FLAGS_2  = 3,
    E_SP00_VIP_CNTRL_0  = 4,
    E_SP00_VIP_CNTRL_1  = 5,
    E_SP00_VIP_CNTRL_2  = 6,
    E_SP00_VIP_CNTRL_3  = 7,
    E_SP00_VIP_CNTRL_4  = 8,
    E_SP00_VIP_CNTRL_5  = 9,
    E_SP00_MAT_CONTRL   = 10,
    E_SP00_TBG_CNTRL_0  = 11,
    E_SP00_TBG_CNTRL_1  = 12,
    E_SP00_HVF_CNTRL_0  = 13,
    E_SP00_HVF_CNTRL_1  = 14,
    E_SP00_TIMER_H      = 15,
    E_SP00_DEBUG_PROBE  = 16,
    E_SP00_AIP_CLKSEL   = 17,
#ifndef NO_HDCP
    E_SP12_HDCP_CTRL    = 18,
#ifdef BCAPS_REPEATER
    E_SP12_HDCP_BCAPS   = 19,
    E_SNUM              = 20,   /* Number of shadow registers */
    E_SNONE             = 20    /* Index value indicating no shadow register */
#else
    E_SNUM              = 19,   /* Number of shadow registers */
    E_SNONE             = 19    /* Index value indicating no shadow register */
#endif /* BCAPS_REPEATER */
#else
    E_SNUM              = 18,   /* Number of shadow registers */
    E_SNONE             = 18    /* Index value indicating no shadow register */
#endif /* NO_HDCP */
#else
    E_SP00_MAIN_CNTRL0  = 0,
    E_SP00_INT_FLAGS_0  = 1,
    E_SP00_INT_FLAGS_1  = 2,
    E_SP00_VIP_CNTRL_0  = 3,
    E_SP00_VIP_CNTRL_1  = 4,
    E_SP00_VIP_CNTRL_2  = 5,
    E_SP00_VIP_CNTRL_3  = 6,
    E_SP00_VIP_CNTRL_4  = 7,
    E_SP00_VIP_CNTRL_5  = 8,
    E_SP00_MAT_CONTRL   = 9,
    E_SP00_TBG_CNTRL_0  = 10,
    E_SP00_TBG_CNTRL_1  = 11,
    E_SP00_HVF_CNTRL_0  = 12,
    E_SP00_HVF_CNTRL_1  = 13,
    E_SP00_TIMER_H      = 14,
    E_SP00_DEBUG_PROBE  = 15,
    E_SP00_AIP_CLKSEL   = 16,
    E_SP01_SC_VIDFORMAT = 17,
    E_SP01_SC_CNTRL     = 18,
    E_SP01_TBG_CNTRL_0  = 19,
#ifndef NO_HDCP
    E_SP12_HDCP_CTRL    = 20,
#ifdef BCAPS_REPEATER
    E_SP12_HDCP_BCAPS   = 21,
    E_SNUM              = 22,   /* Number of shadow registers */
    E_SNONE             = 22    /* Index value indicating no shadow register */
#else
    E_SNUM              = 21,   /* Number of shadow registers */
    E_SNONE             = 21    /* Index value indicating no shadow register */
#endif /* BCAPS_REPEATER */
#else
    E_SNUM              = 20,   /* Number of shadow registers */
    E_SNONE             = 20    /* Index value indicating no shadow register */
#endif /* NO_HDCP */
#endif /* TMFL_TDA9981_SUPPORT */
};

/**
 * Page list
 * These are indexes to the allowed register page numbers
 */
enum _ePage
{
    E_PAGE_00      = 0,
    E_PAGE_01      = 1,
    E_PAGE_02      = 2,
    E_PAGE_10      = 3,         /* New for N4 */
    E_PAGE_11      = 4,
    E_PAGE_12      = 5,
    E_PAGE_NUM     = 6,         /* Number of pages */
    E_PAGE_INVALID = 6          /* Index value indicating invalid page */
};

/**
 * Macros to initialize and access the following register list enum _eReg
 */
/* Pack shadow index s, page index p and register address a into UInt16 */
#define SPA(s,p,a)       (UInt16)(((s)<<11)|((p)<<8)|(a))
/* Unpacks shadow index s from UInt16 */
#define SPA2SHAD(spa)    (UInt8)((spa)>>11)
/* Unpacks page index p from UInt16 */
#define SPA2PAGE(spa)    (UInt8)(((spa)>>8)&0x0007)
/* Unpacks register address a from UInt16 */
#define SPA2ADDR(spa)    (UInt8)((spa)&0x00FF)

/**
 * Register list
 *
 * Each register symbol has these fields: E_REG_page_register_access
 *
 * The symbols have a 16-bit value as follows, including an index to
 * the Device Instance Data shadowReg[] array:
 *
 * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
 * |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
 * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
 * |  Shadow Index     |Page Index |       Register Address        |
 * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
 *
 */
enum _eReg
{
    /*************************************************************************/
    /** Rows formatted in "HDMI Driver - Register List.xls" and pasted here **/
    /*************************************************************************/
    E_REG_MIN_ADR                   = 0x00, /* First register on all pages   */
    E_REG_CURPAGE_ADR_W             = 0xFF, /* Address register on all pages */
                                            
    E_REG_P00_VERSION_R             = SPA(E_SNONE            , E_PAGE_00, 0x00),
    E_REG_P00_MAIN_CNTRL0_W         = SPA(E_SP00_MAIN_CNTRL0 , E_PAGE_00, 0x01),
#ifdef TMFL_TDA9981_SUPPORT
    E_REG_P00_SR_REG_W              = SPA(E_SNONE            , E_PAGE_00, 0x0A),
    E_REG_P00_DDC_DISABLE_RW        = SPA(E_SNONE            , E_PAGE_00, 0x0B),
    E_REG_P00_CCLK_ON_RW            = SPA(E_SNONE            , E_PAGE_00, 0x0C),
#endif /* TMFL_TDA9981_SUPPORT */
    E_REG_P00_INT_FLAGS_0_RW        = SPA(E_SP00_INT_FLAGS_0 , E_PAGE_00, 0x0F),
    E_REG_P00_INT_FLAGS_1_RW        = SPA(E_SP00_INT_FLAGS_1 , E_PAGE_00, 0x10),
#ifdef TMFL_TDA9981_SUPPORT
    E_REG_P00_INT_FLAGS_2_RW        = SPA(E_SP00_INT_FLAGS_2 , E_PAGE_00, 0x11),
    E_REG_P00_INT_FLAGS_3_R         = SPA(E_SNONE            , E_PAGE_00, 0x12),
    E_REG_P00_SW_INT_W              = SPA(E_SNONE            , E_PAGE_00, 0x15),
    E_REG_P00_ENA_VP_0_RW           = SPA(E_SNONE            , E_PAGE_00, 0x18),
    E_REG_P00_ENA_VP_1_RW           = SPA(E_SNONE            , E_PAGE_00, 0x19),
    E_REG_P00_ENA_VP_2_RW           = SPA(E_SNONE            , E_PAGE_00, 0x1A),
    E_REG_P00_GND_VP_0_RW           = SPA(E_SNONE            , E_PAGE_00, 0x1B),
    E_REG_P00_GND_VP_1_RW           = SPA(E_SNONE            , E_PAGE_00, 0x1C),
    E_REG_P00_GND_VP_2_RW           = SPA(E_SNONE            , E_PAGE_00, 0x1D),
    E_REG_P00_ENA_AP_RW             = SPA(E_SNONE            , E_PAGE_00, 0x1E),
    E_REG_P00_GND_AP_RW             = SPA(E_SNONE            , E_PAGE_00, 0x1F),
#endif /* TMFL_TDA9981_SUPPORT */
    E_REG_P00_VIP_CNTRL_0_W         = SPA(E_SP00_VIP_CNTRL_0 , E_PAGE_00, 0x20),
    E_REG_P00_VIP_CNTRL_1_W         = SPA(E_SP00_VIP_CNTRL_1 , E_PAGE_00, 0x21),
    E_REG_P00_VIP_CNTRL_2_W         = SPA(E_SP00_VIP_CNTRL_2 , E_PAGE_00, 0x22),
    E_REG_P00_VIP_CNTRL_3_W         = SPA(E_SP00_VIP_CNTRL_3 , E_PAGE_00, 0x23),
    E_REG_P00_VIP_CNTRL_4_W         = SPA(E_SP00_VIP_CNTRL_4 , E_PAGE_00, 0x24),
    E_REG_P00_VIP_CNTRL_5_W         = SPA(E_SP00_VIP_CNTRL_5 , E_PAGE_00, 0x25),
    E_REG_P00_MAT_CONTRL_W          = SPA(E_SP00_MAT_CONTRL  , E_PAGE_00, 0x80),
    E_REG_P00_MAT_OI1_MSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x81),
    E_REG_P00_MAT_OI1_LSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x82),
    E_REG_P00_MAT_OI2_MSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x83),
    E_REG_P00_MAT_OI2_LSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x84),
    E_REG_P00_MAT_OI3_MSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x85),
    E_REG_P00_MAT_OI3_LSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x86),
    E_REG_P00_MAT_P11_MSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x87),
    E_REG_P00_MAT_P11_LSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x88),
    E_REG_P00_MAT_P12_MSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x89),
    E_REG_P00_MAT_P12_LSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x8A),
    E_REG_P00_MAT_P13_MSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x8B),
    E_REG_P00_MAT_P13_LSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x8C),
    E_REG_P00_MAT_P21_MSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x8D),
    E_REG_P00_MAT_P21_LSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x8E),
    E_REG_P00_MAT_P22_MSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x8F),
    E_REG_P00_MAT_P22_LSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x90),
    E_REG_P00_MAT_P23_MSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x91),
    E_REG_P00_MAT_P23_LSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x92),
    E_REG_P00_MAT_P31_MSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x93),
    E_REG_P00_MAT_P31_LSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x94),
    E_REG_P00_MAT_P32_MSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x95),
    E_REG_P00_MAT_P32_LSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x96),
    E_REG_P00_MAT_P33_MSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x97),
    E_REG_P00_MAT_P33_LSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x98),
    E_REG_P00_MAT_OO1_MSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x99),
    E_REG_P00_MAT_OO1_LSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x9A),
    E_REG_P00_MAT_OO2_MSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x9B),
    E_REG_P00_MAT_OO2_LSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x9C),
    E_REG_P00_MAT_OO3_MSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x9D),
    E_REG_P00_MAT_OO3_LSB_W         = SPA(E_SNONE            , E_PAGE_00, 0x9E),
    E_REG_P00_VIDFORMAT_W           = SPA(E_SNONE            , E_PAGE_00, 0xA0),
    E_REG_P00_REFPIX_MSB_W          = SPA(E_SNONE            , E_PAGE_00, 0xA1),
    E_REG_P00_REFPIX_LSB_W          = SPA(E_SNONE            , E_PAGE_00, 0xA2),
    E_REG_P00_REFLINE_MSB_W         = SPA(E_SNONE            , E_PAGE_00, 0xA3),
    E_REG_P00_REFLINE_LSB_W         = SPA(E_SNONE            , E_PAGE_00, 0xA4),
    E_REG_P00_NPIX_MSB_W            = SPA(E_SNONE            , E_PAGE_00, 0xA5),
    E_REG_P00_NPIX_LSB_W            = SPA(E_SNONE            , E_PAGE_00, 0xA6),