cx24143_regs.c

QPSK Tuner details, for conexant chipset.

/* cobra_reg.c */

/****************************************************************************

* Conexant QPSK driver  (internal mode)                                                          			 *

* Copyright ? Shenzhen Coship Electronics Co.，LTD.            						 *

* All rights reserved.                                                  								 *

* Author: Sunfugong                                                   								 *

* Create Date:  2005/7/20                                                       						 *

* Update:   2005/8/01  Sunfugong												 *

*****************************************************************************/
//#include "warnfix.h"
#include <stdio.h>                     /* ANSI Standard */

#include "cx24143_all.h"                     /* Cobra include files, ordered */
#include "cx24143_regs.h"                /* Cobra Internal */

/* performs Cobra register I/O using the cobra_reg.h REGISTER structure to determine        */
/* how register data is read and written to the Demod.                                      */

/*******************************************************************************************************/
/* RegisterRead() */
/*******************************************************************************************************/
BOOL           RegisterRead(           /* function to read a register named in the reg.map */
NIM            *nim,                   /* pointer to nim */
REGIDX         regidx,                 /* index to register name */
ULONG  *val)                   /* pointer to long where value read is returned */
{
  static  UCHAR    temp_buf[4];
  ULONG   ioval;

  /* test that regidx points to the correct register record */
  if (Register[regidx].reg_idx != regidx)
  {
    /* register record does not match passed regidx (this is a big problem!) */
    DRIVER_SetError(nim,REG_MATCH_IDX);
    return(False);
  }

  /* test for register that is Read-only */
  switch (Register[regidx].regRW)
  {
    case  REG_RW:
    case  REG_RO:
    {
      break;
    }
    case  REG_WO:
    {
      /* error -- register is write-only */
      DRIVER_SetError(nim,REG_HDWR_REGWTO);
      return(False);
      break;
    }
    default:
    {
      DRIVER_SetError(nim,REG_VERFY_REGRW);
      return(False);
      break;
    }
  }  /* switch(... */

  /* read from the hardware */
  if (RegisterReadFromHDWR(nim,regidx,temp_buf) == False)  return(False);

  /* translate to usable -> translate from raw to enum */
  if (RegisterTranslate(regidx,(LONG*)&ioval,temp_buf) != True)
  {
    /* translation error */
    DRIVER_SetError(nim,REG_MATCH_TRX);
    return(False);
  }

  /* return translated value to caller */
  *val = ioval;

  return(True);

}  /* RegisterRead() */


/*******************************************************************************************************/
/* RegisterWrite() */
/*******************************************************************************************************/
BOOL           RegisterWrite(          /* function to write to a register named in the reg.map */
NIM            *nim,                   /* pointer to nim */
REGIDX         regidx,                 /* index to register name */
ULONG  val)                    /* value to write to register */
{
  ULONG   range_test = 0UL;
  static  UCHAR    temp_buf[4];

  /* test that regidx points to the correct register record */
  if (Register[regidx].reg_idx != regidx)
  {
    /* register record does not match passed regidx (this is a big problem!) */
    DRIVER_SetError(nim,REG_MATCH_IDX);
    return(False);
  }

  /* test that unsigned long value to be written is at least within allowable range */
  /* (mark as an error, but write value anyway!) */
  range_test = (0x01UL << Register[regidx].bit_count)-1UL;
  if (val > range_test)
  {
    /* range exceeded, mark error (warning) BUT continue */
    DRIVER_SetError(nim,API_RANGE);
  }

  /* test for register that is Read-only */
  switch (Register[regidx].regRW)
  {
    case  REG_RW:
    case  REG_WO:
    {
      break;
    }
    case  REG_RO:
    {
      /* error -- register is read-only */
      DRIVER_SetError(nim,REG_HDWR_REGRDO);
      return(False);
      break;
    }
    default:
    {
      DRIVER_SetError(nim,REG_VERFY_REGRW);
      return(False);
      break;
    }
  }  /* switch(... */

  /* translate from numeric to hardware-writable format */
  if (RegisterDeTranslate(regidx,temp_buf,val) != True)
  {
    /* de-translation error */
    DRIVER_SetError(nim,REG_MATCH_DTRX);
    return(False);
  }

  /* write to the hardware */
  if (RegisterWriteToHDWR(nim,regidx,temp_buf) == False)  return(False);

  return(True);

}  /* RegisterWrite() */


/*******************************************************************************************************/
/* RegisterReadFromHDWR() */
/*******************************************************************************************************/
BOOL           RegisterReadFromHDWR(   /* low-level i/o function to read bytes from hardware */
NIM            *nim,                   /* pointer to nim */
REGIDX         regidx,                 /* register index */
UCHAR  *rbuf)                  /* pointer to storage where read data will be stored */
{
  register int  i = 0;            /* counts bits read */
  UCHAR offst = 0;    /* counts bytes read */

  /* clear io error return value */
  nim->iostatus = 0UL;

  /* read until minimum number of bits (yes, bits) are read into union */
  offst = 0;
  nim->iostatus = 0UL;
  while (i < Register[regidx].bit_count && nim->iostatus != 1UL)
  {
    rbuf[offst] = (*nim->SBRead)(nim->demod_handle,(UCHAR)(Register[regidx].addr+offst),&nim->iostatus);
    offst++;
    i += 8;
  }

  if (nim->iostatus != 0UL)
  {
    /* read error reading hardware */
    DRIVER_SetError(nim,API_IO_READERR);
    return(False);
  }

  return(True);

}  /* RegisterReadFromHDWR() */


/*******************************************************************************************************/
/* RegisterWriteToHDWR() */
/*******************************************************************************************************/
BOOL           RegisterWriteToHDWR(    /* low-level function to write bytes to hardware */
NIM            *nim,                   /* nim to write data to */
REGIDX         regidx,                 /* register index number */
UCHAR  *wbuf)                  /* data to write to register (translated) */
{
  register int  i;            /* counts bits read */
  UCHAR offst;        /* counts bytes read */

  static union 
  {
    ULONG   ulTemp;
    UCHAR   c[sizeof(ULONG)];
  }u;

  /* clear io error return value */
  nim->iostatus = 0UL;

  /* write until minimum number of bits written from union */
  for (i = 0 , offst = 0; Register[regidx].hwmask[i] != 0x00 ; i++ , offst++)
  {
    /* add'l test for eo-mask */
    if (Register[regidx].hwmask[i] == 0x00)  break;
    else
    {
      /* if whole byte is occupied, no need to read/mask/write, just write it */
      if (Register[regidx].hwmask[i] == 0xff)
      {
        /* write the byte to the hardware */
        (*nim->SBWrite)(nim->demod_handle,(UCHAR)(Register[regidx].addr+offst),wbuf[i],&nim->iostatus);
      }
      else
      {
        if (Register[regidx].regtype != REGT_BITHL)
        {
          /* byte must be read, masked, written */
          u.c[offst] = (*nim->SBRead)(nim->demod_handle,(UCHAR)(Register[regidx].addr+offst),&nim->iostatus);

          /* watch for special-case error, read error during write */
          if (nim->iostatus != 0UL)