cx24143_fun.c
来自「QPSK Tuner details, for conexant chipset」· C语言 代码 · 共 1,929 行 · 第 1/5 页
C
1,929 行
NIM *nim, /* NIM pointer */
MODTYPE modtype) /* modulation type: QPSK, BPSK */
{
ULONG ulRegVal;
/* validate nim and mpeg storage */
if (DRIVER_ValidateNim(nim) == False) return(False);
switch(modtype)
{
case MOD_QPSK:
case MOD_BPSK:
{
ulRegVal = (modtype == MOD_QPSK ? BIT_ZERO : BIT_ONE);
if (RegisterWrite(nim,CX24130_SYSMODTYPE,ulRegVal) == False) return(False);
break;
}
case MOD_QPSK_DCII_MUX:
{
/* set DCII mode to "combined" */
ulRegVal = 0x00UL;
if (RegisterWrite(nim,CX24130_DC2MODE,ulRegVal) == False) return(False);
break;
}
case MOD_QPSK_DCII_SPLIT_I:
{
/* set DCII mode to Split I */
ulRegVal = 0x03UL;
if (RegisterWrite(nim,CX24130_DC2MODE,ulRegVal) == False) return(False);
break;
}
case MOD_QPSK_DCII_SPLIT_Q:
{
/* set DCII mode to Split Q */
ulRegVal = 0x02UL;
if (RegisterWrite(nim,CX24130_DC2MODE,ulRegVal) == False) return(False);
break;
}
case MOD_UNDEF:
default:
{
/* bad parameter passed */
DRIVER_SetError(nim,API_BAD_PARM);
return(False);
break;
}
} /* switch(... */
return(True);
} /* API_SetModulation() */
/*******************************************************************************************************/
/* API_GetModulation() */
/*******************************************************************************************************/
BOOL API_GetModulation( /* function to retrieve current modulation setting from the nim */
NIM *nim, /* pointer to nim */
MODTYPE *modtype) /* returned modulation type */
{
ULONG ulRegVal;
/* test for valid NIM and parm not NULL */
if (DRIVER_ValidateNim(nim) == False) return(False);
if (modtype == NULL) DRIVER_SetError(nim,API_BAD_PARM);
else
{
/* read modulation type from cobra */
if (RegisterRead(nim,CX24130_SYSMODTYPE,&ulRegVal) == False) return(False);
/* convert returned raw value to enum */
/* (removed per CR 6323) modtype = (ulRegVal == BIT_ZERO ? MOD_QPSK : MOD_BPSK); */
if (ulRegVal == BIT_ZERO) *modtype = MOD_QPSK;
else *modtype = MOD_BPSK;
return(True);
}
return(False);
} /* API_GetModulation() */
/*******************************************************************************************************/
/* API_GetAssociatedSampleFrequency() */
/*******************************************************************************************************/
BOOL API_GetAssociatedSampleFrequency( /* function to return sample freq to the caller */
NIM *nim, /* pointer to nim */
SAMPFRQ sampfrq, /* sample frequency */
ULONG *AssdFs) /* returned Fs to caller */
{
int i;
ULONG pll_mult;
ULONG samplerate;
/* validate nim */
if (DRIVER_ValidateNim(nim) == False) return(False);
if (AssdFs != NULL)
{
for (i = 0 ; sampfrq_list[i] != SAMPLE_FREQ_UNDEF ; i++)
{
if (sampfrq_list[i] == sampfrq)
{
/* get sample frequency from caller's selection from list */
samplerate = sampfrq_eqlist[i];
/* compute the demod pll multiplier */
pll_mult = DRIVER_compute_demod_pll_mult(nim,samplerate,nim->crystal_freq);
*AssdFs = DRIVER_compute_fs(pll_mult,nim->crystal_freq);
/* return Ass'd Fs to caller -> use progFs (Fs-value programmed to the demod) * Fc / 6 */
return(True);
}
}
}
DRIVER_SetError(nim,API_BAD_PARM);
return(False);
} /* API_GetAssociatedSampleFrequency() */
/*******************************************************************************************************/
/* API_SetSampleFrequency() */
/*******************************************************************************************************/
BOOL API_SetSampleFrequency( /* function to set the sample frequency */
NIM *nim, /* pointer to nim */
SAMPFRQ sampfrq) /* sample freq number (from allowable sample freq. list) */
{
int i;
ULONG pllmult;
ULONG samplerate = 0UL;
/* validate nim and mpeg storage */
if (DRIVER_ValidateNim(nim) == False) return(False);
/* match sampfrq enum (1..n) passed in by caller to an associated Fs in a list */
for (i = 0 ; sampfrq_list[i] != SAMPLE_FREQ_UNDEF ; i++)
{
/* test each item in list for a match */
if (sampfrq_list[i] == sampfrq)
{
/* extract the associated sample freq from the list */
samplerate = sampfrq_eqlist[i];
break;
}
}
if (sampfrq_list[i] == SAMPLE_FREQ_UNDEF)
{
DRIVER_SetError(nim,API_BAD_PARM);
return(False);
}
#ifdef CAMARIC_FEATURES
if (DRIVER_Camaric(nim) == True)
{
if (nim->symbol_rate_ideal <= 4000UL)
{
/* set sampling freq to 26.963MHz if symbol rate is less than 4Msps */
samplerate = SAMPLE_FREQ_LT_4MSPS;
}
else
{
/* set sampling freq to 99.425MHz if it is less than 2 times of symbol rate */
if (samplerate < (nim->symbol_rate_ideal * M * 2UL))
{
samplerate = SAMPLE_FREQ_NOM_VAL;
}
}
}
#endif /* #ifdef CAMARIC_FEATURES */
/* compute the PLL value for the sample rate */
pllmult = DRIVER_compute_demod_pll_mult(nim,samplerate,nim->crystal_freq);
/* set the value to write to the demod */
if (RegisterWritePLLMult(nim,pllmult) == False)
{
return(False);
}
return (True);
} /* API_SetSampleFrequency() */
/*******************************************************************************************************/
/* __API_SetSampleFrequency() */
/*******************************************************************************************************/
BOOL __API_SetSampleFrequency( /* function to set the sample frequency without using ENUM SAMPFRQ */
NIM *nim, /* pointer to nim */
ULONG sampleratehz) /* sample freq number (not ENUM) */
{
ULONG pllmult;
/* validate nim and mpeg storage */
if (DRIVER_ValidateNim(nim) == False) return(False);
/* compute the PLL value for the sample rate */
pllmult = DRIVER_compute_demod_pll_mult(nim,sampleratehz,nim->crystal_freq);
/* set the value to write to the demod */
if (RegisterWritePLLMult(nim,pllmult) == False)
{
return(False);
}
return(True);
} /* __API_SetSampleFrequency() */
/*******************************************************************************************************/
/* API_GetSampleFrequency() */
/*******************************************************************************************************/
BOOL API_GetSampleFrequency( /* function to read demod's current sample rate */
NIM *nim, /* pointer to nim */
ULONG *samplerate) /* returned sample rate */
{
ULONG pllmult;
ULONG rate;
/* validate nim and mpeg storage */
if (DRIVER_ValidateNim(nim) == False) return(False);
if (samplerate != NULL)
{
/* read the pll mult from the demod, find the associated SAMPFRQ */
pllmult = (ULONG)nim->ucPLLMult_shadow;
rate = DRIVER_compute_fs(pllmult,nim->crystal_freq);
*samplerate = rate;
return(True);
}
DRIVER_SetError(nim,API_BAD_PARM);
return(False);
} /* API_GetSampleFrequency() */
/*******************************************************************************************************/
/* API_SetTransportSpec() */
/*******************************************************************************************************/
BOOL API_SetTransportSpec( /* function to set the NIM's transport spec */
NIM *nim, /* pointer to nim */
TRANSPEC transpec) /* transport specification */
{
ULONG ulRegVal;
/* test for valid NIM and parm not NULL */
if (DRIVER_ValidateNim(nim) == False) return(False);
/* perform a "firm" (i.e. not a soft, nor a hard) reset */
/* DRIVER_Reset(nim) ; */
/* perform a "hard" reset (as a last resort) */
/* DRIVER_HardReset(nim); */
/* 9/11/01 code added to test if DCII mode register must be reset for NIM B (s/b reset via DRIVER_default() */
if (RegisterRead(nim,CX24130_DC2MODE,&ulRegVal) == False) return(False);
if (ulRegVal != 0x00UL)
{
ulRegVal = 0x00;
if (RegisterWrite(nim,CX24130_DC2MODE,ulRegVal) == False) return(False);
}
/* set the transport spec */
switch (transpec)
{
case SPEC_DSS:
{
/* reset the sub-dcii mode */
ulRegVal = 0x00UL;
if (RegisterWrite(nim,CX24130_DC2MODE,ulRegVal) == False) return(False);
/* set modulation to DSS */
ulRegVal = 0x01UL;
if (RegisterWrite(nim,CX24130_SYSTRANSTD,ulRegVal) == False) return(False);
/* (CR 8114) This code executed only if Rev C or single demod */
ulRegVal = 0x08UL;
if (RegisterWrite(nim,CX24130_ACQSYNCBYTEWIN,ulRegVal) == False) return(False);
ulRegVal = 0x05UL;
if (RegisterWrite(nim,CX24130_ACQRSSYNCTHRESH,ulRegVal) == False) return(False);
ulRegVal = 0xff;
if (RegisterWrite(nim,CX24130_ACQVITNORMTHRESH,ulRegVal) == False) return(False);
ulRegVal = 0x09;
if (RegisterWrite(nim,CX24130_ACQVITNORMWIN12,ulRegVal) == False) return(False);
ulRegVal = 0x15;
if (RegisterWrite(nim,CX24130_ACQVITNORMWIN23,ulRegVal) == False) return(False);
ulRegVal = 0x56;
if (RegisterWrite(nim,CX24130_ACQVITNORMWIN67,ulRegVal) == False) return(False);
ulRegVal = 0x10;
if (RegisterWrite(nim,CX24130_ACQFULLSYNCWIN,ulRegVal) == False) return(False);
break;
}
case SPEC_DVB:
{
/* reset the sub-dcii mode */
ulRegVal = 0x00UL;
if (RegisterWrite(nim,CX24130_DC2MODE,ulRegVal) == False) return(False);
/* modulation in BVDs */
ulRegVal = 0x00UL;
if (RegisterWrite(nim,CX24130_SYSTRANSTD,ulRegVal) == False) return(False);
/* new transpec mods 8/29/01 */
ulRegVal = 0x08UL;
if (RegisterWrite(nim,CX24130_ACQSYNCBYTEWIN,ulRegVal) == False) return(False);
ulRegVal = 0x05UL;
if (RegisterWrite(nim,CX24130_ACQRSSYNCTHRESH,ulRegVal) == False) return(False);
/* (CR 7930) */
ulRegVal = 0xfe;
if (RegisterWrite(nim,CX24130_ACQVITNORMTHRESH,ulRegVal) == False) return(False);
ulRegVal = 0x09;
if (RegisterWrite(nim,CX24130_ACQVITNORMWIN12,ulRegVal) == False) return(False);
ulRegVal = 0x15;
if (RegisterWrite(nim,CX24130_ACQVITNORMWIN23,ulRegVal) == False) return(False);
ulRegVal = 0x24;
if (RegisterWrite(nim,CX24130_ACQVITNORMWIN34,ulRegVal) == False) return(False);
ulRegVal = 0x34;
if (RegisterWrite(nim,CX24130_ACQVITNORMWIN45,ulRegVal) == False) return(False);
ulRegVal = 0x44;
if (RegisterWrite(nim,CX24130_ACQVITNORMWIN56,ulRegVal) == False) return(False);
ulRegVal = 0x56;
if (RegisterWrite(nim,CX24130_ACQVITNORMWIN67,ulRegVal) == False) return(False);
ulRegVal = 0x64;
if (RegisterWrite(nim,CX24130_ACQVITNORMWIN78,ulRegVal) == False) return(False);
ulRegVal = 0x10;
if (RegisterWrite(nim,CX24130_ACQFULLSYNCWIN,ulRegVal) == False) return(False);
break;
}
case SPEC_DCII:
{
/* set modulation to DCII */
ulRegVal = 0x03UL;
if (RegisterWrite(nim,CX24130_SYSTRANSTD,ulRegVal) == False) return(False);
/* set DCII mode to "combined" */
ulRegVal = 0x00UL;
if (RegisterWrite(nim,CX24130_DC2MODE,ulRegVal) == False) return(False);
/* new transpec mods per cp 8/29/01 */
ulRegVal = 0x20UL;
if (RegisterWrite(nim,CX24130_ACQSYNCBYTEWIN,ulRegVal) == False) return(False);
ulRegVal = 0x02UL;
if (RegisterWrite(nim,CX24130_ACQRSSYNCTHRESH,ulRegVal) == False) return(False);
ulRegVal = 0x09;
if (RegisterWrite(nim,CX24130_ACQVITNORMWIN12,ulRegVal) == False) return(False);
ulRegVal = 0x15;
if (RegisterWrite(nim,CX24130_ACQVITNORMWIN23,ulRegVal) == False) return(False);
ulRegVal = 0x56;
if (RegisterWrite(nim,CX24130_ACQVITNORMWIN67,ulRegVal) == False) return(False);
ulRegVal = 0x10;
if (RegisterWrite(nim,CX24130_ACQFULLSYNCWIN,ulRegVal) == False) return(False);
/* (CR 8218) Set DCII ClkDis */
ulRegVal = 0x00;
if (RegisterWrite(nim,CX24130_DC2CLKDIS,ulRegVal) == False) return(False);
#ifdef DCII_DEFAULT_SMOOTHCLK
/* (CR 8209) Added following block of code to allow default MPEG Smooth Clk Div setting */
if (transpec == SPEC_DCII)
{
ulRegVal = DCII_HARD_SMOOTHCLK;
if (RegisterWriteClkSmoothDiv(nim,ulRegVal) == False) return(False);
}
#endif /* #ifdef DCII_DEFAULT_SMOOTHCLK */
break;
}
#ifdef CAMARIC_FEATURES
case SPEC_DVB_DSS:
{
/* reset the sub-dcii mode */
ulRegVal = 0x00UL;
if (RegisterWrite(nim,CX24130_DC2MODE,ulRegVal) == False) return(False);
/* modulation is either DVB or DSS */
ulRegVal = 0x02UL;
if (RegisterWrite(nim,CX24130_SYSTRANSTD,ulRegVal) == False) return(False);
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