phantom_cmd.c
来自「QPSK Tuner details, for conexant chipset」· C语言 代码 · 共 769 行 · 第 1/3 页
C
769 行
/* phantom_cmd.c */
/*+++ *******************************************************************\
*
* Abstract:
*
* Contains all register-based code to perform I/O to, from the Demod,
* excluding the lowest-level I/O functions: SBREAD and SBWRITE. Both
* of which are dependant upon hardware implementation.
*
* Created: 3/30/2004
*
* Author: Amarnath Puttur
*
* Copyright and Disclaimer:
*
* ---------------------------------------------------------------
* This software is provided "AS IS" without warranty of any kind,
* either expressed or implied, including but not limited to the
* implied warranties of noninfringement, merchantability and/or
* fitness for a particular purpose.
* ---------------------------------------------------------------
*
* Copyright (c) 2004 Conexant Systems, Inc.
* All rights reserved.
*
\******************************************************************* ---*/
#include <stdio.h> /* ANSI Standard */
#include "phantom.h" /* Phantom include files, ordered */
#include "phantom_cmd.h" /* Phantom Internal */
/***************************************************************************************************************************
| -- D E M O D R E G I S T E R M A P -- |
***************************************************************************************************************************/
const PHANTOM_REGISTER_MAP phantom_register_map[] = {
/* ------------------------------------------------------------------------------------------------------------------------*
| [bit_field] [address] [start_bit][bits] [access] [reg_type] [hw_mask]|
* ------------------------------------------------------------------------------------------------------------------------*/
{PHANTOM_SC_FE_CHIP_VERSION, PHANTOM_SC_CHIP_VERSION, 7, 8, PHANTOM_REG_RO, PHANTOM_REGT_BYTE, "\xFF"},
{PHANTOM_SC_FF_CHIP_TYPE, PHANTOM_SC_CHIP_TYPE, 7, 8, PHANTOM_REG_RO, PHANTOM_REGT_BYTE, "\xFF"},
/* GPIO */
{PHANTOM_SC_FC_GPIO_DIRECTION, PHANTOM_SC_GPIO_DIRECTION, 7, 4, PHANTOM_REG_RO, PHANTOM_REGT_BIT, "\xF0"},
{PHANTOM_SC_FC_GPIO_OUTPUTS, PHANTOM_SC_GPIO_OUTPUTS, 3, 4, PHANTOM_REG_RO, PHANTOM_REGT_BIT, "\x0F"},
{PHANTOM_SC_FD_GPIO_INPUTS, PHANTOM_SC_GPIO_INPUTS, 6, 7, PHANTOM_REG_RO, PHANTOM_REGT_BIT, "\x3F"},
{PHANTOM_SC_F9_ADC_MODE_SEL, PHANTOM_SC_ADC_MODE_SELECT, 0, 1, PHANTOM_REG_RW, PHANTOM_REGT_BIT, "\x01"},
{PHANTOM_SC_F8_PLL_LCLK_DIV, PHANTOM_SC_PLL_LCLK_REG, 2, 3, PHANTOM_REG_RW, PHANTOM_REGT_BIT, "\x07"},
{PHANTOM_SC_F4_DOWNLOAD_CONTROL, PHANTOM_SC_DOWNLOAD_CONTROL, 7, 8, PHANTOM_REG_WO, PHANTOM_REGT_BIT, "\x97"},
{PHANTOM_SC_F1_PLL_SPMP, PHANTOM_SC_PLL_SPMP, 7, 8, PHANTOM_REG_RW, PHANTOM_REGT_BYTE, "\xFF"},
{PHANTOM_SC_F2_PLL_SDIV, PHANTOM_SC_PLL_SDIV, 7, 8, PHANTOM_REG_RW, PHANTOM_REGT_BYTE, "\xFF"},
{PHANTOM_SC_F3_PLL_MAIN_CLK_DIV, PHANTOM_SC_PLL_CLK_DIV_CONTROL, 2, 3, PHANTOM_REG_RW, PHANTOM_REGT_BIT, "\x07"},
{PHANTOM_SC_F3_PLL_SMOOTH_CLK_DIV, PHANTOM_SC_PLL_CLK_DIV_CONTROL, 6, 3, PHANTOM_REG_RW, PHANTOM_REGT_BIT, "\x70"},
{PHANTOM_SC_F0_RESET_CNTL, PHANTOM_SC_RESET_CNTL, 7, 8, PHANTOM_REG_WO, PHANTOM_REGT_BIT, "\xFF"},
{PHANTOM_SC_F0_8051_MODULE_RESET, PHANTOM_SC_RESET_CNTL, 1, 1, PHANTOM_REG_RW, PHANTOM_REGT_BIT, "\x02"},
{PHANTOM_SC_F0_8051_SW_RESET, PHANTOM_SC_RESET_CNTL, 0, 1, PHANTOM_REG_RW, PHANTOM_REGT_BIT, "\x01"},
{PHANTOM_SC_F0_8051_CLK_DIV, PHANTOM_SC_TUNER_SB_REPEATER, 1, 2, PHANTOM_REG_WO, PHANTOM_REGT_BIT, "\x03"},
{PHANTOM_SC_EA_CLOCK_CONTROL, PHANTOM_SC_SHUT_CLK_CNTL, 7, 8, PHANTOM_REG_RW, PHANTOM_REGT_BYTE, "\xFF"},
{PHANTOM_SC_E8_BOARD_VERSION, PHANTOM_SC_ADDRESS_E8, 4, 2, PHANTOM_REG_RO, PHANTOM_REGT_BIT, "\x18"},
{PHANTOM_SC_E3_CLK_DIV, PHANTOM_SC_AFE_CNTL0, 1, 2, PHANTOM_REG_RW, PHANTOM_REGT_BIT, "\x03"},
{PHANTOM_SC_E5_REF_CLK_DIV, PHANTOM_SC_AFE_CNTL2, 6, 1, PHANTOM_REG_RW, PHANTOM_REGT_BIT, "\x40"},
{PHANTOM_SC_E1_ADC_PDN, PHANTOM_SC_ADDRESS_E1, 1, 1, PHANTOM_REG_RW, PHANTOM_REGT_BIT, "\x02"},
{PHANTOM_SC_E0_DISEQC_ADC_ENABLE, PHANTOM_SC_ADDRESS_E0, 3, 1, PHANTOM_REG_WO, PHANTOM_REGT_BIT, "\x08"},
{PHANTOM_SC_E0_DISABLE_PLL, PHANTOM_SC_ADDRESS_E0, 0, 1, PHANTOM_REG_RW, PHANTOM_REGT_BIT, "\x01"},
/* Page0 bit-fields */
{PHANTOM_P0_96_SW_VERSION, PHANTOM_P0_SW_VERSION, 7, 8, PHANTOM_REG_RO, PHANTOM_REGT_BYTE, "\xFF"},
/* Channel parameters */
{PHANTOM_P0_97_TUNER_FREQ_KHZ, PHANTOM_P0_TUNER_FREQUENCY, 7, 24, PHANTOM_REG_RW, PHANTOM_REGT_MBYTE,"\xFF\xFF\xFF\x00"},
{PHANTOM_P0_9C_SPECINV, PHANTOM_P0_MODCODE_PILOT_SI, 6, 1, PHANTOM_REG_RO, PHANTOM_REGT_BIT, "\x40"},
{PHANTOM_P0_9C_ACTUAL_VITCODERATE, PHANTOM_P0_MODCODE_PILOT_SI, 5, 6, PHANTOM_REG_RO, PHANTOM_REGT_BIT, "\x3F"},
/* Analog AGC */
{PHANTOM_P0_9D_ANALOG_AGC_MSBITS, PHANTOM_P0_LOCK_INDICATORS, 7, 2, PHANTOM_REG_RO, PHANTOM_REGT_BIT, "\xC0"},
{PHANTOM_P0_9E_ANALOG_AGC_LSBITS, PHANTOM_P0_ANALOG_AGC, 7, 8, PHANTOM_REG_RO, PHANTOM_REGT_BYTE, "\xFF"},
/* Frequency offset */
{PHANTOM_P0_9F_FREQ_OFFSET, PHANTOM_P0_FREQ_OFFSET_KHZ, 7, 16, PHANTOM_REG_RO, PHANTOM_REGT_MBYTE,"\xFF\xFF"},
/* Symbol rate offset */
{PHANTOM_P0_A1_SYMBRATE_OFFSET, PHANTOM_P0_SYMBOL_RATE_OFFSET_KSPS,
7, 16, PHANTOM_REG_RO, PHANTOM_REGT_MBYTE,"\xFF\xFF"},
/* Lock indicators */
{PHANTOM_P0_9D_LOCK_STATUS, PHANTOM_P0_LOCK_INDICATORS, 4, 5, PHANTOM_REG_RO, PHANTOM_REGT_BIT, "\x1F"},
{PHANTOM_P0_9D_PLL_LOCK, PHANTOM_P0_LOCK_INDICATORS, 0, 1, PHANTOM_REG_RO, PHANTOM_REGT_BIT, "\x01"},
{PHANTOM_P0_9D_DEMOD_SYNC_LOCK, PHANTOM_P0_LOCK_INDICATORS, 1, 1, PHANTOM_REG_RO, PHANTOM_REGT_BIT, "\x02"},
{PHANTOM_P0_9D_LDPC_LOCK, PHANTOM_P0_LOCK_INDICATORS, 2, 1, PHANTOM_REG_RO, PHANTOM_REGT_BIT, "\x04"},
{PHANTOM_P0_9D_VITERBI_LOCK, PHANTOM_P0_LOCK_INDICATORS, 2, 1, PHANTOM_REG_RO, PHANTOM_REGT_BIT, "\x04"},
{PHANTOM_P0_9D_BCH_LOCK, PHANTOM_P0_LOCK_INDICATORS, 3, 1, PHANTOM_REG_RO, PHANTOM_REGT_BIT, "\x08"},
{PHANTOM_P0_9D_RS_LOCK, PHANTOM_P0_LOCK_INDICATORS, 3, 1, PHANTOM_REG_RO, PHANTOM_REGT_BIT, "\x08"},
{PHANTOM_P0_9D_LP_LOCK, PHANTOM_P0_LOCK_INDICATORS, 4, 1, PHANTOM_REG_RO, PHANTOM_REGT_BIT, "\x10"},
{PHANTOM_P0_9D_TUNER_HANDSHAKE, PHANTOM_P0_LOCK_INDICATORS, 5, 1, PHANTOM_REG_RW, PHANTOM_REGT_BIT, "\x20"},
/* Interrupts */
{PHANTOM_P0_BA_INTR_ENABLE, PHANTOM_P0_INTERRUPTS_ENABLE, 3, 4, PHANTOM_REG_RO, PHANTOM_REGT_BIT, "\x0F"},
{PHANTOM_P0_BB_INTR_PENDING, PHANTOM_P0_INTERRUPTS_PENDING, 3, 4, PHANTOM_REG_RO, PHANTOM_REGT_BIT, "\x0F"},
/* LNB */
{PHANTOM_P0_BC_LNB_RX_MSG_LENGTH, PHANTOM_P0_LNB_STATUS, 2, 3, PHANTOM_REG_RO, PHANTOM_REGT_BIT, "\x07"},
{PHANTOM_P0_BC_LNBDC_LEVEL, PHANTOM_P0_LNB_STATUS, 3, 1, PHANTOM_REG_RO, PHANTOM_REGT_BIT, "\x08"},
{PHANTOM_P0_BC_LNB_TX_READY, PHANTOM_P0_LNB_STATUS, 5, 1, PHANTOM_REG_RW, PHANTOM_REGT_BIT, "\x20"},
{PHANTOM_P0_BC_LNB_RX_READY, PHANTOM_P0_LNB_STATUS, 6, 1, PHANTOM_REG_RW, PHANTOM_REGT_BIT, "\x40"},
{PHANTOM_P0_BC_LNB_TONE, PHANTOM_P0_LNB_STATUS, 7, 1, PHANTOM_REG_RO, PHANTOM_REGT_BIT, "\x80"},
{PHANTOM_P0_BD_LNB_RX_ERROR, PHANTOM_P0_LNB_RX_ERROR, 7, 8, PHANTOM_REG_RO, PHANTOM_REGT_BYTE, "\xFF"},
{PHANTOM_P0_BE_LNB_REPLY_BYTE0, PHANTOM_P0_LNB_REPLY_BYTE0, 7, 8, PHANTOM_REG_RW, PHANTOM_REGT_BYTE, "\xFF"},
{PHANTOM_P0_BF_LNB_REPLY_BYTE1, PHANTOM_P0_LNB_REPLY_BYTE1, 7, 8, PHANTOM_REG_RW, PHANTOM_REGT_BYTE, "\xFF"},
{PHANTOM_P0_C0_LNB_REPLY_BYTE2, PHANTOM_P0_LNB_REPLY_BYTE2, 7, 8, PHANTOM_REG_RW, PHANTOM_REGT_BYTE, "\xFF"},
{PHANTOM_P0_C1_LNB_REPLY_BYTE3, PHANTOM_P0_LNB_REPLY_BYTE3, 7, 8, PHANTOM_REG_RW, PHANTOM_REGT_BYTE, "\xFF"},
{PHANTOM_P0_C2_LNB_REPLY_BYTE4, PHANTOM_P0_LNB_REPLY_BYTE4, 7, 8, PHANTOM_REG_RW, PHANTOM_REGT_BYTE, "\xFF"},
{PHANTOM_P0_C3_LNB_REPLY_BYTE5, PHANTOM_P0_LNB_REPLY_BYTE5, 7, 8, PHANTOM_REG_RW, PHANTOM_REGT_BYTE, "\xFF"},
{PHANTOM_P0_C4_LNB_REPLY_BYTE6, PHANTOM_P0_LNB_REPLY_BYTE6, 7, 8, PHANTOM_REG_RW, PHANTOM_REGT_BYTE, "\xFF"},
{PHANTOM_P0_C5_LNB_REPLY_BYTE7, PHANTOM_P0_LNB_REPLY_BYTE7, 7, 8, PHANTOM_REG_RW, PHANTOM_REGT_BYTE, "\xFF"},
{PHANTOM_P0_A3_ESNO_ESTIMATION_MSB, PHANTOM_P0_ESNO_ESTIMATION_MSB, 7, 8, PHANTOM_REG_RW, PHANTOM_REGT_BYTE, "\xFF"},
/* Error rate measurement */
{PHANTOM_P0_C6_CORR_BIT_ERR_COUNT, PHANTOM_P0_CORR_BIT_ERR_COUNT, 7, 32, PHANTOM_REG_RO, PHANTOM_REGT_MBYTE,"\xFF\xFF\xFF\xFF"},
{PHANTOM_P0_CA_UNCORR_FRAME_ERR_COUNT,
PHANTOM_P0_UNCORR_FRAME_ERR_COUNT,
7, 16, PHANTOM_REG_RO, PHANTOM_REGT_MBYTE,"\xFF\xFF"},
{PHANTOM_P0_CC_MEASUREMENT_COUNTER, PHANTOM_P0_MEASUREMENT_COUNTER, 7, 8, PHANTOM_REG_RO, PHANTOM_REGT_BYTE, "\xFF"},
{PHANTOM_P0_CD_CRC_FRAME_ERR_COUNT, PHANTOM_P0_CRC_FRAME_ERR_COUNT, 7, 16, PHANTOM_REG_RO, PHANTOM_REGT_MBYTE,"\xFF\xFF"},
{PHANTOM_P0_CF_CRC_MEASUREMENT_COUNTER,
PHANTOM_P0_CRC_MEASUREMENT_COUNTER,
7, 8, PHANTOM_REG_RO, PHANTOM_REGT_BYTE, "\xFF"},
{PHANTOM_P0_DB_BER_WIN_ADJUST, PHANTOM_P0_BER_WIN_ADJUST, 7, 16, PHANTOM_REG_RO, PHANTOM_REGT_MBYTE,"\xFF\xFF"},
{PHANTOM_P0_DD_CRC_WIN_ADJUST, PHANTOM_P0_CRC_WIN_ADJUST, 7, 16, PHANTOM_REG_RO, PHANTOM_REGT_MBYTE,"\xFF\xFF"},
{PHANTOM_P0_D0_TUNER_ERR_CODE, PHANTOM_P0_TUNER_ERR_CODE, 7, 8, PHANTOM_REG_RO, PHANTOM_REGT_BYTE, "\xFF"},
{PHANTOM_P0_D1_BIN_CYCLES_COUNTER, PHANTOM_P0_BIN_CYCLES_COUNTER, 7, 8, PHANTOM_REG_RO, PHANTOM_REGT_BYTE, "\xFF"},
{PHANTOM_P0_D5_ESNO_ESTIMATION_LSB, PHANTOM_P0_ESNO_ESTIMATION_LSB, 7, 8, PHANTOM_REG_RW, PHANTOM_REGT_BYTE, "\xFF"},
{PHANTOM_P0_D6_LNB_REPLY_PARITY, PHANTOM_P0_LNB_REPLY_PARITY, 7, 8, PHANTOM_REG_RO, PHANTOM_REGT_BYTE, "\xFF"},
{PHANTOM_P0_D7_ERR_CORR, PHANTOM_P0_MISC_STATUS, 0, 1, PHANTOM_REG_RO, PHANTOM_REGT_BIT, "\x01"},
{PHANTOM_P0_D8_ACQUISITION_TIME_COUNTER,
PHANTOM_P0_ACQUISITION_TIME, 7, 16, PHANTOM_REG_RO, PHANTOM_REGT_MBYTE,"\xFF\xFF"},
{PHANTOM_P0_DA_ESTIMATED_INPUT_POWER,
PHANTOM_P0_ESTIMATED_INPUT_POWER,
7, 8, PHANTOM_REG_RO, PHANTOM_REGT_BYTE, "\xFF"}
};
/*** END OF REGISTER MAP ***********************************************************************************************/
/*******************************************************************************************************
* C O M M A N D I N T E R F A C E F U N C T I O N S
*******************************************************************************************************/
/* === Register Functions ===*/
/*******************************************************************************************************
* Name: PHANTOM_RegisterWrite
*
* Description:
* This function writes to a bit-field or a byte in the special control area. This function is NOT
* applicable for Page0 address space since it is read-only.
* Return Value:
* TRUE - operation successful; FALSE - otherwise.
*
* I/O Parameters Descriptions
* IN PHANTOM_NIM* p_nim Pointer to PHANTOM_NIM structure allocated by application
* IN REGISTER_BIT_FIELD reg_field_index Index that uniquely identifies the value within a register
* (or spanning multiple 8-bit registers while reading from Page0).
* IN unsigned long value Value to be written.
*******************************************************************************************************/
BOOL
PHANTOM_RegisterWrite(PHANTOM_NIM* p_nim,
unsigned short reg_field_index,
unsigned long value,
PHANTOM_SB_USE_HANDLE use_handle)
{
int bytes = 0;
int offset = 0;
unsigned char data_write = 0x00U;
unsigned char data_read = 0x00U;
unsigned long handle;
const PHANTOM_REGISTER_MAP* p_register_map;
/* Validation */
if (p_nim == 0) /* bad pointer */
{
return (False);
}
/* Initialization */
switch (use_handle)
{
case PHANTOM_USE_DEMOD_HANDLE:
handle = p_nim->demod_handle;
p_register_map = phantom_register_map;
break;
default:
return (False);
}
/* Verify that index passed points to the correct register record */
PHANTOM_DBG_VALIDATE_REG_IDX(p_register_map, reg_field_index);
/* Register read-only */
PHANTOM_DBG_VALIDATE_REG_RO (p_register_map, reg_field_index);
/* de-translate from variable to hardware bit positioned value and write to hardware */
switch (p_register_map[reg_field_index].reg_type)
{
case PHANTOM_REGT_BIT: /* 1 to 7 bit(s) wide */
case PHANTOM_REGT_BYTE: /* 1 byte wide */
{
unsigned char data_write = 0x00U;
unsigned char data_read = 0x00U;
if (p_register_map[reg_field_index].bit_count == 0x01) /* single bit */
{
if (value)
{
data_write = p_register_map[reg_field_index].p_hw_mask[0];
}
else
{
data_write = 0x00;
}
}
else /* Minimum 2 bits, max 8 bits */
{
unsigned long temp;
/* mask useful bits from raw, shift left (make range 0..2^bit_count) */
temp = value & (unsigned long)( (0x01UL << (unsigned long)(p_register_map[reg_field_index].bit_count) ) - 1UL );
temp = (temp << (p_register_map[reg_field_index].start_bit-(p_register_map[reg_field_index].bit_count-1)));
data_write = (unsigned char)temp;
}
/* clear io error return value */
p_nim->iostatus = 0UL;
/* Byte must be read, modified, written */
data_read = (*p_nim->SBRead)(handle,(unsigned char)(p_register_map[reg_field_index].address),&p_nim->iostatus);
/* Watch for special-case error, read error during write */
if (p_nim->iostatus != 0UL)
{
/* Hardware write error */
PHANTOM_DBG_SET_ERROR(PHANTOM_REG_HDWR_RD_WR_ERR);
return (False);
}
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