ct202.h

来自「QPSK Tuner details, for conexant chipset」· C头文件 代码 · 共 497 行 · 第 1/2 页

#ifndef _MERCURY_DEVICE_DRIVER_
#define _MERCURY_DEVICE_DRIVER_

//demod registers
#define	REVISION_REG	0x00
#define	SYSTEM_MODE_REG	0x01
#define	TS_CONTROL_REG_1	0x02
#define	TS_CONTROL_REG_2	0x03
#define	PIN_CONTROL_REG_1	0x04
#define	PIN_CONTROL_REG_2	0x05
#define	BYPASS_REG	0x06
#define	INTERRUPT_ENABLE_REG_0	0x07
#define	INTERRUPT_ENABLE_REG_1	0x08
#define	INTERRUPT_ENABLE_REG_2	0x09
#define	INTERRUPT_ENABLE_REG_3	0x0A
#define	INTERRUPT_STATUS_REG_0	0x0B
#define	INTERRUPT_STATUS_REG_1	0x0C
#define	INTERRUPT_STATUS_REG_2	0x0D
#define	INTERRUPT_STATUS_REG_3	0x0E
#define	LOCK_STATUS_REG_1	0x0F
#define	LOCK_STATUS_REG_2	0x10
#define	ACQ_STATUS_REG	0x11
#define	FADE_CONTROL_REG	0x12
#define	ACQ_CONTROL_REG_1	0x13
#define	ACQ_CONTROL_REG_2	0x14
#define	PLL_DIVISOR_REG	0x15
#define	COARSE_TUNE_REG	0x16
#define	FINE_TUNE_REG_L	0x17
#define	FINE_TUNE_REG_H	0x18
#define	TUNER_SERIAL_INTERFACE_CONTROL_REG	0x19
#define	TUNER_SERIAL_INTERFACE_DATA_REG_L	0x1A
#define	TUNER_SERIAL_INTERFACE_DATA_REG_H	0x1B

#define	DC_CORRECTOR_CONTROL_REG	0x20
#define	DC_CORRECTOR_IN_PHASE_OFFSET_REG	0x21
#define	DC_CORRECTOR_QUADRATURE_OFFSET_REG	0x22
#define	ANALOG_AGC_CONTROL_REG_1	0x23
#define	ANALOG_AGC_CONTROL_REG_2	0x24
#define	ANALOG_AGC_GAIN_REG_L	0x25
#define	ANALOG_AGC_GAIN_REG_H	0x26
#define	ANALOG_AGC_THRESHOLD_REG	0x27
#define	ANALOG_AGC_POWER_LEVEL_REG	0x28
#define	CFO_ESTIMATOR_CONTROL_REG_1	0x29
#define	CFO_ESTIMATOR_CONTROL_REG_2	0x2A
#define	CFO_ESTIMATOR_CONTROL_REG_3	0x2B
#define	CFO_ESTIMATOR_THRESHOLD_REG_1	0x2C
#define	CFO_ESTIMATOR_THRESHOLD_REG_2	0x2D
#define	CFO_ESTIMATOR_THRESHOLD_REG_3	0x2E
#define	CFO_ESTIMATOR_THRESHOLD_REG_4	0x2F
#define	CFO_ESTIMATOR_THRESHOLD_REG_5	0x30
#define	SYMBOL_RATE_ESTIMATE_REGISTER_L	 0x31 //CFO_ESTIMATOR_FAST_THRESHOLD_REG_1	0x31
#define	CFO_ESTIMATOR_FAST_THRESHOLD_REG_2	0x32
#define	CFO_ESTIMATOR_FAST_THRESHOLD_REG_3	0x33
#define	CFO_ESTIMATOR_STEP_REG_L	0x34
#define	CFO_ESTIMATOR_STEP_REG_H	0x35
#define	CFO_ESTIMATOR_OFFSET_REG_L	0x36
#define	CFO_ESTIMATOR_OFFSET_REG_H	0x37
#define	CFO_ERROR_REG_L	0x38
#define	CFO_ERROR_REG_H	0x39
#define	SYMBOL_RATE_ESTIMATOR_CONTROL_REG	0x3A
#define	SYMBOL_RATE_ESTIMATOR_THRESHOLD_REG_1	0x3B
#define	SYMBOL_RATE_ESTIMATOR_THRESHOLD_REG_2	0x3C
#define	SYMBOL_RATE_ESTIMATOR_THRESHOLD_REG_3	0x3D
#define	SYMBOL_RATE_ESTIMATOR_THRESHOLD_REG_4	0x3E
#define	SYMBOL_RATE_REG_L	0x3F
#define	SYMBOL_RATE_REG_M	0x40
#define	SYMBOL_RATE_REG_H	0x41
#define	SYMBOL_RATE_ESTIMATOR_MAXIMUM_REG	0x42
#define	SYMBOL_RATE_ESTIMATOR_MINIMUM_REG	0x43
#define	SYMBOL_LOOP_CONTROL_REG_1	0x44
#define	SYMBOL_LOOP_CONTROL_REG_2	0x45
#define	SYMBOL_LOOP_CONTROL_REG_3	0x46
#define	SYMBOL_LOOP_LOCK_THRESHOLD_REG_L	0x47
#define	SYMBOL_LOOP_LOCK_THRESHOLD_REG_H	0x48
#define	SYMBOL_LOOP_UNLOCK_THRESHOLD_REG_L	0x49
#define	SYMBOL_LOOP_UNLOCK_THRESHOLD_REG_H	0x4A
#define	SYMBOL_LOOP_SWEEP_MAXIMUM_REG	0x4B
#define	SYMBOL_LOOP_SWEEP_MINIMUM_REG	0x4C
#define	SYMBOL_LOOP_SWEEP_RATE_REG_L	0x4D
#define	SYMBOL_LOOP_SWEEP_RATE_REG_H	0x4E
#define	SYMBOL_LOOP_ACQ_PROPNL_COEFF_HIGH_BAUD_RATES_REG	0x4F
#define	SYMBOL_LOOP_ACQ_PROPNL_COEFF_LOW_BAUD_RATES_REG	0x50
#define	SYMBOL_LOOP_TRK_PROPNL_COEFF_HIGH_BAUD_RATES_REG	0x51
#define	SYMBOL_LOOP_TRK_PROPNL_COEFF_LOW_BAUD_RATES_REG	0x52
#define	SYMBOL_LOOP_ERROR_REG_L	0x53
#define	SYMBOL_LOOP_ERROR_REG_M	0x54
#define	SYMBOL_LOOP_ERROR_REG_H	0x55
#define	I_Q_IMBALANCE_CORRECTOR_CONTROL_REG	0x56
#define	I_Q_PHASE_COEFF_REG	0x57
#define	I_Q_GAIN_COEFF_REG	0x58
#define	CARRIER_LOOP_CONTROL_REG_1	0x59
#define	CARRIER_LOOP_CONTROL_REG_2	0x5A
#define	CARRIER_LOOP_LOCK_THRESHOLD_REG	0x5B
#define	CARRIER_LOOP_UNLOCK_THRESHOLD_REG	0x5C
#define	CARRIER_LOOP_SWEEP_MAXIMUM_REG_L	0x5D
#define	CARRIER_LOOP_SWEEP_MAXIMUM_REG_H	0x5E
#define	CARRIER_LOOP_SWEEP_MINIMUM_REG_L	0x5F
#define	CARRIER_LOOP_SWEEP_MINIMUM_REG_H	0x60
#define	CARRIER_LOOP_SWEEP_RATE_REG	0x61
#define	CARRIER_LOOP_ACQ_PROPNL_COEFF_HIGH_BAUD_RATES_REG	0x62
#define	CARRIER_LOOP_ACQ_PROPNL_COEFF_LOW_BAUD_RATES_REG	0x63
#define	CARRIER_LOOP_TRK_PROPNL_COEFF_HIGH_BAUD_RATES_REG	0x64
#define	CARRIER_LOOP_TRK_PROPNL_COEFF_LOW_BAUD_RATES_REG	0x65
#define	CARRIER_LOOP_ERROR_REG_L	0x66
#define	CARRIER_LOOP_ERROR_REG_M	0x67
#define	CARRIER_LOOP_ERROR_REG_H	0x68
#define	PHASE_TRK_LOOP_CONTROL_REG_1	0x69
#define	PHASE_TRK_LOOP_SCALED_PROPNL_COEFF_HIGH_BAUD_RATES_REG	0x6A
#define	PHASE_TRK_LOOP_SCALED_GAIN_COEFF_HIGH_BAUD_RATES_REG	0x6B
#define	PHASE_TRK_LOOP_SCALED_PROPNL_COEFF_LOW_BAUD_RATES_REG	0x6C
#define	PHASE_TRK_LOOP_SCALED_GAIN_COEFF_LOW_BAUD_RATES_REG	0x6D
#define	PHASE_TRK_LOOP_ERROR_REG_L	0x6E
#define	PHASE_TRK_LOOP_ERROR_REG_M	0x6F
#define	PHASE_TRK_LOOP_ERROR_REG_H	0x70
#define	EQUALIZER_CONTROL_REG_1	0x71
#define	EQUALIZER_CONTROL_REG_2	0x72
#define	EQUALIZER_CONTROL_REG_3	0x73
#define	EQUALIZER_COEFF_REG	0x74
#define	DIGITAL_AGC_1_CONTROL_REG	0x75
#define	DIGITAL_AGC_1_GAIN_REG_L	0x76
#define	DIGITAL_AGC_1_GAIN_REG_H	0x77
#define	DIGITAL_AGC_2_CONTROL_REG	0x78
#define	DIGITAL_AGC_2_THRESHOLD_REG	0x79
#define	DIGITAL_AGC_2_LEVEL_REG_L	0x7A
#define	DIGITAL_AGC_2_LEVEL_REG_H	0x7B
#define	C_N_ESTIMATOR_CONTROL_REG	0x7C
#define	C_N_ESTIMATOR_THRESHOLD_REG	0x7D
#define	C_N_ESTIMATOR_LEVEL_REG_L	0x7E
#define	C_N_ESTIMATOR_LEVEL_REG_H	0x7F

#define	BLIND_SCAN_CONTROL_REGISTER	0x80
#define	BLIND_SCAN_CONTROLLER_MIN_FREQUENCY_REGISTER_L	0x81
#define	BLIND_SCAN_CONTROLLER_MIN_FREQUENCY_REGISTER_M	0x82
#define	BLIND_SCAN_CONTROLLER_MIN_FREQUENCY_REGISTER_H	0x83
#define	BLIND_SCAN_CONTROLLER_MAX_FREQUENCY_REGISTER_L	0x84
#define	BLIND_SCAN_CONTROLLER_MAX_FREQUENCY_REGISTER_M	0x85
#define	BLIND_SCAN_CONTROLLER_MAX_FREQUENCY_REGISTER_H	0x86
#define	BLIND_SCAN_DIGITAL_MIXER_FREQUENCY_REGISTER_L	0x87
#define	BLIND_SCAN_DIGITAL_MIXER_FREQUENCY_REGISTER_H	0x88
#define	BLIND_SCAN_CONTROLLER_COARSE_FREQUENCY_DATA_REGISTER	0x89
#define	BLIND_SCAN_CONTROLLER_FINE_FREQUENCY_DATA_REGISTER_L	0x8A
#define	BLIND_SCAN_CONTROLLER_FINE_FREQUENCY_DATA_REGISTER_H	0x8B
#define	BLIND_SCAN_PLL_DIVISOR_REGISTER	0x8C

#define	LSA_CONTROL_REGISTER_1	0x8D
#define	SPECTRUM_TILT_CORRECTION_THRESHOLD_REGISTER	0x8F
#define	ONE_DB_BANDWIDTH_THRESHOLD_REGISTER	0x90
#define	TWO_DB_BANDWIDTH_THRESHOLD_REGISTER	0x91
#define	THREE_DB_BANDWIDTH_THRESHOLD_REGISTER	0x92
#define	INBAND_POWER_THRESHOLD_REGISTER	0x93
#define	REFERENCE_NOISE_LEVEL_MARGIN_THRESHOLD_REGISTER	0x94

#define	VITERBI_SEARCH_CONTROL_REG_1	0xA0
#define	VITERBI_SEARCH_CONTROL_REG_2	0xA1
#define	VITERBI_SEARCH_CONTROL_REG_3	0xA2
#define	VITERBI_SEARCH_STATUS_REG	0xA3
#define	VITERBI_RATE_1_2_LOCK_THRESHOLD_REG	0xA4
#define	VITERBI_RATE_2_3_LOCK_THRESHOLD_REG	0xA5
#define	VITERBI_RATE_3_4_LOCK_THRESHOLD_REG	0xA6
#define	VITERBI_RATE_5_6_LOCK_THRESHOLD_REG	0xA7
#define	VITERBI_RATE_6_7_LOCK_THRESHOLD_REG	0xA8
#define	VITERBI_RATE_7_8_LOCK_THRESHOLD_REG	0xA9
#define	VITERBI_UNLOCK_THRESHOLD_REG	0xAA
#define	VITERBI_BER_COUNT_REG_L	0xAB
#define	VITERBI_BER_COUNT_REG_H	0xAC
#define	FRAME_SYNCHRONIZER_CONTROL_REG_1	0xAD
#define	FRAME_SYNCHRONIZER_CONTROL_REG_2	0xAE
#define	FRAME_SYNCHRONIZER_STATUS_REG	0xAF
#define	REED_SOLOMON_CONTROL_REG	0xB0
#define	REED_SOLOMON_ERROR_COUNT_REG_L	0xB1
#define	REED_SOLOMON_ERROR_COUNT_REG_H	0xB2
#define	DESCRAMBLER_CONTROL_REG	0xB3
#define	AUX_DAC_CONTROL_REG	0xB4
#define	PRBS_CONTROL_REG	0xB5
		
#define	LNB_CONTROL_REG_1	0xC0
#define	LNB_CONTROL_REG_2	0xC1
#define	LNB_CONTROL_REG_3	0xC2
#define	LNB_CONTROL_REG_4	0xC3
#define	LNB_CONTROL_STATUS_REG	0xC4
#define	LNB_FIFO_REGS_0	0xC5
#define	LNB_FIFO_REGS_1	0xC6
#define	LNB_FIFO_REGS_2	0xC7
#define	LNB_FIFO_REGS_3	0xC8
#define	LNB_FIFO_REGS_4	0xC9
#define	LNB_FIFO_REGS_5	0xCA
#define	LNB_SUPPLY_CONTROL_REG_1	0xCB
#define	LNB_SUPPLY_CONTROL_REG_2	0xCC
#define	LNB_SUPPLY_CONTROL_REG_3	0xCD
#define	LNB_SUPPLY_CONTROL_REG_4	0xCE
#define	LNB_SUPPLY_STATUS_REG	0xCF
#define	LNB_TEST_REG_1	0xD0
#define	LNB_TEST_REG_2	0xD1
#define	LNB_TEST_REG_3	0xD2
#define	LNB_TEST_REG_4	0xD3
#define	LNB_TEST_REG_5	0xD4
#define	LNB_TEST_REG_6	0xD5
#define	LNB_TEST_REG_7	0xD6

#define	LNB_TEST_REG_8	0xD7
		
#define	AAF_CONTROL_REG_1	0xE0
#define	AAF_CONTROL_REG_2	0xE1
#define	TUNER_CONTROL_REGISTER	0xE2
#define	PLL_CONTROL_REG1	0xE3
#define	PLL_CONTROL_REG2	0xE4
#define	PLL_CONTROL_REG3	0xE5
#define	PLL_CONTROL_REG4	0xE6
#define	PLL_CONTROL_REG5	0xE7
#define	PLL_CONTROL_REG6	0xE8
#define	RCAL_STATUS_REG	0xE9
#define	VREG_CONTROL_REG	0xEA
#define	BIST_CONTROL_REG	0xEB
#define	CALIBRATION_CONTROL_REG	0xEC
#define	ADC_CONTROL_REG	0xED
#define	TUNER_SERIAL_INTERFACE_DEBUG_REG	0xEE
#define	FILTER_CAL_CONTROL_REG	0xEF
#define	MIXER_CAL_CONTROL_REG	0xF0
#define	VCO_CAL_CONTROL_REG_1	0xF1
#define	VCO_CAL_CONTROL_REG_2	0xF2
#define	SPARE_WRITE_REG_1	0xF3
#define	SPARE_WRITE_REG_2	0xF4
#define	SPARE_WRITE_REG_3	0xF5
#define	SPARE_WRITE_REG_4	0xF6
#define	SPARE_READ_REG_1	0xF7
#define	SPARE_READ_REG_2	0xF8
#define	SPARE_READ_REG_3	0xF9
#define	SPARE_READ_REG_4	0xFA

#define	MISC_MODE_CONTROL_REG	0xFE

//********************************************************************************
//DEFINITIONS
//********************************************************************************
#define MAX_MERCURY_REGS	0x100

#define TUNER_I2C_ADDRESS	0xD0

#define ALLOWABLE_FS_COUNT 10

#define TUNER_FREQ_LOW_LIM_KHZ	            940000L	/* Low frequency limit in kHz */
#define TUNER_FREQ_HIGH_LIM_KHZ	            2160000L/* High frequency limit in kHz */

#define TUNER_NORMAL_SCAN_FREQ_STEP_KHZ     3000    /* 2M ,original 2000*//* 20000 kHz scan frequency step */
#define TUNER_NORMAL_SCAN_FREQ_LOW_LIM_KHZ	940000L	/* Low frequency limit in kHz */
#define TUNER_NORMAL_SCAN_FREQ_HIGH_LIM_KHZ 1600000L/* High frequency limit in kHz */