📄 cx24143drv.c
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/****************************************************************************
* Conexant QPSK driver (internal mode) *
* Copyright ? Shenzhen Coship Electronics Co.，LTD. *
* All rights reserved. *
* Author: Sunfugong *
* Create Date: 2005/7/20 *
* Update: 2005/8/01 Sunfugong *
*****************************************************************************/
#include "CSHDI_typedef.h"
#include "cx24143_all.h"
#include "CSQpskCFG.h"
#include "cs_qpsk.h"
#include "cx24143drv.h"
#include "cs_os.h"
#include "CS_I2c.h"
#include "Allcommand.h"
#include "cs_frnpublic.h"
#include "cs_gpio.h"
#include "CS_assert.h"
//#include "cobra_enum.h"
typedef volatile ULONG *ULPREG;
typedef struct
{
ULONG frequency;
ULONG symbol_rate;
NIM_SATELLITE_POLARISATION polarisation;
NIM_FEC_RATE fec;
SHORT orbital_position;
NIM_SATELLITE_SPECTRUM spectrum;
} NIM_SATELLITE_TUNE;
typedef struct
{
DEMOD_NIM_TYPE type;
NIM_SATELLITE_TUNE nim_satellite_tune;
} TUNING_SPEC;
typedef struct
{
DEMOD_NIM_TYPE type;
UCHAR signal_quality;
UCHAR signal_strength;
} SIGNAL_STATS;
// Macro define start
#define CNT_TIMES 10
#define MAXIMUM_NUMBER_UNITS (2)
#define BER_WINDOW_SIZE (255)
#define CONNECTED (3)
/* These definitions are related to interrupt operation. */
#define COBRA_NO_INTERRUPTS (0)
#define COBRA_CONNECTING_INTERRUPTS (INTR_ACQ_SYNC)
#define USE_LNB_22KHZ_TONE
#define DEMOD_NIM_SATELLITE 1
/*
* Access macros used to get, set/clear bits within a hardware register.
* These macros *do not* perform any automatic shifting of bits and are
* meant to be used with bit definitions which include their encoded bit
* position within the register definition (e.g. an enable bit).
*/
#define CS_CNXT_REGMAP_GET(reg,mask) (*(ULPREG)(reg) & (mask))
#define CS_CNXT_REGMAP_SET(reg,mask,val) (*(ULPREG)(reg)) = \
((*(ULPREG)(reg) & ~(mask)) | ((val) & (mask)))
//#define PIO_LNB_ENABLE (107+0x00000000+0x00000000+0x80000000)
#define PIO_LNB_ENABLE (107)
#define CS_DMD_BASE 0x304E0000
#define CS_DEMOD_REG_TO_ASX_ADDR(x) (((x)*4) + CS_DMD_BASE)
#define CS_PLL_BASE 0x30440000
#define CS_PLL_TEST_REG (CS_PLL_BASE + 0x70)
#define CS_PLL_TEST_DEMOD_DISABLE_MASK 0x00080000
#define CS_PLL_TEST_DEMOD_DISABLED (1UL<<19)
#define CS_PLL_PAD_FAST_CTRL_REG (CS_PLL_BASE + 0x74)
#define CS_PLL_FAST_CTRL_DEMOD_CONNECT_SEL_MASK 0x00040000
#define CS_PLL_FAST_CTRL_DEMOD_CONNECT_ASX (0UL<<18)
#define CS_PLL_FAST_CTRL_DEMOD_I2C_SEL_MASK 0x00030000
#define CS_PLL_FAST_CTRL_DEMOD_I2C_BUS_0 (1UL<<16)
#define CS_I2C_ADDR_CAMARO 0xAA
#define CS_PLL_FAST_CTRL_DEMOD_CONNECT_I2C (1UL<<18)
#define CS_I2C_BUS_CAMARO 1
static int demod_handle[MAXIMUM_NUMBER_UNITS] = { 0, 0 };
static NIM NIMs[MAXIMUM_NUMBER_UNITS];
static MPEG_OUT MPEG;
static HCSHANDLE hCX2414XI2C[MAXIMUM_NUMBER_UNITS]={0,0};
/* This are the default code rates to try when connecting in auto fec mode */
static unsigned int viterbicoderates = CODERATE_2DIV3 | CODERATE_3DIV4 | CODERATE_4DIV5 | CODERATE_5DIV6 | CODERATE_6DIV7 | CODERATE_7DIV8;
static int demod_initfalg=0;
static TUNING_SPEC Stuning;
static BYTE g_ucCx2414xTunerType[MAXIMUM_NUMBER_UNITS];
static VOID CSSleep_ex(DWORD dwMilliSeconds)
{
task_time_sleep(dwMilliSeconds);
}
static CODERATE convert_fec_in( NIM_FEC_RATE fec );
static SPECINV convert_spectrum_in( NIM_SATELLITE_SPECTRUM spectrum );
static CSQPSK_Error_t CX2414X_get_signal_stats( ULONG unit, SIGNAL_STATS *signal_stats ,BOOL strength_flag);
static CSQPSK_Error_t CX2414X_demod_init(CSHDITunerIndex bTunerIndex );
static CSQPSK_Error_t CX2414X_lnb_init( BOOL enable );
extern int g_nFrequencyOffset[MAXIMUM_NUMBER_UNITS];
extern CSQPSK_Error_t CSQPSKSleep(CSHDITunerIndex bTunerIndex,DWORD dwSleepTime);
// variable end
/*****************************************************************************/
/* FUNCTION: CX2414x_I2C_Handle_Init */
/* PARAMETERS: bTunerIndex - tuner index.
*/
/* DESCRIPTION: Handle by I2C. */
/* RETURNS: suceess or failure */
/*****************************************************************************/
static CSQPSK_Error_t CX2414x_I2C_Handle_Init(CSHDITunerIndex bTunerIndex)
{
CSQPSK_Error_t ErrorCode=CSQPSK_SUCCESS;
hCX2414XI2C[bTunerIndex] = 0;
ErrorCode = CSI2COpen(bTunerIndex,CS_I2C_ADDR_CAMARO,&hCX2414XI2C[bTunerIndex]);
if ( ErrorCode != CSI2C_SUCCESS)
{
return CSQPSK_I2C_ERROR;
}
// chip setup, don't remove it when use iic.
CS_CNXT_REGMAP_SET( CS_PLL_PAD_FAST_CTRL_REG, CS_PLL_FAST_CTRL_DEMOD_I2C_SEL_MASK, CS_PLL_FAST_CTRL_DEMOD_I2C_BUS_0 );
return CSQPSK_SUCCESS;
}
static BOOL RegUseI2C(UCHAR reg_addr)
{
if ( reg_addr == 0 || reg_addr == 0x33 || reg_addr == 0x23|| reg_addr == 0x34 ||
reg_addr == 0x39 || reg_addr == 0x3a || reg_addr == 0x3b ||
reg_addr == 0x43 || reg_addr == 0x44 || reg_addr == 0x3c )
return TRUE;
else
return FALSE;
}
/*****************************************************************************/
/* FUNCTION: I2CWriteReg */
/* PARAMETERS: bTunerIndex - tuner index
byIndex - the tuner register index / register addres.
byRegData -data to be writed.
*/
/* DESCRIPTION: register write by I2C. */
/* RETURNS: suceess or failure */
/*****************************************************************************/
static CSQPSK_Error_t I2CWriteReg(CSHDITunerIndex bTunerIndex, BYTE byIndex, BYTE byRegData) //, IICBUS bus)
{
CSQPSK_Error_t err=CSQPSK_SUCCESS;
BYTE bBuffer[2];
bBuffer[0]=byIndex;
bBuffer[1]=byRegData;
if ( CSI2CRequestBus_inner(bTunerIndex, CSHDI_TIMEOUT_INFINITY) == CSI2C_SUCCESS )
{
if(CSI2CWriteWithStop(hCX2414XI2C[bTunerIndex], bBuffer, 2 )!= CSI2C_SUCCESS )
err= CSQPSK_I2C_ERROR;
//CSTRACE(INFO_LEVEL,"[HDI][CS_QPSK] CSI2CWriteWithStop ERROR=%d \n",tI2cError);
CSI2CReleaseBus_inner(bTunerIndex);
}
else
{
err= CSQPSK_I2C_ERROR;
}
/*
if ( err!=CSQPSK_SUCCESS )
{
CSTRACE(QPSK_DEBUG_LEVEL,"[I2CWriteReg]I2C ERROR!!!%%%%%%%%%%");
}
*/
return err;
}
/*****************************************************************************/
/* FUNCTION: I2CReadReg */
/* PARAMETERS: bTunerIndex - tuner index
byIndex - the tuner register index / register addres.
byRegData -data was read.
*/
/* DESCRIPTION: register read by I2C. */
/* RETURNS: suceess or failure */
/*****************************************************************************/
static CSQPSK_Error_t I2CReadReg(CSHDITunerIndex bTunerIndex, BYTE byIndex, BYTE *byRegData) //, IICBUS bus)
{
CSQPSK_Error_t err=CSQPSK_SUCCESS;
if ( CSI2CRequestBus_inner(bTunerIndex, CSHDI_TIMEOUT_INFINITY) == CSI2C_SUCCESS )
{
if(CSI2CWriteWithoutStop(hCX2414XI2C[bTunerIndex], &byIndex, 1 ) != CSI2C_SUCCESS )
err= CSQPSK_I2C_ERROR;
if(CSI2CReadWithStop(hCX2414XI2C[bTunerIndex], byRegData, 1 )!= CSI2C_SUCCESS )
err= CSQPSK_I2C_ERROR;
CSI2CReleaseBus_inner(bTunerIndex);
}
else
{
err= CSQPSK_I2C_ERROR;
}
/*
if ( err!=CSQPSK_SUCCESS )
{
CSTRACE(QPSK_DEBUG_LEVEL,"[I2CReadReg]I2C ERROR!!!%%%%%%%%%%");
}
*/
return err;
}
// same as SBRead()
/*****************************************************************************/
/* FUNCTION: CX2414XReadReg */
/* PARAMETERS: bTunerIndex - tuner index
byIndex - the tuner register index / register addres.
byRegData -data was read.
*/
/* DESCRIPTION: register read by uC. */
/* RETURNS: suceess or failure */
/*****************************************************************************/
CSQPSK_Error_t CX2414XReadReg(CSHDITunerIndex bTunerIndex, UCHAR reg_addr, UCHAR *data )
{
UCHAR reg_value = 0;
if(data==NULL)
{
CSASSERT(data);
return CSQPSK_FAILURE;
}
/* perform the read */
if (RegUseI2C(reg_addr)==TRUE)
{
CS_CNXT_REGMAP_SET( CS_PLL_PAD_FAST_CTRL_REG, CS_PLL_FAST_CTRL_DEMOD_CONNECT_SEL_MASK,
CS_PLL_FAST_CTRL_DEMOD_CONNECT_I2C );
if(I2CReadReg(bTunerIndex, reg_addr, ®_value)!=CSQPSK_SUCCESS)
{
CSTRACE(ERROR_LEVEL,"[HDI][CS_QPSK]CX2414XReadReg error \n");
CS_CNXT_REGMAP_SET( CS_PLL_PAD_FAST_CTRL_REG, CS_PLL_FAST_CTRL_DEMOD_CONNECT_SEL_MASK,
CS_PLL_FAST_CTRL_DEMOD_CONNECT_ASX );
return CSQPSK_FAILURE;
}
CS_CNXT_REGMAP_SET( CS_PLL_PAD_FAST_CTRL_REG, CS_PLL_FAST_CTRL_DEMOD_CONNECT_SEL_MASK,
CS_PLL_FAST_CTRL_DEMOD_CONNECT_ASX );
}
else
{
reg_value = *(ULPREG)CS_DEMOD_REG_TO_ASX_ADDR(reg_addr);
}
*data=reg_value;
return CSQPSK_SUCCESS;
}
// same as SBWrite()
/*****************************************************************************/
/* FUNCTION: CX2414XWriteReg */
/* PARAMETERS: bTunerIndex - tuner index
byIndex - the tuner register index / register addres.
byRegData -data to be writed.
*/
/* DESCRIPTION: register write by uC. */
/* RETURNS: suceess or failure */
/*****************************************************************************/
CSQPSK_Error_t CX2414XWriteReg(CSHDITunerIndex bTunerIndex, UCHAR reg_addr, UCHAR data )
{
/* perform the write */
if (RegUseI2C(reg_addr)==TRUE)
{
CS_CNXT_REGMAP_SET( CS_PLL_PAD_FAST_CTRL_REG, CS_PLL_FAST_CTRL_DEMOD_CONNECT_SEL_MASK,
CS_PLL_FAST_CTRL_DEMOD_CONNECT_I2C );
if(I2CWriteReg(bTunerIndex, reg_addr, data)!=CSQPSK_SUCCESS)
{
CSTRACE(ERROR_LEVEL,"[HDI][CS_QPSK]CX2414XWriteReg error \n");
CS_CNXT_REGMAP_SET( CS_PLL_PAD_FAST_CTRL_REG, CS_PLL_FAST_CTRL_DEMOD_CONNECT_SEL_MASK,
CS_PLL_FAST_CTRL_DEMOD_CONNECT_ASX );
return CSQPSK_FAILURE;
}
CS_CNXT_REGMAP_SET( CS_PLL_PAD_FAST_CTRL_REG, CS_PLL_FAST_CTRL_DEMOD_CONNECT_SEL_MASK,
CS_PLL_FAST_CTRL_DEMOD_CONNECT_ASX );
}
else
{
*(ULPREG)CS_DEMOD_REG_TO_ASX_ADDR(reg_addr) = data;
}
return CSQPSK_SUCCESS;
}
/*****************************************************************************/
/* FUNCTION: SBWrite */
/* */
/* PARAMETERS: demod_handle - handle of demod for write request (San Diego */
/* code handle, not multi-instance demod handle). */
/* reg_addr - the register offset to be written. */
/* data - the data value to be written. */
/* status - pointer to status value filled in at completion */
/* (0 for success, non-0 for failure). */
/* */
/* DESCRIPTION: This function writes the specified value to the specified */
/* register offset of the specified demod unit. */
/* */
/* RETURNS: Nothing. */
/* */
/* CONTEXT: Must be called from non-interrupt context. */
/* */
/*****************************************************************************/
static void SBWrite( ULONG demod_handle, UCHAR reg_addr, UCHAR data, ULONG *status )
{
if ( 0 == status )
{
CSASSERT(status);
return;
}
/* perform the write */
if(CX2414XWriteReg(0, reg_addr, data )!=CSQPSK_SUCCESS)
*status=1;
else
*status=0;
}
/*****************************************************************************/
/* FUNCTION: SBRead */
/* */
/* PARAMETERS: demod_handle - handle of demod for read request (San Diego */
/* code handle, not multi-instance demod handle). */
/* reg_addr - the register offset to be read. */
/* status - pointer to status value filled in at completion */
/* (0 for success, non-0 for failure). */
/* */
/* DESCRIPTION: This function reads from the specified register offset of */
/* the specified demod unit and returns the value read. */
/* */
/* RETURNS: The value read from the device. */
/* */
/* CONTEXT: Must be called from non-interrupt context. */
/* */
/*****************************************************************************/
static UCHAR SBRead( ULONG demod_handle, UCHAR reg_addr, ULONG *status )
{
UCHAR reg_value = 0;
UCHAR data[4];
if ( 0 == status )
{
CSASSERT(status);
return 0;
}
if( CX2414XReadReg(0, reg_addr, data )!=CSQPSK_SUCCESS)
*status=1;
else
*status=0;
if(*status==0)
reg_value= data[0];
#if 0
/* perform the read */
if ( reg_addr == 0 || reg_addr == 0x33 || reg_addr == 0x34 ||
reg_addr == 0x39 || reg_addr == 0x3a || reg_addr == 0x3b ||
reg_addr == 0x43 || reg_addr == 0x44 || reg_addr == 0x3c
)
{
/* get serial bus address from demod handle */
serial_bus_addr = (UCHAR)(demod_handle & 0x000000FF);
/* determine DEMOD_A or DEMOD_B register address offset. */
if ( (demod_handle >> 16) != 0 )
reg_addr |= 0x80; /* add 128 to register address. */
CS_CNXT_REGMAP_SET( CS_PLL_PAD_FAST_CTRL_REG, CS_PLL_FAST_CTRL_DEMOD_CONNECT_SEL_MASK,
CS_PLL_FAST_CTRL_DEMOD_CONNECT_I2C );
#if 0
*status = !iicReadIndexedReg( serial_bus_addr, reg_addr, ®_value, CS_I2C_BUS_CAMARO );
#else
if(I2CReadReg(0, reg_addr, ®_value)!=CSQPSK_SUCCESS)
{
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