phantom_cmd.h

QPSK Tuner details, for conexant chipset.

#define PHANTOM_SC_F3_PLL_MAIN_CLK_DIV                  (PHANTOM_SC_F2_PLL_SDIV + 0x0001)	         /* address 0xF3 [2:0], W */
#define PHANTOM_SC_F3_PLL_SMOOTH_CLK_DIV                (PHANTOM_SC_F3_PLL_MAIN_CLK_DIV + 0x0001)	 /* address 0xF3 [6:4], W */

/* Tuner repeater, 8051 clock divider */
#define PHANTOM_SC_F0_RESET_CNTL                        (PHANTOM_SC_F3_PLL_SMOOTH_CLK_DIV + 0x0001)	 /* address 0xF0 [7:0], W */

#define PHANTOM_SC_F0_8051_MODULE_RESET                 (PHANTOM_SC_F0_RESET_CNTL + 0x0001)	         /* address 0xF0 [1], W */
#define PHANTOM_SC_F0_8051_SW_RESET				        (PHANTOM_SC_F0_8051_MODULE_RESET + 0x0001)   /* address 0xF0 [0], W */

#define PHANTOM_SC_F0_8051_CLK_DIV						(PHANTOM_SC_F0_8051_SW_RESET + 0x0001)       /* address 0xF0 [1:0], W */

#define PHANTOM_SC_EA_CLOCK_CONTROL                     (PHANTOM_SC_F0_8051_CLK_DIV + 0x0001)        /* address 0xEA [7:0], RW */

/* Board version */
#define PHANTOM_SC_E8_BOARD_VERSION                     (PHANTOM_SC_EA_CLOCK_CONTROL + 0x0001)       /* address 0xE8[4:3] */

#define PHANTOM_SC_E3_CLK_DIV /* need a better name*/   (PHANTOM_SC_E8_BOARD_VERSION + 0x0001)       /* address 0xE3[1:0] */

/* Demod's ref_clk divider */
#define PHANTOM_SC_E5_REF_CLK_DIV                       (PHANTOM_SC_E3_CLK_DIV + 0x0001)             /* address 0xE5[6] */

/* ADC Powerdown */
#define PHANTOM_SC_E1_ADC_PDN                           (PHANTOM_SC_E5_REF_CLK_DIV + 0x0001)         /* address 0xE1[1] */

/* DiSEqC ADC enable */
#define PHANTOM_SC_E0_DISEQC_ADC_ENABLE                 (PHANTOM_SC_E1_ADC_PDN + 0x0001)             /* address 0xE0[3] */
/* PLL disable */
#define PHANTOM_SC_E0_DISABLE_PLL                       (PHANTOM_SC_E0_DISEQC_ADC_ENABLE + 0x0001)   /* address 0xE0[0] */

/* === Page0 bit-fields (read-only) === */
/* SW Version */
#define PHANTOM_P0_96_SW_VERSION						(PHANTOM_SC_E0_DISABLE_PLL + 0x0001)	     /* address 0x96[7:0] */

/* Channel parameters */
#define PHANTOM_P0_97_TUNER_FREQ_KHZ                    (PHANTOM_P0_96_SW_VERSION + 0x0001)          /* address 0x97[23:0] */
#define PHANTOM_P0_9C_SPECINV                           (PHANTOM_P0_97_TUNER_FREQ_KHZ + 0x0001)      /* address 0x9C[6]    */
#define PHANTOM_P0_9C_ACTUAL_VITCODERATE                (PHANTOM_P0_9C_SPECINV + 0x0001)             /* address 0x9C[5:0]  */

/* Analog AGC */
#define PHANTOM_P0_9D_ANALOG_AGC_MSBITS                 (PHANTOM_P0_9C_ACTUAL_VITCODERATE + 0x0001)  /* address 0x9D[7:6] */
#define PHANTOM_P0_9E_ANALOG_AGC_LSBITS                 (PHANTOM_P0_9D_ANALOG_AGC_MSBITS + 0x0001)   /* address 0x9E[7:0] */

/* Frequency offset */
#define PHANTOM_P0_9F_FREQ_OFFSET                       (PHANTOM_P0_9E_ANALOG_AGC_LSBITS + 0x0001)   /* address 0x9F[15:0]*/

/* Symbol rate offset */
#define PHANTOM_P0_A1_SYMBRATE_OFFSET                   (PHANTOM_P0_9F_FREQ_OFFSET + 0x0001)         /* address 0xA1[15:0]*/

/* Lock indicators */
#define PHANTOM_P0_9D_LOCK_STATUS                       (PHANTOM_P0_A1_SYMBRATE_OFFSET + 0x0001)     /* address 0x9D[4:0] */
#define PHANTOM_P0_9D_PLL_LOCK                          (PHANTOM_P0_9D_LOCK_STATUS + 0x0001)         /* address 0x9D[0]   */
#define PHANTOM_P0_9D_DEMOD_SYNC_LOCK					(PHANTOM_P0_9D_PLL_LOCK + 0x0001)	         /* address 0x9D[1]   */
#define PHANTOM_P0_9D_LDPC_LOCK						    (PHANTOM_P0_9D_DEMOD_SYNC_LOCK + 0x0001)	 /* address 0x9D[2]   */
#define PHANTOM_P0_9D_VITERBI_LOCK					    (PHANTOM_P0_9D_LDPC_LOCK + 0x0001)	         /* address 0x9D[2]   */
#define PHANTOM_P0_9D_BCH_LOCK						    (PHANTOM_P0_9D_VITERBI_LOCK + 0x0001)	     /* address 0x9D[3]   */
#define PHANTOM_P0_9D_RS_LOCK						    (PHANTOM_P0_9D_BCH_LOCK + 0x0001)	         /* address 0x9D[3]   */
#define PHANTOM_P0_9D_LP_LOCK						    (PHANTOM_P0_9D_RS_LOCK + 0x0001)	         /* address 0x9D[4]   */
#define PHANTOM_P0_9D_TUNER_HANDSHAKE				    (PHANTOM_P0_9D_LP_LOCK + 0x0001)	         /* address 0x9D[5]   */

/* Interrupts */
#define PHANTOM_P0_BA_INTR_ENABLE					    (PHANTOM_P0_9D_TUNER_HANDSHAKE + 0x0001)	 /* address 0xB8[5:0] */
#define PHANTOM_P0_BB_INTR_PENDING					    (PHANTOM_P0_BA_INTR_ENABLE + 0x0001)	     /* address 0xB9[5:0] */

/* LNB */
#define PHANTOM_P0_BC_LNB_RX_MSG_LENGTH                 (PHANTOM_P0_BB_INTR_PENDING + 0x0001)          /* address 0xBC[2:0] */
#define PHANTOM_P0_BC_LNBDC_LEVEL                       (PHANTOM_P0_BC_LNB_RX_MSG_LENGTH + 0x0001)     /* address 0xBC[3] */
#define PHANTOM_P0_BC_LNB_TX_READY                      (PHANTOM_P0_BC_LNBDC_LEVEL + 0x0001)           /* address 0xBC[5] */
#define PHANTOM_P0_BC_LNB_RX_READY                      (PHANTOM_P0_BC_LNB_TX_READY + 0x0001)          /* address 0xBC[6] */
#define PHANTOM_P0_BC_LNB_TONE                          (PHANTOM_P0_BC_LNB_RX_READY + 0x0001)          /* address 0xBC[7] */

#define PHANTOM_P0_BD_LNB_RX_ERROR                      (PHANTOM_P0_BC_LNB_TONE + 0x0001)              /* address 0xBD[7:0] */

#define PHANTOM_P0_BE_LNB_REPLY_BYTE0                   (PHANTOM_P0_BD_LNB_RX_ERROR + 0x0001)          /* address 0xBE[7:0] */
#define PHANTOM_P0_BF_LNB_REPLY_BYTE1                   (PHANTOM_P0_BE_LNB_REPLY_BYTE0 + 0x0001)       /* address 0xBF[7:0] */
#define PHANTOM_P0_C0_LNB_REPLY_BYTE2                   (PHANTOM_P0_BF_LNB_REPLY_BYTE1 + 0x0001)       /* address 0xC0[7:0] */
#define PHANTOM_P0_C1_LNB_REPLY_BYTE3                   (PHANTOM_P0_C0_LNB_REPLY_BYTE2 + 0x0001)       /* address 0xC1[7:0] */
#define PHANTOM_P0_C2_LNB_REPLY_BYTE4                   (PHANTOM_P0_C1_LNB_REPLY_BYTE3 + 0x0001)       /* address 0xC2[7:0] */
#define PHANTOM_P0_C3_LNB_REPLY_BYTE5                   (PHANTOM_P0_C2_LNB_REPLY_BYTE4 + 0x0001)       /* address 0xC3[7:0] */
#define PHANTOM_P0_C4_LNB_REPLY_BYTE6                   (PHANTOM_P0_C3_LNB_REPLY_BYTE5 + 0x0001)       /* address 0xC4[7:0] */    
#define PHANTOM_P0_C5_LNB_REPLY_BYTE7                   (PHANTOM_P0_C4_LNB_REPLY_BYTE6 + 0x0001)       /* address 0xC5[7:0] */

#define PHANTOM_P0_A3_ESNO_ESTIMATION_MSB               (PHANTOM_P0_C5_LNB_REPLY_BYTE7 + 0x0001)       /* address 0xA3[7:0] */

/* Error rate measurement */
#define PHANTOM_P0_C6_CORR_BIT_ERR_COUNT                (PHANTOM_P0_A3_ESNO_ESTIMATION_MSB + 0x0001)   /* 0xC6[31:0]  */
#define PHANTOM_P0_CA_UNCORR_FRAME_ERR_COUNT            (PHANTOM_P0_C6_CORR_BIT_ERR_COUNT + 0x0001)    /* 0xCA[15:0]  */
#define PHANTOM_P0_CC_MEASUREMENT_COUNTER               (PHANTOM_P0_CA_UNCORR_FRAME_ERR_COUNT + 0x0001)/* 0xCC[7:0]   */
#define PHANTOM_P0_CD_CRC_FRAME_ERR_COUNT               (PHANTOM_P0_CC_MEASUREMENT_COUNTER + 0x0001)   /* 0xCD[15:0]  */
#define PHANTOM_P0_CF_CRC_MEASUREMENT_COUNTER           (PHANTOM_P0_CD_CRC_FRAME_ERR_COUNT + 0x0001)   /* 0xCF[7:0]   */

#define PHANTOM_P0_DB_BER_WIN_ADJUST                    (PHANTOM_P0_CF_CRC_MEASUREMENT_COUNTER + 0x0001)   /* 0xDB[15:0]   */ 
#define PHANTOM_P0_DD_CRC_WIN_ADJUST                    (PHANTOM_P0_DB_BER_WIN_ADJUST + 0x0001)   /* 0xDD[15:0]   */ 
#define PHANTOM_P0_D0_TUNER_ERR_CODE                    (PHANTOM_P0_DD_CRC_WIN_ADJUST + 0x0001)   /* 0xD0[7:0]   */
#define PHANTOM_P0_D1_BIN_CYCLES_COUNTER                (PHANTOM_P0_D0_TUNER_ERR_CODE + 0x0001)   /* 0xD1[7:0]   */
#define PHANTOM_P0_D5_ESNO_ESTIMATION_LSB               (PHANTOM_P0_D1_BIN_CYCLES_COUNTER + 0x0001)   /* address 0xA3[7:0] */

#define PHANTOM_P0_D6_LNB_REPLY_PARITY                  (PHANTOM_P0_D5_ESNO_ESTIMATION_LSB + 0x0001)   /* address 0xD6[7:0] */

#define PHANTOM_P0_D7_ERR_CORR                          (PHANTOM_P0_D6_LNB_REPLY_PARITY + 0x0001)      /* address 0xD7[0] */
        
/* Acquisition time */
#define PHANTOM_P0_D8_ACQUISITION_TIME_COUNTER          (PHANTOM_P0_D7_ERR_CORR + 0x0001)              /* 0xD8[15:0] for now */

#define PHANTOM_P0_DA_ESTIMATED_INPUT_POWER             (PHANTOM_P0_D8_ACQUISITION_TIME_COUNTER + 0x0001) /* 0xDA[7:0]*/

/* End of bit-fields listing */


/*******************************************************************************************
 * Register access level
 *******************************************************************************************/
typedef enum _phantom_reg_access_level
{
    PHANTOM_REG_RW=1,            /* register is readable and writable */
    PHANTOM_REG_RO=2,            /* register is read-only  */
    PHANTOM_REG_WO=4,            /* register is write-only */
    PHANTOM_REG_RESERVED=0       /* register is reserved or not accessible */
} PHANTOM_REG_ACCESS_LEVEL;


/*******************************************************************************************
 * Register map type 
 *******************************************************************************************/
typedef enum _phantom_reg_type
{  
    PHANTOM_REGT_BIT=1,    /* bit-field */
    PHANTOM_REGT_BYTE=2,   /* byte-wide register */
    PHANTOM_REGT_MBYTE=4,  /* multiple bytes (found in Page0:RO) wide register */
    PHANTOM_REGT_UNKNOWN=0
} PHANTOM_REG_TYPE;


/*******************************************************************************************
 * PHANTOM_LLF section 
 *******************************************************************************************/
typedef enum _PHANTOM_llf_section
{  
    PHANTOM_LLF_SECTION_UNKNOWN=0,  /* unknown section */
    PHANTOM_LLF_SECTION_LOWER=1,  /* lower 32-bytes section */
    PHANTOM_LLF_SECTION_UPPER=2   /* upper 32-bytes section */
} PHANTOM_LLF_SECTION;
/* -- End: command Interface related enumerations -- */
/* ----------------------------------------------------------------------------------------*/

/*******************************************************************************************
 * Serial bus handle selction.
 *******************************************************************************************/
typedef enum _PHANTOM_use_handle
{  
	PHANTOM_USE_DEMOD_HANDLE = 1,
    PHANTOM_USE_VIPER_HANDLE = 1,
    PHANTOM_USE_HANDLE_UNKNOWN=0
} PHANTOM_SB_USE_HANDLE;

/* -- Begin: command Interface related structures -- */
/*******************************************************************************************
 * Register Control structure
 *******************************************************************************************/
typedef struct _PHANTOM_register_map      
{                     
    unsigned short            bit_field;    /* bit-field, byte, multi-byte(start) index */      
    unsigned char             address;      /* SB register address in special control/Page0 */
    unsigned char             start_bit;    /* Start bit position  */
    unsigned char             bit_count;    /* Length of bit field */
    PHANTOM_REG_ACCESS_LEVEL  access_level; /* Indicates register access: RW/RO/WO */
    PHANTOM_REG_TYPE          reg_type;     /* Type of data held: bit-field, byte, multi-byte */
    char*                     p_hw_mask;    /* Holds hardware mask string */
}PHANTOM_REGISTER_MAP;


/**********************************************************************************
 * PHANTOM_LLF Structure
 **********************************************************************************/
typedef struct _PHANTOM_llf
{
    unsigned char op_code;                /* PHANTOM_LLF OpCode */
    unsigned char data[PHANTOM_MAX_LLF_ARG_SIZE]; /* write or/and return upto PHANTOM_MAX_LLF_ARG_SIZE bytes */
    unsigned char send_data_length;       /* Number of LLF arguments */
    unsigned char received_data_length;   /* Number of return arguments */
    PHANTOM_LLF_SECTION   send_to;                /* issue this LLF to lower or upper section */
} PHANTOM_LLF;


/*******************************************************************************************************
 * External reference to Demod's Register map in phantom_cmd.c 
 *******************************************************************************************************/
extern const PHANTOM_REGISTER_MAP phantom_register_map[];

/* -- End: command Interface related structures -- */
#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif  /* #ifndef PHANTOM_CMD_H_DEFINED */