phantom_cmd.h

QPSK Tuner details, for conexant chipset.

#ifndef PHANTOM_CMD_H_DEFINED
#define PHANTOM_CMD_H_DEFINED

/* phantom_cmd.h */
/*+++ *******************************************************************\
*
*  Abstract:
*
*       Contains structure and definitions used internally by the 
*       Phantom Driver software.
*
*  Created: 3/30/2004
*
*  Author: Amarnath Puttur
*
*  Copyright and Disclaimer: 
*  
*     --------------------------------------------------------------- 
*     This software is provided "AS IS" without warranty of any kind, 
*     either expressed or implied, including but not limited to the 
*     implied warranties of noninfringement, merchantability and/or 
*     fitness for a particular purpose.
*     --------------------------------------------------------------- 
*   
*     Copyright (c) 2004 Conexant Systems, Inc. 
*     All rights reserved. 
*
\******************************************************************* ---*/

/***********************************************************************************
 * Include Phantom internal 
 ***********************************************************************************/
#include "phantom_globals.h"                /* Phantom Globals */


#ifdef __cplusplus
extern "C" {
#endif  /* __cplusplus */

/* -- Begin: command Interface related enumerations -- */
/***********************************************************************************
 * SB DPR ADDRESS MAP
 ***********************************************************************************/
/* == PHANTOM_LLF Write == */
#define PHANTOM_LLF_LOWER_OFFSET					    (0x00)
#define PHANTOM_LLF_LWRITE_OPCODE					    (PHANTOM_LLF_LOWER_OFFSET + 0x00)
#define PHANTOM_LLF_LWRITE_ARG_BASE					    (PHANTOM_LLF_LOWER_OFFSET + 0x01)
#define PHANTOM_LLF_LWRITE_CONTROL_BYTE				    (PHANTOM_LLF_LOWER_OFFSET + 0x1F) /* Writing to this address causes LLF execution */

#define PHANTOM_LLF_UPPER_OFFSET					    (PHANTOM_LLF_LWRITE_CONTROL_BYTE + 0x01)
#define PHANTOM_LLF_UWRITE_OPCODE					    (PHANTOM_LLF_UPPER_OFFSET + 0x00)
#define PHANTOM_LLF_UWRITE_ARG_BASE					    (PHANTOM_LLF_UPPER_OFFSET + 0x01)
#define PHANTOM_LLF_UWRITE_CONTROL_BYTE				    (PHANTOM_LLF_UPPER_OFFSET + 0x1F) /* Writing to this address causes an interrupt */


/* == Page0 == */
/* debug */
#define PHANTOM_P0_AVERAGE_ITER_ADDITIONAL_THRESH       (0x30)
#define PHANTOM_P0_PWR_MGMT_ENABLE                      (0x31)

/* --- Page0 Registers (byte/multibyte-level) --- */
#define PHANTOM_P0_CHIP_ID                              (0x94)
#define PHANTOM_P0_CHIP_VERSION                         (0x95)
#define PHANTOM_P0_SW_VERSION						    (0x96)

/* Channel parameter */
#define PHANTOM_P0_TUNER_FREQUENCY                      (0x97) /* [23:0] */
#define PHANTOM_P0_SYMBOL_RATE                          (0x9A) /* [15:8] */
#define PHANTOM_P0_MODCODE_PILOT_SI                     (0x9C) /* pilot[7], SI[6], MODCODE[5:0] */

/* Status */
#define PHANTOM_P0_LOCK_INDICATORS                      (0x9D) /* bits 4,3,2,1,0 */
#define PHANTOM_P0_ANALOG_AGC                           (0x9E) /* bits [7:0]  */
#define PHANTOM_P0_FREQ_OFFSET_KHZ                      (0x9F) /* bits [15:0] */
#define PHANTOM_P0_SYMBOL_RATE_OFFSET_KSPS              (0xA1) /* bits [15:0] */
#define PHANTOM_P0_ESNO_ESTIMATION_MSB                  (0xA3) /* [7:0] */

/* 0xA4 thru 0xB9 : Mongoose register mirror */

/* Interrupts */
#define PHANTOM_P0_INTERRUPTS_ENABLE					(0xBA)  /* bits 5:0   */
#define PHANTOM_P0_INTERRUPTS_PENDING				    (0xBB)  /* bits 5:0   */

/* LNB */
#define PHANTOM_P0_LNB_STATUS                           (0xBC)  /* bits 7:0   */
#define PHANTOM_P0_LNB_RX_ERROR                         (0xBD)  /* bits 7:0   */

#define PHANTOM_P0_LNB_REPLY_BYTE0                      (0xBE)  /* bits 7:0   */
#define PHANTOM_P0_LNB_REPLY_BYTE1                      (0xBF)  /* bits 7:0   */
#define PHANTOM_P0_LNB_REPLY_BYTE2                      (0xC0)  /* bits 7:0   */
#define PHANTOM_P0_LNB_REPLY_BYTE3                      (0xC1)  /* bits 7:0   */
#define PHANTOM_P0_LNB_REPLY_BYTE4                      (0xC2)  /* bits 7:0   */
#define PHANTOM_P0_LNB_REPLY_BYTE5                      (0xC3)  /* bits 7:0   */
#define PHANTOM_P0_LNB_REPLY_BYTE6                      (0xC4)  /* bits 7:0   */
#define PHANTOM_P0_LNB_REPLY_BYTE7                      (0xC5)  /* bits 7:0   */

/* Error Rate Measurement */
#define PHANTOM_P0_CORR_BIT_ERR_COUNT                   (0xC6)  /* bits 31:0  */
#define PHANTOM_P0_UNCORR_FRAME_ERR_COUNT               (0xCA)  /* bits 15:0  */
#define PHANTOM_P0_MEASUREMENT_COUNTER                  (0xCC)  /* bits 7:0   */
#define PHANTOM_P0_CRC_FRAME_ERR_COUNT                  (0xCD)  /* bits 15:0  */
#define PHANTOM_P0_CRC_MEASUREMENT_COUNTER              (0xCF)  /* bits 7:0   */

#define PHANTOM_P0_TUNER_ERR_CODE                       (0xD0)  /* bits 7:0   */
#define PHANTOM_P0_BIN_CYCLES_COUNTER                   (0xD1)  /* bits 7:0   */

/* Acquisition times */
#define PHANTOM_P0_ACQUISITION_TIME                     (0xD8)  /* bits 31:0 for now */

/* Free running counter */        
#define PHANTOM_P0_FREE_RUNNING_COUNTER				    (0xD4)  /* bits 7:0 */
#define PHANTOM_P0_ESNO_ESTIMATION_LSB                  (0xD5)  /* [7:0] */
#define PHANTOM_P0_LNB_REPLY_PARITY                     (0xD6)  /* [7:0] */
#define PHANTOM_P0_MISC_STATUS                          (0xD7)  /* bit0:RS error corr disable; 1:BCH err corr disable */
#define PHANTOM_P0_ESTIMATED_INPUT_POWER                (0xDA)  

#define PHANTOM_P0_BER_WIN_ADJUST                       (0xDB)
#define PHANTOM_P0_CRC_WIN_ADJUST                       (0xDD)

/* == Special control == */
#define PHANTOM_SC_ADDRESS_E0                           (0xE0)
#define PHANTOM_SC_ADDRESS_E1                           (0xE1)
#define PHANTOM_SC_CLK_INV                              (0xE2)
#define PHANTOM_SC_AFE_CNTL0                            (0xE3)
#define PHANTOM_SC_AFE_CNTL1                            (0xE4)
#define PHANTOM_SC_AFE_CNTL2                            (0xE5)
#define PHANTOM_SC_8051_MBIST_SEL                       (0xE6)
#define PHANTOM_SC_8051_MBIST_CNTL                      (0xE7)
#define PHANTOM_SC_ADDRESS_E8                           (0xE8)

#define PHANTOM_SC_TUNER_SB_REPEATER		            (0xE9) // Phantom (write-only)

#define PHANTOM_SC_8051_MBIST_STATUS                    (0xE9) // (read-only)
#define PHANTOM_SC_SHUT_CLK_CNTL                        (0xEA) 
#define PHANTOM_SC_TBUS_PINS_CNTL                       (0xEB) 
#define PHANTOM_SC_8051_TBUS_CNTL                       (0xEC)
#define PHANTOM_SC_ADDRESS_ED                           (0xED)
#define PHANTOM_SC_ADDRESS_EE                           (0xEE)
#define PHANTOM_SC_SER_GEN                              (0xEF)
#define PHANTOM_SC_RESET_CNTL                           (0xF0)
#define PHANTOM_SC_PLL_SPMP                             (0xF1)
#define PHANTOM_SC_PLL_SDIV                             (0xF2)
#define PHANTOM_SC_PLL_CLK_DIV_CONTROL                  (0xF3)

/* Load code/data */
#define PHANTOM_SC_DOWNLOAD_CONTROL                     (0xF4) 
#define PHANTOM_SC_ADDRESS_LOW				            (0xF5) 
#define PHANTOM_SC_ADDRESS_HIGH			                (0xF6) 
#define PHANTOM_SC_DATA					                (0xF7) 

#define PHANTOM_SC_PLL_LCLK_REG                         (0xF8)

#define PHANTOM_SC_ADC_MODE_SELECT                      (0xF9)
#define PHANTOM_SC_MICRO_OUT_DATA_LSB                   (0xFA)
#define PHANTOM_SC_MICRO_OUT_DATA_MSB                   (0xFB)

/* GPIO */
#define PHANTOM_SC_GPIO_DIRECTION                       (0xFC)  /* addr 252 */
#define PHANTOM_SC_GPIO_OUTPUTS                         (0xFC)  /* addr 252 */
#define PHANTOM_SC_GPIO_INPUTS                          (0xFD)  /* addr 253 */

/* Chip ID and Version */
#define PHANTOM_SC_CHIP_VERSION			                (0xFE)
#define PHANTOM_SC_CHIP_TYPE				            (0xFF)  /* Chip ID */


/**********************************************************************************
 * Status Register bit-fields (read/write)
 *
 * CAUTION!!! Please make sure the order of constants match the register map columns 
 * structure. The constant values should be in ascending order and in increments of 1.
 * Enums can be 8-bits wide on some platforms. Safe to use #defines.
 *
 **********************************************************************************/ 
/* === Special control bit-fields === */
/* Chip information */
#define PHANTOM_SC_FE_CHIP_VERSION						(0x0000)	                         /* address 0xFE [7:0] R */     
#define PHANTOM_SC_FF_CHIP_TYPE							(PHANTOM_SC_FE_CHIP_VERSION + 0x0001)	     /* address 0xFF [7:0] R */ 

/* GPIO */
#define PHANTOM_SC_FC_GPIO_DIRECTION                    (PHANTOM_SC_FF_CHIP_TYPE + 0x0001)           /* address 0xFC [7:4] W/R*/
#define PHANTOM_SC_FC_GPIO_OUTPUTS                      (PHANTOM_SC_FC_GPIO_DIRECTION + 0x0001)      /* address 0xFC [3:0] W/R*/
#define PHANTOM_SC_FD_GPIO_INPUTS                       (PHANTOM_SC_FC_GPIO_OUTPUTS + 0x0001)        /* address 0xFD [4:0] W/R*/

/* ADC Mode select */
#define PHANTOM_SC_F9_ADC_MODE_SEL                      (PHANTOM_SC_FD_GPIO_INPUTS + 0x0001)         /* address 0xF9 [0] W/R */

#define PHANTOM_SC_F8_PLL_LCLK_DIV                      (PHANTOM_SC_F9_ADC_MODE_SEL + 0x0001)        /* address 0xF8 [2:0] W/R */

/* Load code/data */
#define PHANTOM_SC_F4_DOWNLOAD_CONTROL					(PHANTOM_SC_F8_PLL_LCLK_DIV + 0x0001)        /* address 0xF4 [7:0], W */

/* PLL control registers */
#define PHANTOM_SC_F1_PLL_SPMP                          (PHANTOM_SC_F4_DOWNLOAD_CONTROL + 0x0001)	 /* address 0xF1 [7:0],   W */
#define PHANTOM_SC_F2_PLL_SDIV						    (PHANTOM_SC_F1_PLL_SPMP + 0x0001)	         /* address 0xF2 [7:0],   W */

/* Dividers */