📄 asymspwm.asm
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****************************************************************************
* File name : asymspwm.asm *
****************************************************************************
.title "asymspwm"
.include "2407.h"
.include "vector.h"
.def _c_int0
;----------------------定义变量---------------------------------------------
.bss temp1,1
.bss temp2,1
.bss temp3,1
.bss temp4,1
.bss temp5,1
.bss temp6,1
.bss temp7,1
.bss temp8,1
.bss temp9,1
.bss temp10,1
.bss temp11,1
.bss temp12,1
.bss period_flag,1 ; period start flag
.bss S_W,1 ; set angular speed: D11
.bss T_sample,1 ; sampling period: D-9
.bss theta_360,1 ; D3 360
.bss THETAH_1,1 ; D3, angular position higher word
.bss THETAL_1,1 ; angular position lower word
.bss THETAH_2,1 ; D3, angular position higher word
.bss THETAL_2,1 ; angular position lower word
.bss theta_r_1,1 ; rounded THETAH
.bss theta_r_2,1 ; rounded THETAH
.bss theta_i,1 ; D11, theta to index for sine table
.bss index_1,1 ; D15, index to sine table
.bss index_2,1 ; D15, index to sine table
.bss sin_theta,1 ; sin(THETA): D1
.bss SIN_1st,1 ; beginning of sin table
.bss vref,1 ;
.bss one,1
;-------------------------------------------------------------------
; Peripheral Registers and constants of TMS320C240
;-------------------------------------------------------------------
ST0 .set 0 ; status register ST0
ST1 .set 1 ; status regsiter ST1
wd_rst_1 .set 55h ; watchdog timer reset strings
wd_rst_2 .set 0aah ;
;---------------------Variables in B2-------------------------------
ST0_SAVE .set 0060h
ST1_SAVE .set 0061h
ACCH .set 0062h
ACCL .set 0063h
;---------------------Program parameters--------------------------------
;T1_period_ .set 19048 ; Tp = 2*19048*25nS=952uS => Fp = 1050Hz
;T3_period_ .set 19048 ;
;T_sample_ .set 15978; D-9, Fs=1050kHz
;theta_i_ .set 7334 ; D9 720/2*pi
**********************************************************
.text ;(program start)
********************************************************************
** Start of main body of code **
********************************************************************
_c_int0
SETC INTM ; disable all interrupt except Reset
CLRC CNF
********************************************************************
** System configuration **
********************************************************************
; Point at Sys Module reg page 0
LDP #0E0h ;7000H
SPLK #006fh, WDCR ;(0x7029) kick off the WD
* bits 15-8 0-0: Reserved
* bit 7 0: WD flag
* bit 6 1: WD Disable(Only when WD OVERRIDE bit in SCSR2 set to 1) .
* bits 5-3 101: must be 101 for normal operation,else system reset is aserted.
* bits 2-0 111: WD prescale is x/64 (110-x/32)
SPLK #wd_rst_1,WDKEY
SPLK #wd_rst_2,WDKEY
; Set the system control & status regs.
SPLK #00ddh,SCSR1;(0x7018)
* bit 15 0: reserved
* bit 14 0: CLKSRC clk out pin select(0-CPU CLK and 1-WDCLK)
* bits 13-12 00: low power mode select
* bits 11-9 000: CLKOUT prescale select(4xFin=4*10MHz=40MHz)
* bit 8 0: reserved
* bit 7 1: CLK enable for ADC
* bit 6 1: CLK enable for SCI
* bit 5 0: CLK disable for SPI
* bit 4 1: CLK enable for CAN
* bit 3 1: CLK disable for EVB
* bit 2 1: CLK disable for EVA
* bit 1 0: reserved
* bit 0 1: illegal address detect (write 1 to the bit to clear it,or will cause NMI)
LDP #0E1h ; Point at Sys Module reg page 1
SPLK #3fdbh,MCRA
* bit 15 0: 0-IOPB7, 1-TCLKINA
* bit 14 0: 0-IOPB6, 1-TDIRA
* bit 13 1: 0-IOPB5, 1-T2PWM/T2CMP
* bit 12 1: 0-IOPB4, 1-T1PWM/T1CMP
* bit 11 1: 0-IOPB3, 1-PWM6
* bit 10 1: 0-IOPB2, 1-PWM5
* bit 9 1: 0-IOPB1, 1-PWM4
* bit 8 1: 0-IOPB0, 1-PWM3
* bit 7 1: 0-IOPA7, 1-PWM2
* bit 6 1: 0-IOPA6, 1-PWM1
* bit 5 0: 0-IOPA5, 1-CAP3
* bit 4 1: 0-IOPA4, 1-CAP2/QEP2
* bit 3 1: 0-IOPA3, 1-CAP1/QEP1
* bit 2 0: 0-IOPA2, 1-XINT1
* bit 1 1: 0-IOPA1, 1-SCIRXD
* bit 0 1: 0-IOPA0, 1-SCITXD
SPLK #0fec2h,MCRB
* bit 15 1: 0-reserved, 1-TMS2
* bit 14 1: 0-reserved, 1-TMS
* bit 13 1: 0-reserved, 1-TDO
* bit 12 1: 0-reserved, 1-TDI
* bit 11 1: 0-reserved, 1-TCK
* bit 10 1: 0-reserved, 1-EMU1
* bit 9 1: 0-reserved, 1-EMU0
* bit 8 0: 0-IOPD0, 1-XINT2/ADCSOC
* bit 7 1: 0-IOPC7, 1-CANRX
* bit 6 1: 0-IOPC6, 1-CANTX
* bit 5 0: 0-IOPC5, 1-SPISTE
* bit 4 0: 0-IOPC4, 1-SPICLK
* bit 3 0: 0-IOPC3, 1-SPISOMI
* bit 2 0: 0-IOPC2, 1-SPISIMO
* bit 1 0: 0-IOPC1, 1-BIO
* bit 0 0: 0-IOPC0, 1-WR
SPLK #0dffh,MCRC
* bit 15 0: reserved
* bit 14 0: 0-IOPF6, 1-reserved
* bit 13 0: 0-IOPF5, 1-TCLKINB
* bit 12 0: 0-IOPF4, 1-TDIRB
* bit 11 1: 0-IOPF3, 1-T4PWM/T4CMP
* bit 10 1: 0-IOPF2, 1-T3PWM/P3CMP
* bit 9 0: 0-IOPF1, 1-CAP6
* bit 8 1: 0-IOPF0, 1-CAP5/QEP4
* bit 7 1: 0-IOPE7, 1-CAP4/QEP3
* bit 6 1: 0-IOPE6, 1-PWM12
* bit 5 1: 0-IOPE5, 1-PWM11
* bit 4 1: 0-IOPE4, 1-PWM10
* bit 3 1: 0-IOPE3, 1-PWM9
* bit 2 1: 0-IOPE2, 1-PWM8
* bit 1 1: 0-IOPE1, 1-PWM7
* bit 0 1: 0-IOPE0, 1-CLKOUT
;-----------------------------------------------------------------------
;Enable interrupts
;-----------------------------------------------------------------------
LDP #0
SPLK #0FFH,IFR ;Clear all core interrupt flags
SPLK #03H, IMR ;Unmask INT1,INT2
LDP #232
SPLK #0FFFFH,EVAIFRA ;清事件管理器A所有中断标志
SPLK #0FFFFH,EVAIFRB
SPLK #0FFFFH,EVAIFRC
SPLK #0201H,EVAIMRA ;开T1下溢中断
SPLK #0000H,EVAIMRB
SPLK #0000H,EVAIMRC
LDP #0EAh
SPLK #0FFFFH,EVBIFRA ;清事件管理器B所有中断标志
SPLK #0FFFFH,EVBIFRB
SPLK #0FFFFH,EVBIFRC
SPLK #0001H,EVBIMRA ;
SPLK #0000H,EVBIMRB
SPLK #0000H,EVBIMRC
********************************************************************
** Initialize variables **
********************************************************************
; Point to B1 page 0
LDP #6
SPLK #1,one ; +1 => one
SPLK #1678,T_sample; sampling period,Q24格式
SPLK #0,THETAL_1 ; theta low byte
SPLK #0,THETAH_1 ; theta high byte
SPLK #346dh,THETAL_2 ; theta low byte
SPLK #0h,THETAH_2 ; theta high byte
splk #0,theta_r_1
splk #0,theta_r_2
; Init conversion ratio from theta to index for sine table
splk #7334,theta_i ; D0
; Init table 1st and last entries and table poiter
SPLK #TB_S_,SIN_1st
;-----------------------------------------------------------------------
;Initialize EVA,EVB
;-----------------------------------------------------------------------
LDP #232
SPLK #2000,T1PR ;
SPLK #0,T1CNT
SPLK #0,CMPR1 ;初试占空比初值 0%
SPLK #0,CMPR2
SPLK #0,CMPR3
SPLK #0000011001100110B,ACTRA ;
* bits 15 0: Dir = CCW (n/c)
* bits 14-12 000: D2D1D0 = 000 (n/c)
* bits 11-10 10: PWM6/CMP6 active high
* bits 9-8 01: PWM5/CMP5 active low
* bits 7-6 10: PWM4/CMP4 active high
* bits 5-4 01: PWM3/CMP3 active low
* bits 3-2 10: PWM2/CMP2 active high
* bits 1-0 01: PWM1/CMP1 active low
SPLK #02F4h,DBTCONA ;
* bits 15-12 reserved
* bits 11-8 0010: deadband period (32*2*25nS=1.6uS)
* bit 7 1: enable deadband for compare unit3 (PWM5/6)
* bit 6 1: enable deadband for compare unit2 (PWM3/4)
* bit 5 1: enable deadband for compare unit1 (PWM1/2)
* bits 4-2 101: deadband prescale /32
* bits 1-0 00: reserved
SPLK #1000001000000000B,COMCONA ;允许比较,下溢重载
* bit 15 1: Enable Compare/PWM operation
* bits 14-13 00: Load F. Comp. Registers underflow
* bit 12 0: Disable Space Vector PWM Mode
* bits 11-10 00: Load ACTR on underflow of GPt1
* bit 9 1: Enable Compare outputs
* bit 8 0: PDINTA STATUS
* bit 7-0 Reserved
LDP #234
SPLK #2000,T3PR
SPLK #0,T3CNT
SPLK #0,CMPR4
SPLK #0,CMPR5
SPLK #0,CMPR6
SPLK #0000011001100110B,ACTRB ;
* bits 15 0: Dir = CCW (n/c)
* bits 14-12 000: D2D1D0 = 000 (n/c)
* bits 11-10 10: PWM12/CMP6 active high
* bits 9-8 01: PWM11/CMP5 active low
* bits 7-6 10: PWM10/CMP4 active high
* bits 5-4 01: PWM9/CMP3 active low
* bits 3-2 10: PWM8/CMP2 active high
* bits 1-0 01: PWM7/CMP1 active low
SPLK #02F4h,DBTCONB ;
SPLK #1000001000000000B,COMCONB ;
* bit 15 1: Enable Compare/PWM operation
* bits 14-13 00: Load F. Comp. Registers underflow
* bit 12 0: Disable Space Vector PWM Mode
* bits 11-10 00: Load ACTR on underflow of GPt3
* bit 9 1: Enable Compare outputs
* bit 8 0: PDINTA STATUS
* bit 7-0 Reserved
SPLK #0000100001000010B,T3CON ;
* bits 15 0: FREE = 0
* bits 14 0: SOFT = 0
* bits 13 Reserved
* bits 12-11 01: continuous-up/dn count mode
* bits 10-8 000: Prescaler =x /1 x=CPU clock
* bit 7 0: Timer 2 use own TENABLE bit
* bit 6 1: enable Timer (counting operation)
* bits 5-4 00: Select internal CLK
* bits 3-2 10: Load GP Timer comp register immediately
* bit 1 0: GP Timer compare disabled
* bit 0 0: Timer 2 use own period register
LDP #232
SPLK #0000100001000010B,T1CON
* bits 15 0: FREE = 0
* bits 14 0: SOFT = 0
* bits 13 Reserved
* bits 12-11 01: continuous-up/dn count mode
* bits 10-8 000: Prescaler =x /1 x=CPU clock
* bit 7 0: Timer 2 use own TENABLE bit
* bit 6 1: enable Timer (counting operation)
* bits 5-4 00: Select internal CLK
* bits 3-2 10: Load GP Timer comp register immediately
* bit 1 0: GP Timer compare disabled
* bit 0 0: Timer 2 use own period register
CLRC INTM ;
********************************************************************
** Set sign extention and overflow modes **
********************************************************************
;SETC OVM ; Set overflow protect mode
;SETC SXM ; Set sign extention (allow) mode
********************************************************************
** Start of main loop **
********************************************************************
MAIN
ldp #6 ; point at B1 page 0
; Wait for sampling period start.
SPLK #0,period_flag ; Reset the flag if it is set
w_sample
LACC period_flag ; Load sampling period start flag
BZ w_sample ; Wait if not set
ldp #6
SPLK #0,period_flag ; Reset the flag if it is set
********************************************************************
** to get radian frequency S_W **
********************************************************************
ldp #6
splk #5027, S_W ; Q4 16*2*3.1416*50
splk #800, vref ; Q0 AM=0.8
********************************************************************
** Obtain theta (phase of Uout) through 32 bit integration **
********************************************************************
ldp #6
splk #6487h, theta_360 ;Q12
LT S_W ; D11
MPY T_sample ; D-9*D11=D(2+1)
PAC ; D3
ADDH THETAH_1 ;
ADDS THETAL_1 ;
SACH THETAH_1 ;
SACL THETAL_1 ; accumulate: D3+D3=D3
SUBH theta_360 ; compare with 2*pi: D3-D3=D3
BLEZ Theta_in_limit_1 ; continue if within limit
SACH THETAH_1 ; mod(2*pi, THETA) if not
Theta_in_limit_1
ZALH THETAH_1 ;
ADDS THETAL_1 ;
ADD one,15 ;
SACH theta_r_1 ; round up to upper 16 bits
LT S_W ; D11
MPY T_sample ; D-9*D11=D(2+1)
PAC ; D3
ADDH THETAH_2 ;
ADDS THETAL_2 ;
SACH THETAH_2 ;
SACL THETAL_2 ; accumulate: D3+D3=D3
SUBH theta_360 ; compare with 2*pi: D3-D3=D3
BLEZ Theta_in_limit_2 ; continue if within limit
SACH THETAH_2 ; mod(2*pi, THETA) if not
Theta_in_limit_2
ZALH THETAH_2 ;
ADDS THETAL_2 ;
ADD one,15 ;
SACH theta_r_2 ; round up to upper 16 bits
**************************************
lt theta_r_1 ; D3
mpy theta_i ; D3*D9=D13
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