ds26528.h

Sample driver code for Dallas DS26528 T1/E1 framer chip.

					/* TMS nor the driver, just passed */

	/* 
	 * MAX_DEVICES defines the number of devices (hardware chips) you have
	 * in your system.  If you have less than the number shown, change
	 * this to the lower number.  If you have more, you want to change this
	 * to the higher value. Since there is an interrupt service routine per 
	 * device, when you get a larger number than NCI_MAX_DEVICES,
	 * you need to add the additional interrupt service routines.  The
	 * code is set up to generate a #warning when this happens.
	 */
#define MAX_DEVICES 4

	/* The following define controls if the standard CLIB functions
	 * memset and memcpy are used by the driver or
	 * the driver uses its own local routine for these functions.
	 * By default, the standard CLIB functions are used.
	 */
#undef USE_OWN_DRV_MEMLIB

/* -------------------------------------------------------------------------- */
/* -------------------------------------------------------------------------- */
/* Chip Level CUSTOMIZATION Section
 * This set of defines control the global part of the driver.
 */

#define MAX_RESET_WAIT		0xfffff	/* Max Wait before error */

/* See GTCR1 Register 0F0H */
#define RLOFLTS_SELECT		0	/* 0 = RLOF/LOTCX pin = LOF */
					/* 1 = RLOF/LOTCX pin = LOC */

/* See GFCR Register 0F1H */
#define RCHBCS_SELECT		0	/* 0 = RCHBLK/CLK pins = RCHBLK */
					/* 1 = RCHBLK/CLK pins = RCHCLK */

#define TCHBCS_SELECT		0	/* 0 = TCHBLK/CLK pins = TCHBLK */
					/* 1 = TCHBLK/CLK pins = TCHCLK */

#define RFMSS_SELECT		0	/* 0 = RF/RMSYCC pins = RFSYNC */
					/* 1 = RF/RMSYCC pins = RMSYNC */

#define RLOSSFS_SELECT		0	/* 0 = RLOS/RSIGF pins = RLOS */
					/* 1 = RLOS/RSIGF pins = RSIGF */

#define BACKPLANE_CLOCK		0	/* BPCLK Frequency */
					/* 0 = 2.048 MHZ */
					/* 1 = 4.096 MHZ */
					/* 2 = 8.192 MHZ */
					/* 3 = 16.384 MHZ */

#define INTERLEAVE_MODE		0 	/* Interleave Bus Operation Mode */
					/* 0 = IBO mux disabled */
					/* 1 = 4.096 MHz (2 per) */
					/* 2 = 8.192 MHz (4 per) */
					/* 3 = 16.384 MHz (8 per) */

/* See GTCR2 Register 0F2H */
#define TSSYNIO_SELECT		1	/* 0 = TSSYNCIO pin is an input */
					/* 1 = TSSYNCIO pin is an 8Khz ouput */

#define LOS_SELECT		0 	/* 0 = LOS pins driven from Framer LOS*/
					/* 1 = LOS pins driven from LIU LOS */

/* See GTCCR Register 0F3H */
#define FREQUENCY_SELECT	0	/* See Master Period below */
					/* 0 = 2.048 Mhz Based */
					/* 1 = 1.544 Mhz Based */

#define MASTER_PERIOD		0	/* MCLK Frequency Base * multiplier */
					/* 0 = Base * 1 */
					/* 1 = Base * 2 */
					/* 2 = Base * 4 */
					/* 3 = Base * 8 */

#define BACKPLANE_REFERENCE	9	/* Reference clock */
					/* 0 = LIU RCLK 1 */
					/* 1 = LIU RCLK 2 */
					/* 2 = LIU RCLK 3 */
					/* 3 = LIU RCLK 4 */
					/* 4 = LIU RCLK 5 */
					/* 5 = LIU RCLK 6 */
					/* 6 = LIU RCLK 7 */
					/* 7 = LIU RCLK 8 */
					/* 8 = 1.544 MHZ from MCLK */
					/* 9 = 2.048 MHZ from MCLK */
					/* A = 1.544 MHZ from REFCLKIO */
					/* B = 2.048 MHZ from REFCLKIO */


#define BP_FREQUENCY_SELECT	0	/* Backplane FREQ */
					/* 0 = 2.048 Mhz Based */
					/* 1 = 1.544 Mhz Based */



/* See TCR3 Register 183H */
#define TX_UNIPOLAR		0	/* 0 = BIPOLAR Data transmitted */
					/* 1 = NRZ data transmitted at TPOS */

/* See RCR3 Register 083H */
#define RX_UNIPOLAR		0	/* 0 = BIPOLAR Data expected */
					/* 1 = NRZ data expected at RPOS */

/* See RCR1 Register 081H */
#define RESYNC_CRITERIA		0	/* 0 = Resync on OOF and LOS */
					/* 1 = Resync on OOF only */

#define SYNC_TIME		0	/* 0 = qualify in 10 bits */
					/* 1 = qualify in 24 bits */

/* See RCR2 Register 014H */
#define OOF_CRITERIA		0	/* 0 = 2/4 frame bits in error */
					/* 1 = 2/5 frame bits in error */	
					/* 2 = 2/6 frame bits in error */	
					/* 3 = 2/6 frame bits in error */

/* See RIOCR Register 084H */
#define RSYNC_MODE1		0	/* 0 = Frame mode */
					/* 1 = multiframer mode */

#define RSYNC_IO_SELECT		0	/* 0 = RSYNC is an output */
					/* 1 = RSYNC is an input */

#define RSYNC_SKIP		0	/* 0 = Output every multiframe */
					/* 1 = Output every other multiframe */

#define H100_MODE		0	/* 0 = Normal operation */
					/* 1 = RYSNC and TSSYNCIO are shifted */

#define RSYNC_INV		0	/* 0 = No inversion of RSYNC */
					/* 1 = Invert RSYNC */

#define RCLK_INV		0	/* 0 = No inversion of RCLK */
					/* 1 = Invert RCLK */

/* See RESCR Register 085H */
#define RX_ELASTIC_STORE_EN	1	/* 0 = RX elastic store bypassed */
					/* 1 = RX elastic store enabled */

#define RES_MIN_DELAY		0	/* 0 = Two frame depth */
					/* 1 = 32-bit depth */

#define RXS_ZONE_SEL		0	/* 0 = slip at 9 bytes or less */
					/* 1 = slip at 2 bytes or less */

#define GAP_CLOCK_EN		0	/* 0 = RCHCLK functions normally */
					/* 1 = Enable gapped bit clock */

#define RX_CHAN_FORMAT		0	/* 0 = 64 KBps all 8 bits */
					/* 1 = 56 KBps only 7 bits */


/* See ERCNT Register 086H */
#define LCV_SELECT		1	/* 0 = do not count EXZ */
					/* 1 = count EXZ */

#define MOS_COUNT_SELECT	0 	/* 0 = Count framing bit position errs*/
					/* 1 = Count multiframes out of SYNC */
					   
#define PCVCR_SELECT		1	/* 0 = only FT bit position errors */
					/* 1 = FS and FT bit position errors */

#define ERROR_ACU_MODE		0	/* 0 = Auto Update */
					/* 1 = Manual Update */

#define MANUAL_UPDATE_SEL	0	/* If manual update */
					/* 0 = use MECU bit */
					/* 1 = latch on LATCH_CNT signal */

#define ONE_SECOND_SEL		0	/* 0 = use internal 1 Sec timer */
					/* 1 = use external 1 Sec pin SEC_IN */

/* See RHFC Register 087H */
#define HIGH_WATER_MARK		1	/* 0 = 4 bytes */
					/* 1 = 16 bytes */
					/* 2 = 32 bytes */
					/* 3 = 48 butes */

/* See RIBOC Register 088H */
/* See TIBOC Register 088H */
#define DEVICE_ASSIGNMENT	0	/* 0 - 7 = device 1-8 on bus */

#define IBO_EN			0	/* 0 = Interleave Bus disabled */
					/* 1 = Interleave Bus Enabled */

#define IBO_SEL			0	/* 0 = Channel Interleave */
					/* 1 = Frame Interleave */

#define IBO_SIZE		0	/* 0 = 2 Devices on Bus */
					/* 1 = 4 Devices on Bus */
					/* 2 = 8 Devices on Bus */

/* See TIOCR Register 0184H */
#define TSYNC_MODE		0	/* 0 = Framer mode */
					/* 1 = multiframe mode */

#define TSYNC_DOUBLE_WIDE	0	/* 0 = no double wide pulse */
					/* 1 = pulse double wide in sig frames*/

#define TSYNC_IO		1	/* 0 = TSYNC is an input */
					/* 1 = TSYNC is an output */

#define TSSYNC_MODE		0	/* 0 = Framer mode */
					/* 1 = multiframe mode */

#define TSYNCIO_INV		0	/* 0 = do not invert TSSYNC */
					/* 1 = invert TSSYNC */

#define TSYNC_INV		0	/* 0 = do not invert TSYNC */
					/* 1 = invert TSYNC */

#define TCLK_INV		0	/* 0 = do not invert TCLK */
					/* 1 = invert TCLK */

					   
/* See TESCR Register 0185H */
#define TX_ELASTIC_STORE_EN	1	/* 0 = TX elastic store bypassed */
					/* 1 = TX elastic store enabled */

#define TES_MIN_DELAY		0	/* 0 = Two frame depth */
					/* 1 = 32-bit depth */

#define TXS_ZONE_SEL		0	/* 0 = slip at 9 bytes or less */
					/* 1 = slip at 2 bytes or less */

#define TDATA_EN		0	/* 0 = Normal Operation */
					/* 1 = TDATA pin is active */

#define TGAP_CLOCK_EN		0	/* 0 = TCHCLK functions normally */
					/* 1 = Enable gapped bit clock */

#define TX_CHAN_FORMAT		0	/* 0 = 64 KBps all 8 bits */
					/* 1 = 56 KBps only 7 bits */

/* See THFC Register 187H */
#define LOW_WATER_MARK		1	/* 0 = 4 bytes */
					/* 1 = 16 bytes */
					/* 2 = 32 bytes */
					/* 3 = 48 butes */

/* -------------------------------------------------------------------------- */
/* -------------------------------------------------------------------------- */
/* T1 CUSTOMIZATION Section
 * This set of defines control the T1 part of the driver.
 */

/* See RIOCR Register 084H */
#define RSYNC_MODE2_T1		0	/* 0 = do not pulse double wide */
					/* 1 = pulse double wide */

#define RSYNC_CLK_MODE_T1	0	/* 0 = RSYSCLK = 1.544 Mhz */
					/* 1 = RSYSCLK = 2.048 Mhz */

/* See ERCNT Register 086H */
#define UPDATE_SELECT_T1	0 	/* 0 = Update on one second */
					/* 1 = Update at 42ms */
					   	
/* See TIOCR Register 0184H */
#define TSYSCLK_MODE_T1		0	/* 0 = TSYSCLK is 1.544 Mhz */
					/* 1 = TSYSCLK is 2.048 * n */

					
/* -------------------------------------------------------------------------- */
/* -------------------------------------------------------------------------- */
/* E1 CUSTOMIZATION Section
 * This set of defines control the E1 part of the driver.
 */

#define SASI_OSTICKER		0	/* ID for SASI Ticker */
#define SASI_POLL_TICK		50	/* in milliseconds */

/* See RIOCR Register 084H */
#define RSYNC_MODE2_E1		0	/* 0 = Output CAS multiframe bounds */
					/* 1 = Output CRC4 multiframe bounds */

#define RSYNC_CLK_MODE_E1	1	/* 0 = RSYSCLK = 1.544 Mhz */
					/* 1 = RSYSCLK = 2.048 Mhz */

/* See ERCNT Register 086H */
#define UPDATE_SELECT_E1	0 	/* 0 = Update on one second */
					/* 1 = Update at 62.5ms */

/* See TIOCR Register 0184H */
#define TSYSCLK_MODE_E1		1	/* 0 = TSYSCLK is 1.544 Mhz */
					/* 1 = TSYSCLK is 2.048 * n */

/* See LTITSR Register 0x1001 */
#define TX_IMPEDANCE		0	/* 0 = 75 Ohm */
					/* 1 = 120 Ohm */

/* See LRISMR Register 0x1007 */
#define RX_IMPEDANCE		0	/* 0 = 75 Ohm */
					/* 1 = 120 Ohm */

/* ------------------------------------------------------------------------- */
/* -------------------------------------------------------------------------- */
/* LIU CUSTOMIZATION Section
 * This set of defines control the LIU part of the driver.
 */

/* See LTRCR Register 1000H */
#define JAT_DEPTH		0	/* 0 = 128 bit depth */
					/* 1 = 32 bit depth */

#define JAT_POSITION		1	/* 0 = RX path */
					/* 1 = TX path */
					/* 2-3 = JAT not used */

#define LOS_CRITERIA		0	/* 0 = Use G.775 criteria */
					/* 1 = Use ETSI (300233) criteria */

/* See LTITSR Register 1001H */
#define TXTERM_OFF		0	/* 0 = TX termination ON */
					/* 1 = TX termination OFF */

/* See LRISMR Register 1007H */
#define RXTERM_OFF		0	/* 0 = RX termination ON */
					/* 1 = RX termination OFF */


/* -------------------------------------------------------------------------- */
/* CUSTOMIZE HERE
 * This is where you should put your pound include line to include your
 * own file to customize the drivers.  The file will want the form of:
 * #undef the name you want to change
 * #define the name to the value you need
 */

/* pound include "customizations_for_NCI_CHIP_NAME.h" */


/* -------------------------------------------------------------------------- */
/* -------------------------------------------------------------------------- */
/* -------------------------------------------------------------------------- */
/* -------------------------------------------------------------------------- */
/*          You should not need to edit anything below this point.            */
/*          You should not need to edit anything below this point.            */
/*          You should not need to edit anything below this point.            */
/*          You should not need to edit anything below this point.            */
/*          You should not need to edit anything below this point.            */
/* -------------------------------------------------------------------------- */
/* -------------------------------------------------------------------------- */
/* -------------------------------------------------------------------------- */
/* -------------------------------------------------------------------------- */


#define MAX_T1_CHANNELS 8
#define MAX_E1_CHANNELS 8


/* -------------------------------------------------------------------------- */

#define MAX_GLOBAL_TICKERS 0

/*
 * MAX_GLOBAL_TICKERS defines the number of global ticker routines that are 
 * shared between each of the driver technologies.
 */

/* -------------------------------------------------------------------------- */
/* 
 * This section has some misc. defines 
 */

#ifndef NULL
	#define NULL ((void *)(0))
#endif

/* -------------------------------------------------------------------------- */
/*
 * This section contains the defines which are used by the differnt driver
 * files.
 */

/* Function Entry Points */
#define NCID_GDEVICEMAP _ds26528_GlobalDeviceMap
#define NCID_GDEVICEUNMAP _ds26528_GlobalDeviceUnMap
#define NCID_GRESET _ds26528_GlobalReset
#define NCID_GUNRESET _ds26528_GlobalUnReset
#define NCID_GHOOKISR _ds26528_GlobalHookIsr
#define NCID_GHOOKTICKER _ds26528_GlobalHookTicker
#define NCID_GTICKER _ds26528_GlobalTicker

/* -------------------------------------------------------------------------- */
/* 
 * This section defines the top level device strucucture for the device
 */

typedef enum _ds26528_tech_index {
	DRVR_IDX_T1 = (0),
	DRVR_IDX_E1 = (1),
	DRVR_IDX_END = 2
} NCID_TI; 

struct _ds26528_global {
	int onesec_hooked;
	unsigned long t1map;		/* Controls the T1 allocation */
	unsigned long e1map;		/* Controls the E1 allocation */
};

typedef struct _ds26528_Device {
	int init;			/* When 0, chip is not Mapped */
					/* When 1, chip is Mapped */
	int id;				/* Chip ID number */
	int mapCnt;			/* Number times chip has been mapped */
	int resetCnt;			/* Number of times chip has Global */
					/* reset called */
	void *BaseAdr;			/* Address of the chip */

					/* define the interrupt entry points */
	int (*tech_handlers[DRVR_IDX_END])();
	int isr_cnt;
	void *device_isr;		/* The actual ISR */

#if MAX_GLOBAL_TICKERS
	struct _tickers {
		int cnt;		/* number of times ticker allocated */
		void *handle;		/* Ticker handle */
		void (*tickerHandler[DRVR_IDX_END])
			(struct _ds26528_Device *, int ticker);
	} tickers[MAX_GLOBAL_TICKERS];
#endif /* MAX_GLOBAL_TICKERS */

	struct _ds26528_global chip;
} GDEVICE;

/* 
 * define the global level functions.  These functions may be called
 * from each driver component.
 */

extern int NCID_GDEVICEUNMAP(GDEVICE *d);
extern GDEVICE *NCID_GDEVICEMAP(void *baseaddr);
extern void NCID_GRESET(GDEVICE *d);
extern void NCID_GUNRESET(GDEVICE *d);
extern void NCID_GHOOKISR(GDEVICE *d, NCID_TI ti, int onoff, 
	void (*fooptr)(), void *LnPtr, void *isr);
extern void NCID_GHOOKTICKER(GDEVICE *d, NCID_TI ti, int ticker, int onoff,
	void (*fooptr)(), void *LnPtr, void *tech_handler);
extern void NCID_GRESOURCE(int res, int onoff,
	void *LnPtr, int fc, void *isr, int line);




#ifdef USE_OWN_DRV_MEMLIB
/*------------------------------------------------------------------------*/
/* Define the driver specific memset call so that we have a self
 * contained driver.
 */
static void drvMemset(void *p, unsigned char c, unsigned int len)
{

unsigned char *ucp;
unsigned int i;

	for(i = 0, ucp = (unsigned char *)(p) ; i < len ; i++) 
		*ucp++ = c;
}

/*------------------------------------------------------------------------*/
/* Define the driver specific memcpy call so that we have a self
 * contained driver.
 */
static void drvMemcpy(void *dest, void *src, unsigned int len)
{

unsigned char *sp = (unsigned char *)src;
unsigned char *dp = (unsigned char *)dest;
unsigned int i;

	for(i = 0; i < len ; i++) 
		*dp++ = *sp++;

}
#else

	#define drvMemset memset
	#define drvMemcpy memcpy

#endif	/* DRV_MEMLIB */


#if (defined(T1_DRIVER) && defined(DS26528T1)) || \
    (defined(E1_DRIVER) && (defined(DS26528E1) && (!defined(DS26528T1))))


/* -------------------------------------------------------------------------- */
/* -------------------------------------------------------------------------- */
/* 
 * Define the data structures that are required for the device.
 */

static GDEVICE gdevice[MAX_DEVICES];
static int gdevice_init = 0;



/* -------------------------------------------------------------------------- */
/* -------------------------------------------------------------------------- */
/* 
 * The Device Specific Routines are defined below.
 */


/* -------------------------------------------------------------------------- */
/* The _device_GlobalReset implements the device specific reset routine.
 * This routine gets call once when the first time any technology issues its
 * reset call.
 *
 * This routine will be called once, the firs time that a device is reset.
 * This routine should issue a soft reset to the device if it 
 * is capible, then intialize all the hardware register to the value it wants
 * to be for the driver.  The setup once and forget about hardware
 * registers should be done here.